79165 lines
5.9 MiB
79165 lines
5.9 MiB
; --------------------------------------------------------------------------------
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; @Title: AWR2944 On-Chip Peripherals
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; @Props: Released
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; @Author: KMB, ADR, KRZ, NEJ
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; @Changelog: 2021-08-30 KMB
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; 2021-12-14 ADR
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; 2022-04-26 KRZ
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; 2023-11-14 NEJ
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; @Manufacturer: TI - Texas Instruments
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; @Doc: Generated (TRACE32, build: 164583.), based on: awr2944.xml (Ver. 1)
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; @Core: Cortex-M4, Cortex-R5F, C66x
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; @Chip: AWR2944, AWR2944-HSM, AWR2944-HWA, AWR2944DSP
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perawr2944.per 17044 2023-11-21 16:23:45Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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sif (CORENAME()=="C66X")
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "Core Registers (c66x)"
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config 16. 8.
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width 0x0b
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tree.open "Cache"
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tree "L1P Cache"
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base d:0x01840000
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width 9.
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group.long 0x20++0x7 "L1P Cache Control Registers"
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line.long 0x00 "L1PCFG,L1P Configuration Register"
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bitfld.long 0x00 0.--2. " L1PMODE ,Size of the L1P cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
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line.long 0x04 "L1PCC,L1P Cache Control Register"
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bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1"
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bitfld.long 0x04 0. " OPER ,Controls the L1P freeze mode" "Disabled,Enabled"
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wgroup.long 0x4020++0x3
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line.long 0x00 "L1PIBAR,L1P Invalidate Base Address Register"
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hexmask.long 0x00 0.--31. 1. " L1PIBAR ,32-bit base address for block invalidation"
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group.long 0x4024++0x3
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line.long 0x00 "L1PIWC,L1P Invalidate Word Count"
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hexmask.long.word 0x00 0.--15. 1. " L1PIWC ,Word count for block invalidation"
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group.long 0x5028++0x3
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line.long 0x00 "L1PINV,L1P Invalidate Register"
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bitfld.long 0x00 0. " I ,Controls the global invalidation of L1P cache" "Normal,Invalidate"
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//width 13.
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//wgroup.long 0xD00++0x13 "Memory Protection Lock Registers"
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// line.long 0x00 "L1PMPLK0,Memory Protection Lock Register 0"
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// hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0"
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// line.long 0x04 "L1PMPLK1,Memory Protection Lock Register 1"
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// hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32"
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// line.long 0x08 "L1PMPLK2,Memory Protection Lock Register 2"
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// hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64"
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// line.long 0x0c "L1PMPLK3,Memory Protection Lock Register 3"
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// hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96"
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// line.long 0x10 "L1PMPLKCMD,Memory Protection Lock Command Register"
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// bitfld.long 0x10 2. " KEYR ,Reset status" "No effect,Reset"
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// bitfld.long 0x10 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked"
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// bitfld.long 0x10 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
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//rgroup.long 0xD14++0x3
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// line.long 0x00 "L1PMPLKSTAT,Memory Protection Lock Status Register"
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// bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged"
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base d:0x0184a000
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width 12.
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tree "Memory Page Protection Attribute Registers"
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group.long 0x640++0x3f
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line.long 0x0 "L1PMPPA16,Level 1 Memory Page Protection Attribute Register 16"
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bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x0 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x0 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x0 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User"
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line.long 0x4 "L1PMPPA17,Level 1 Memory Page Protection Attribute Register 17"
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bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x4 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x4 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x4 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User"
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line.long 0x8 "L1PMPPA18,Level 1 Memory Page Protection Attribute Register 18"
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bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x8 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x8 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x8 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User"
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line.long 0xC "L1PMPPA19,Level 1 Memory Page Protection Attribute Register 19"
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bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0xC 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0xC 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0xC 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User"
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line.long 0x10 "L1PMPPA20,Level 1 Memory Page Protection Attribute Register 20"
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bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x10 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x10 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x10 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User"
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line.long 0x14 "L1PMPPA21,Level 1 Memory Page Protection Attribute Register 21"
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bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x14 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x14 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x14 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User"
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line.long 0x18 "L1PMPPA22,Level 1 Memory Page Protection Attribute Register 22"
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bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x18 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x18 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x18 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User"
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line.long 0x1C "L1PMPPA23,Level 1 Memory Page Protection Attribute Register 23"
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bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x1C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User"
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line.long 0x20 "L1PMPPA24,Level 1 Memory Page Protection Attribute Register 24"
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bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x20 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x20 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x20 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User"
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line.long 0x24 "L1PMPPA25,Level 1 Memory Page Protection Attribute Register 25"
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bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x24 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x24 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x24 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User"
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line.long 0x28 "L1PMPPA26,Level 1 Memory Page Protection Attribute Register 26"
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bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
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bitfld.long 0x28 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
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bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
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textline " "
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bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor"
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bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor"
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bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
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textline " "
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bitfld.long 0x28 2. " UR ,User read access type" "Normal,User"
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bitfld.long 0x28 1. " UW ,User write access type" "Normal,User"
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bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User"
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line.long 0x2C "L1PMPPA27,Level 1 Memory Page Protection Attribute Register 27"
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bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
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bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
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bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
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textline " "
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bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
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bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
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bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
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textline " "
|
|
bitfld.long 0x2C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x30 "L1PMPPA28,Level 1 Memory Page Protection Attribute Register 28"
|
|
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x30 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x30 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x34 "L1PMPPA29,Level 1 Memory Page Protection Attribute Register 29"
|
|
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x34 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x34 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x38 "L1PMPPA30,Level 1 Memory Page Protection Attribute Register 30"
|
|
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x38 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x38 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x3C "L1PMPPA31,Level 1 Memory Page Protection Attribute Register 31"
|
|
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted"
|
|
bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User"
|
|
tree.end
|
|
width 11.
|
|
rgroup.long 0x400++0x7 "Memory Protection Fault Registers"
|
|
line.long 0x00 "L1PMPFAR,L1P Memory Protection Fault Address"
|
|
hexmask.long 0x00 0.--31. 1. " FA ,Fault Address"
|
|
line.long 0x04 "L1PMPFSR,L1P Memory Protection Fault Set Register"
|
|
hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of faulting requestor"
|
|
bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Local"
|
|
bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x04 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x04 1. " UW ,User write access type" "Normal,User"
|
|
group.long 0x408++0x3
|
|
line.long 0x00 "L1PMPFCLR,L1P Memory Protection Fault Clear"
|
|
bitfld.long 0x00 0. " MPFCLR ,Command to clear the L1DMPFAR and L1DMPFCR" "No effect,Clear"
|
|
AUTOINDENT.ON right tree
|
|
rgroup.long 0x6404++0x3 "Error Detection Registers"
|
|
line.long 0x0 "L1PEDSTAT,L1P Error Detection Status Register"
|
|
bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
|
|
bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True"
|
|
bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True"
|
|
bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True"
|
|
bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True"
|
|
group.long 0x6408++0x3
|
|
line.long 0x0 "L1PEDCMD, L1P Error Detection Command Register"
|
|
bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
|
|
bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable"
|
|
bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable"
|
|
rgroup.long 0x640C++0x3
|
|
line.long 0x0 "L1PEDADDR, L1P Error Detection Address Register"
|
|
hexmask.long.long 0x0 5.--31. 32. "ADDR,Contains the upper 27 bit of error location"
|
|
bitfld.long 0x0 0. "RAM,Location where error was detected" "L1P cache,L1P RAM"
|
|
AUTOINDENT.OFF
|
|
width 0xb
|
|
tree.end
|
|
tree "L1D Cache"
|
|
base d:0x01840000
|
|
width 10.
|
|
group.long 0x40++0x7 "L1D Cache Control Registers"
|
|
line.long 0x00 "L1DCFG,L1D Cache Configuration"
|
|
bitfld.long 0x00 0.--2. " L1DMODE ,Size of the L1D cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
|
|
line.long 0x04 "L1DCC,L1D Cache Control Register"
|
|
bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1"
|
|
bitfld.long 0x04 0. " OPER ,Controls the L1D freeze mode" "Disabled,Enabled"
|
|
wgroup.long 0x4030++0x3
|
|
line.long 0x00 "L1DWIBAR,L1D Writeback-Invalidated Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L1DWIBAR ,L1D Writeback-Invalidated Base Address"
|
|
group.long 0x4034++0x3
|
|
line.long 0x00 "L1DWIWC,L1D Writeback-Invalidated Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " L1DWIWC ,L1D Writeback-Invalidated Word Count"
|
|
wgroup.long 0x4040++0x3
|
|
line.long 0x00 "L1DWBAR,L1D Writeback Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L1DWBAR ,L1D Writeback Base Address"
|
|
group.long 0x4044++0x3
|
|
line.long 0x00 "L1DWWC,L1D Writeback Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " L1DWWC ,L1D Writeback Word Count"
|
|
wgroup.long 0x4048++0x3
|
|
line.long 0x00 "L1DIBAR,L1D Invalidate Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L1DIBAR ,L1D Invalidate Base Address"
|
|
group.long 0x404c++0x3
|
|
line.long 0x00 "L1DIWC,L1D Invalidate Word Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " L1DIWC ,L1D Invalidate Word Count"
|
|
group.long 0x5048++0x3
|
|
line.long 0x00 "L1DINV,L1D Invalidate Register"
|
|
bitfld.long 0x00 0. " I ,Controls the global invalidation of L1D cache" "Normal,Invalidate"
|
|
group.long 0x5040++0x3
|
|
line.long 0x00 "L1DWB,L1P Writeback Register"
|
|
bitfld.long 0x00 0. " C ,Controls the global writeback operation of L1D cache" "Normal,Write back"
|
|
group.long 0x5044++0x3
|
|
line.long 0x00 "L1DWBINV,L1D Writeback-Invalidate Register"
|
|
bitfld.long 0x00 0. " C ,Controls the global writeback-invalidate operation of L1D cache" "Normal,Invalidate"
|
|
width 11.
|
|
base d:0x0184a000
|
|
tree "Memory Protection Attribute Registers"
|
|
group.long 0xe40++0x3f
|
|
line.long 0x0 "MPPA16,Memory Protection Attribute Register"
|
|
bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x0 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x0 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x4 "MPPA17,Memory Protection Attribute Register"
|
|
bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x4 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x4 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x8 "MPPA18,Memory Protection Attribute Register"
|
|
bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x8 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x8 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0xC "MPPA19,Memory Protection Attribute Register"
|
|
bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0xC 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0xC 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x10 "MPPA20,Memory Protection Attribute Register"
|
|
bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x10 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x10 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x14 "MPPA21,Memory Protection Attribute Register"
|
|
bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x14 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x14 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x18 "MPPA22,Memory Protection Attribute Register"
|
|
bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x18 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x18 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x1C "MPPA23,Memory Protection Attribute Register"
|
|
bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x20 "MPPA24,Memory Protection Attribute Register"
|
|
bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x20 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x20 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x24 "MPPA25,Memory Protection Attribute Register"
|
|
bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x24 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x24 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x28 "MPPA26,Memory Protection Attribute Register"
|
|
bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x28 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x28 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x2C "MPPA27,Memory Protection Attribute Register"
|
|
bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x30 "MPPA28,Memory Protection Attribute Register"
|
|
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x30 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x30 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x34 "MPPA29,Memory Protection Attribute Register"
|
|
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x34 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x34 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x38 "MPPA30,Memory Protection Attribute Register"
|
|
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x38 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x38 1. " UW ,User write access type" "Normal,User"
|
|
line.long 0x3C "MPPA31,Memory Protection Attribute Register"
|
|
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User"
|
|
tree.end
|
|
base d:0x0184a000
|
|
width 10.
|
|
rgroup.long 0xc00++0x7 "Memory Protection Fault Registers"
|
|
line.long 0x00 "L1DMPFAR,Memory Protection Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " FA ,Fault Address"
|
|
line.long 0x04 "L1DMPFSR,Memory Protection Fault Set Register"
|
|
hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor"
|
|
bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor"
|
|
bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x04 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x04 1. " UW ,User write access type" "Normal,User"
|
|
group.long 0xc08++0x3
|
|
line.long 0x00 "L1DMPFCR,Memory Protection Fault Clear Register"
|
|
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Cleared"
|
|
width 13.
|
|
wgroup.long 0xd00++0xf "Memory Protection Lock Registers"
|
|
line.long 0x00 "L1DMPLK0,Level 1 Data Memory Protection Lock Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0"
|
|
line.long 0x04 "L1DMPLK1,Level 1 Data Memory Protection Lock Register 1"
|
|
hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32"
|
|
line.long 0x08 "L1DMPLK2,Level 1 Data Memory Protection Lock Register 2"
|
|
line.long 0x0c "L1DMPLK3,Level 1 Data Memory Protection Lock Register 3"
|
|
wgroup.long 0xd10++0x3
|
|
line.long 0x00 "L1DMPLKCMD,Level 1 Data Memory Protection Lock Command Register"
|
|
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
|
|
bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked"
|
|
bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
|
|
rgroup.long 0xd14++0x3
|
|
line.long 0x00 "L1DMPLKSTAT,Level 1 Data Memory Protection Lock Status Register"
|
|
bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged"
|
|
width 0xb
|
|
tree.end
|
|
tree "L2 Cache"
|
|
base d:0x01840000
|
|
width 9.
|
|
group.long 0x00++0x3 "L2 Cache Control Registers"
|
|
line.long 0x00 "L2CFG,L2 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--27. 1. " NUM_MM ,Number of megamodules minus one"
|
|
hexmask.long.byte 0x00 16.--19. 1. " MMID ,Contains the Megamodule ID number"
|
|
bitfld.long 0x00 9. " IP ,L1P global invalidate bit" "Normal,Invalidate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ID ,L1D global invalidate bit" "Normal,Invalidate"
|
|
bitfld.long 0x00 3. " L2CC ,Freeze mode" "Normal,Frozen"
|
|
bitfld.long 0x00 0.--2. " L2MODE ,Size of L2 cache" "Disabled,32K,64K,128K,256K,512K,1024K,Maximum"
|
|
wgroup.long 0x4000++0x3
|
|
line.long 0x00 "L2WBAR,L2 Writeback Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " L2WBAR ,L2 Writeback Base Address"
|
|
group.long 0x4004++0x3
|
|
line.long 0x00 "L2WWC,L2 Writeback Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " L2WWC ,L2 Writeback Word Count"
|
|
wgroup.long 0x4010++0x3
|
|
line.long 0x00 "L2WIBAR,L2 Writeback-Invalidate Base Address"
|
|
hexmask.long 0x00 0.--31. 1. " L2WIBAR ,L2 Writeback Invalidate Base Address"
|
|
group.long 0x4014++0x3
|
|
line.long 0x00 "L2WIWC,L2 Writeback Invalidate Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " L2WIWC ,L2 Writeback Invalidate Word Count"
|
|
wgroup.long 0x4018++0x3
|
|
line.long 0x00 "L2IBAR,L2 Invalidate Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " L2IBAR ,L2 Invalidate Base Address"
|
|
group.long 0x401c++0x3
|
|
line.long 0x00 "L2IWC,L2 Invalidate Word Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " L2IWC ,L2 Invalidate Word Count"
|
|
group.long 0x5000++0xb
|
|
line.long 0x00 "L2WB,L2 Writeback Register"
|
|
bitfld.long 0x00 0. " C ,Controls the global writeback operation of L2 cache" "Normal,Writeback"
|
|
line.long 0x04 "L2WBINV,L2 Writeback-Invalidate Register"
|
|
bitfld.long 0x04 0. " C ,Controls the global writeback-invalidate operation of L2 cache" "Normal,Writeback"
|
|
line.long 0x08 "L2INV,L2 Invalidate Register"
|
|
bitfld.long 0x08 0. " I ,Controls the global invalidation of L2 cache" "Normal,Invalidate"
|
|
tree "Memory Attribute Registers"
|
|
width 8.
|
|
base d:0x01848000
|
|
rgroup.long 0x00++0x2f
|
|
line.long 0x0 "MAR0,Memory Attribute Register 0"
|
|
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x4 "MAR1,Memory Attribute Register 1"
|
|
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x8 "MAR2,Memory Attribute Register 2"
|
|
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC "MAR3,Memory Attribute Register 3"
|
|
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x10 "MAR4,Memory Attribute Register 4"
|
|
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x14 "MAR5,Memory Attribute Register 5"
|
|
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x18 "MAR6,Memory Attribute Register 6"
|
|
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C "MAR7,Memory Attribute Register 7"
|
|
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x20 "MAR8,Memory Attribute Register 8"
|
|
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x24 "MAR9,Memory Attribute Register 9"
|
|
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x28 "MAR10,Memory Attribute Register 10"
|
|
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C "MAR11,Memory Attribute Register 11"
|
|
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
group.long 0x30++0x3cf
|
|
line.long 0x0 "MAR12,Memory Attribute Register 12"
|
|
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x4 "MAR13,Memory Attribute Register 13"
|
|
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x8 "MAR14,Memory Attribute Register 14"
|
|
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC "MAR15,Memory Attribute Register 15"
|
|
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x10 "MAR16,Memory Attribute Register 16"
|
|
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x14 "MAR17,Memory Attribute Register 17"
|
|
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x18 "MAR18,Memory Attribute Register 18"
|
|
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C "MAR19,Memory Attribute Register 19"
|
|
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x20 "MAR20,Memory Attribute Register 20"
|
|
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x24 "MAR21,Memory Attribute Register 21"
|
|
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x28 "MAR22,Memory Attribute Register 22"
|
|
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C "MAR23,Memory Attribute Register 23"
|
|
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x30 "MAR24,Memory Attribute Register 24"
|
|
bitfld.long 0x30 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x30 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x34 "MAR25,Memory Attribute Register 25"
|
|
bitfld.long 0x34 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x34 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x38 "MAR26,Memory Attribute Register 26"
|
|
bitfld.long 0x38 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x38 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C "MAR27,Memory Attribute Register 27"
|
|
bitfld.long 0x3C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x40 "MAR28,Memory Attribute Register 28"
|
|
bitfld.long 0x40 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x40 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x44 "MAR29,Memory Attribute Register 29"
|
|
bitfld.long 0x44 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x44 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x48 "MAR30,Memory Attribute Register 30"
|
|
bitfld.long 0x48 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x48 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x4C "MAR31,Memory Attribute Register 31"
|
|
bitfld.long 0x4C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x4C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x50 "MAR32,Memory Attribute Register 32"
|
|
bitfld.long 0x50 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x50 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x54 "MAR33,Memory Attribute Register 33"
|
|
bitfld.long 0x54 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x54 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x58 "MAR34,Memory Attribute Register 34"
|
|
bitfld.long 0x58 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x58 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x5C "MAR35,Memory Attribute Register 35"
|
|
bitfld.long 0x5C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x5C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x60 "MAR36,Memory Attribute Register 36"
|
|
bitfld.long 0x60 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x60 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x64 "MAR37,Memory Attribute Register 37"
|
|
bitfld.long 0x64 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x64 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x68 "MAR38,Memory Attribute Register 38"
|
|
bitfld.long 0x68 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x68 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x6C "MAR39,Memory Attribute Register 39"
|
|
bitfld.long 0x6C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x6C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x70 "MAR40,Memory Attribute Register 40"
|
|
bitfld.long 0x70 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x70 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x74 "MAR41,Memory Attribute Register 41"
|
|
bitfld.long 0x74 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x74 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x78 "MAR42,Memory Attribute Register 42"
|
|
bitfld.long 0x78 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x78 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x7C "MAR43,Memory Attribute Register 43"
|
|
bitfld.long 0x7C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x7C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x80 "MAR44,Memory Attribute Register 44"
|
|
bitfld.long 0x80 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x80 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x84 "MAR45,Memory Attribute Register 45"
|
|
bitfld.long 0x84 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x84 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x88 "MAR46,Memory Attribute Register 46"
|
|
bitfld.long 0x88 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x88 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x8C "MAR47,Memory Attribute Register 47"
|
|
bitfld.long 0x8C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x8C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x90 "MAR48,Memory Attribute Register 48"
|
|
bitfld.long 0x90 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x90 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x94 "MAR49,Memory Attribute Register 49"
|
|
bitfld.long 0x94 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x94 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x98 "MAR50,Memory Attribute Register 50"
|
|
bitfld.long 0x98 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x98 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x9C "MAR51,Memory Attribute Register 51"
|
|
bitfld.long 0x9C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x9C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xA0 "MAR52,Memory Attribute Register 52"
|
|
bitfld.long 0xA0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xA0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xA4 "MAR53,Memory Attribute Register 53"
|
|
bitfld.long 0xA4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xA4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xA8 "MAR54,Memory Attribute Register 54"
|
|
bitfld.long 0xA8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xA8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xAC "MAR55,Memory Attribute Register 55"
|
|
bitfld.long 0xAC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xAC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xB0 "MAR56,Memory Attribute Register 56"
|
|
bitfld.long 0xB0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xB0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xB4 "MAR57,Memory Attribute Register 57"
|
|
bitfld.long 0xB4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xB4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xB8 "MAR58,Memory Attribute Register 58"
|
|
bitfld.long 0xB8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xB8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xBC "MAR59,Memory Attribute Register 59"
|
|
bitfld.long 0xBC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xBC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC0 "MAR60,Memory Attribute Register 60"
|
|
bitfld.long 0xC0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC4 "MAR61,Memory Attribute Register 61"
|
|
bitfld.long 0xC4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xC8 "MAR62,Memory Attribute Register 62"
|
|
bitfld.long 0xC8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xC8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xCC "MAR63,Memory Attribute Register 63"
|
|
bitfld.long 0xCC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xCC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xD0 "MAR64,Memory Attribute Register 64"
|
|
bitfld.long 0xD0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xD0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xD4 "MAR65,Memory Attribute Register 65"
|
|
bitfld.long 0xD4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xD4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xD8 "MAR66,Memory Attribute Register 66"
|
|
bitfld.long 0xD8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xD8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xDC "MAR67,Memory Attribute Register 67"
|
|
bitfld.long 0xDC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xDC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xE0 "MAR68,Memory Attribute Register 68"
|
|
bitfld.long 0xE0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xE0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xE4 "MAR69,Memory Attribute Register 69"
|
|
bitfld.long 0xE4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xE4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xE8 "MAR70,Memory Attribute Register 70"
|
|
bitfld.long 0xE8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xE8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xEC "MAR71,Memory Attribute Register 71"
|
|
bitfld.long 0xEC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xEC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xF0 "MAR72,Memory Attribute Register 72"
|
|
bitfld.long 0xF0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xF0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xF4 "MAR73,Memory Attribute Register 73"
|
|
bitfld.long 0xF4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xF4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xF8 "MAR74,Memory Attribute Register 74"
|
|
bitfld.long 0xF8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xF8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0xFC "MAR75,Memory Attribute Register 75"
|
|
bitfld.long 0xFC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0xFC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x100 "MAR76,Memory Attribute Register 76"
|
|
bitfld.long 0x100 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x100 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x104 "MAR77,Memory Attribute Register 77"
|
|
bitfld.long 0x104 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x104 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x108 "MAR78,Memory Attribute Register 78"
|
|
bitfld.long 0x108 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x108 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x10C "MAR79,Memory Attribute Register 79"
|
|
bitfld.long 0x10C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x10C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x110 "MAR80,Memory Attribute Register 80"
|
|
bitfld.long 0x110 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x110 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x114 "MAR81,Memory Attribute Register 81"
|
|
bitfld.long 0x114 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x114 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x118 "MAR82,Memory Attribute Register 82"
|
|
bitfld.long 0x118 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x118 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x11C "MAR83,Memory Attribute Register 83"
|
|
bitfld.long 0x11C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x11C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x120 "MAR84,Memory Attribute Register 84"
|
|
bitfld.long 0x120 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x120 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x124 "MAR85,Memory Attribute Register 85"
|
|
bitfld.long 0x124 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x124 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x128 "MAR86,Memory Attribute Register 86"
|
|
bitfld.long 0x128 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x128 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x12C "MAR87,Memory Attribute Register 87"
|
|
bitfld.long 0x12C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x12C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x130 "MAR88,Memory Attribute Register 88"
|
|
bitfld.long 0x130 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x130 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x134 "MAR89,Memory Attribute Register 89"
|
|
bitfld.long 0x134 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x134 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x138 "MAR90,Memory Attribute Register 90"
|
|
bitfld.long 0x138 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x138 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x13C "MAR91,Memory Attribute Register 91"
|
|
bitfld.long 0x13C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x13C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x140 "MAR92,Memory Attribute Register 92"
|
|
bitfld.long 0x140 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x140 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x144 "MAR93,Memory Attribute Register 93"
|
|
bitfld.long 0x144 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x144 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x148 "MAR94,Memory Attribute Register 94"
|
|
bitfld.long 0x148 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x148 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x14C "MAR95,Memory Attribute Register 95"
|
|
bitfld.long 0x14C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x14C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x150 "MAR96,Memory Attribute Register 96"
|
|
bitfld.long 0x150 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x150 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x154 "MAR97,Memory Attribute Register 97"
|
|
bitfld.long 0x154 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x154 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x158 "MAR98,Memory Attribute Register 98"
|
|
bitfld.long 0x158 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x158 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x15C "MAR99,Memory Attribute Register 99"
|
|
bitfld.long 0x15C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x15C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x160 "MAR100,Memory Attribute Register 100"
|
|
bitfld.long 0x160 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x160 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x164 "MAR101,Memory Attribute Register 101"
|
|
bitfld.long 0x164 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x164 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x168 "MAR102,Memory Attribute Register 102"
|
|
bitfld.long 0x168 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x168 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x16C "MAR103,Memory Attribute Register 103"
|
|
bitfld.long 0x16C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x16C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x170 "MAR104,Memory Attribute Register 104"
|
|
bitfld.long 0x170 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x170 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x174 "MAR105,Memory Attribute Register 105"
|
|
bitfld.long 0x174 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x174 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x178 "MAR106,Memory Attribute Register 106"
|
|
bitfld.long 0x178 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x178 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x17C "MAR107,Memory Attribute Register 107"
|
|
bitfld.long 0x17C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x17C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x180 "MAR108,Memory Attribute Register 108"
|
|
bitfld.long 0x180 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x180 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x184 "MAR109,Memory Attribute Register 109"
|
|
bitfld.long 0x184 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x184 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x188 "MAR110,Memory Attribute Register 110"
|
|
bitfld.long 0x188 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x188 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x18C "MAR111,Memory Attribute Register 111"
|
|
bitfld.long 0x18C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x18C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x190 "MAR112,Memory Attribute Register 112"
|
|
bitfld.long 0x190 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x190 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x194 "MAR113,Memory Attribute Register 113"
|
|
bitfld.long 0x194 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x194 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x198 "MAR114,Memory Attribute Register 114"
|
|
bitfld.long 0x198 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x198 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x19C "MAR115,Memory Attribute Register 115"
|
|
bitfld.long 0x19C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x19C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1A0 "MAR116,Memory Attribute Register 116"
|
|
bitfld.long 0x1A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1A4 "MAR117,Memory Attribute Register 117"
|
|
bitfld.long 0x1A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1A8 "MAR118,Memory Attribute Register 118"
|
|
bitfld.long 0x1A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1AC "MAR119,Memory Attribute Register 119"
|
|
bitfld.long 0x1AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1B0 "MAR120,Memory Attribute Register 120"
|
|
bitfld.long 0x1B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1B4 "MAR121,Memory Attribute Register 121"
|
|
bitfld.long 0x1B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1B8 "MAR122,Memory Attribute Register 122"
|
|
bitfld.long 0x1B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1BC "MAR123,Memory Attribute Register 123"
|
|
bitfld.long 0x1BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C0 "MAR124,Memory Attribute Register 124"
|
|
bitfld.long 0x1C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C4 "MAR125,Memory Attribute Register 125"
|
|
bitfld.long 0x1C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1C8 "MAR126,Memory Attribute Register 126"
|
|
bitfld.long 0x1C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1CC "MAR127,Memory Attribute Register 127"
|
|
bitfld.long 0x1CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1D0 "MAR128,Memory Attribute Register 128"
|
|
bitfld.long 0x1D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1D4 "MAR129,Memory Attribute Register 129"
|
|
bitfld.long 0x1D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1D8 "MAR130,Memory Attribute Register 130"
|
|
bitfld.long 0x1D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1DC "MAR131,Memory Attribute Register 131"
|
|
bitfld.long 0x1DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1E0 "MAR132,Memory Attribute Register 132"
|
|
bitfld.long 0x1E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1E4 "MAR133,Memory Attribute Register 133"
|
|
bitfld.long 0x1E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1E8 "MAR134,Memory Attribute Register 134"
|
|
bitfld.long 0x1E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1EC "MAR135,Memory Attribute Register 135"
|
|
bitfld.long 0x1EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1F0 "MAR136,Memory Attribute Register 136"
|
|
bitfld.long 0x1F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1F4 "MAR137,Memory Attribute Register 137"
|
|
bitfld.long 0x1F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1F8 "MAR138,Memory Attribute Register 138"
|
|
bitfld.long 0x1F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x1FC "MAR139,Memory Attribute Register 139"
|
|
bitfld.long 0x1FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x1FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x200 "MAR140,Memory Attribute Register 140"
|
|
bitfld.long 0x200 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x200 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x204 "MAR141,Memory Attribute Register 141"
|
|
bitfld.long 0x204 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x204 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x208 "MAR142,Memory Attribute Register 142"
|
|
bitfld.long 0x208 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x208 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x20C "MAR143,Memory Attribute Register 143"
|
|
bitfld.long 0x20C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x20C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x210 "MAR144,Memory Attribute Register 144"
|
|
bitfld.long 0x210 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x210 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x214 "MAR145,Memory Attribute Register 145"
|
|
bitfld.long 0x214 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x214 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x218 "MAR146,Memory Attribute Register 146"
|
|
bitfld.long 0x218 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x218 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x21C "MAR147,Memory Attribute Register 147"
|
|
bitfld.long 0x21C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x21C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x220 "MAR148,Memory Attribute Register 148"
|
|
bitfld.long 0x220 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x220 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x224 "MAR149,Memory Attribute Register 149"
|
|
bitfld.long 0x224 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x224 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x228 "MAR150,Memory Attribute Register 150"
|
|
bitfld.long 0x228 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x228 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x22C "MAR151,Memory Attribute Register 151"
|
|
bitfld.long 0x22C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x22C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x230 "MAR152,Memory Attribute Register 152"
|
|
bitfld.long 0x230 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x230 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x234 "MAR153,Memory Attribute Register 153"
|
|
bitfld.long 0x234 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x234 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x238 "MAR154,Memory Attribute Register 154"
|
|
bitfld.long 0x238 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x238 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x23C "MAR155,Memory Attribute Register 155"
|
|
bitfld.long 0x23C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x23C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x240 "MAR156,Memory Attribute Register 156"
|
|
bitfld.long 0x240 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x240 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x244 "MAR157,Memory Attribute Register 157"
|
|
bitfld.long 0x244 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x244 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x248 "MAR158,Memory Attribute Register 158"
|
|
bitfld.long 0x248 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x248 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x24C "MAR159,Memory Attribute Register 159"
|
|
bitfld.long 0x24C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x24C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x250 "MAR160,Memory Attribute Register 160"
|
|
bitfld.long 0x250 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x250 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x254 "MAR161,Memory Attribute Register 161"
|
|
bitfld.long 0x254 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x254 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x258 "MAR162,Memory Attribute Register 162"
|
|
bitfld.long 0x258 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x258 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x25C "MAR163,Memory Attribute Register 163"
|
|
bitfld.long 0x25C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x25C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x260 "MAR164,Memory Attribute Register 164"
|
|
bitfld.long 0x260 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x260 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x264 "MAR165,Memory Attribute Register 165"
|
|
bitfld.long 0x264 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x264 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x268 "MAR166,Memory Attribute Register 166"
|
|
bitfld.long 0x268 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x268 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x26C "MAR167,Memory Attribute Register 167"
|
|
bitfld.long 0x26C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x26C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x270 "MAR168,Memory Attribute Register 168"
|
|
bitfld.long 0x270 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x270 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x274 "MAR169,Memory Attribute Register 169"
|
|
bitfld.long 0x274 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x274 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x278 "MAR170,Memory Attribute Register 170"
|
|
bitfld.long 0x278 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x278 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x27C "MAR171,Memory Attribute Register 171"
|
|
bitfld.long 0x27C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x27C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x280 "MAR172,Memory Attribute Register 172"
|
|
bitfld.long 0x280 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x280 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x284 "MAR173,Memory Attribute Register 173"
|
|
bitfld.long 0x284 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x284 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x288 "MAR174,Memory Attribute Register 174"
|
|
bitfld.long 0x288 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x288 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x28C "MAR175,Memory Attribute Register 175"
|
|
bitfld.long 0x28C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x28C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x290 "MAR176,Memory Attribute Register 176"
|
|
bitfld.long 0x290 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x290 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x294 "MAR177,Memory Attribute Register 177"
|
|
bitfld.long 0x294 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x294 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x298 "MAR178,Memory Attribute Register 178"
|
|
bitfld.long 0x298 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x298 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x29C "MAR179,Memory Attribute Register 179"
|
|
bitfld.long 0x29C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x29C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2A0 "MAR180,Memory Attribute Register 180"
|
|
bitfld.long 0x2A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2A4 "MAR181,Memory Attribute Register 181"
|
|
bitfld.long 0x2A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2A8 "MAR182,Memory Attribute Register 182"
|
|
bitfld.long 0x2A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2AC "MAR183,Memory Attribute Register 183"
|
|
bitfld.long 0x2AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2B0 "MAR184,Memory Attribute Register 184"
|
|
bitfld.long 0x2B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2B4 "MAR185,Memory Attribute Register 185"
|
|
bitfld.long 0x2B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2B8 "MAR186,Memory Attribute Register 186"
|
|
bitfld.long 0x2B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2BC "MAR187,Memory Attribute Register 187"
|
|
bitfld.long 0x2BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C0 "MAR188,Memory Attribute Register 188"
|
|
bitfld.long 0x2C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C4 "MAR189,Memory Attribute Register 189"
|
|
bitfld.long 0x2C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2C8 "MAR190,Memory Attribute Register 190"
|
|
bitfld.long 0x2C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2CC "MAR191,Memory Attribute Register 191"
|
|
bitfld.long 0x2CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2D0 "MAR192,Memory Attribute Register 192"
|
|
bitfld.long 0x2D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2D4 "MAR193,Memory Attribute Register 193"
|
|
bitfld.long 0x2D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2D8 "MAR194,Memory Attribute Register 194"
|
|
bitfld.long 0x2D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2DC "MAR195,Memory Attribute Register 195"
|
|
bitfld.long 0x2DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2E0 "MAR196,Memory Attribute Register 196"
|
|
bitfld.long 0x2E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2E4 "MAR197,Memory Attribute Register 197"
|
|
bitfld.long 0x2E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2E8 "MAR198,Memory Attribute Register 198"
|
|
bitfld.long 0x2E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2EC "MAR199,Memory Attribute Register 199"
|
|
bitfld.long 0x2EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2F0 "MAR200,Memory Attribute Register 200"
|
|
bitfld.long 0x2F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2F4 "MAR201,Memory Attribute Register 201"
|
|
bitfld.long 0x2F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2F8 "MAR202,Memory Attribute Register 202"
|
|
bitfld.long 0x2F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x2FC "MAR203,Memory Attribute Register 203"
|
|
bitfld.long 0x2FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x2FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x300 "MAR204,Memory Attribute Register 204"
|
|
bitfld.long 0x300 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x300 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x304 "MAR205,Memory Attribute Register 205"
|
|
bitfld.long 0x304 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x304 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x308 "MAR206,Memory Attribute Register 206"
|
|
bitfld.long 0x308 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x308 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x30C "MAR207,Memory Attribute Register 207"
|
|
bitfld.long 0x30C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x30C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x310 "MAR208,Memory Attribute Register 208"
|
|
bitfld.long 0x310 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x310 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x314 "MAR209,Memory Attribute Register 209"
|
|
bitfld.long 0x314 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x314 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x318 "MAR210,Memory Attribute Register 210"
|
|
bitfld.long 0x318 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x318 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x31C "MAR211,Memory Attribute Register 211"
|
|
bitfld.long 0x31C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x31C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x320 "MAR212,Memory Attribute Register 212"
|
|
bitfld.long 0x320 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x320 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x324 "MAR213,Memory Attribute Register 213"
|
|
bitfld.long 0x324 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x324 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x328 "MAR214,Memory Attribute Register 214"
|
|
bitfld.long 0x328 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x328 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x32C "MAR215,Memory Attribute Register 215"
|
|
bitfld.long 0x32C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x32C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x330 "MAR216,Memory Attribute Register 216"
|
|
bitfld.long 0x330 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x330 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x334 "MAR217,Memory Attribute Register 217"
|
|
bitfld.long 0x334 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x334 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x338 "MAR218,Memory Attribute Register 218"
|
|
bitfld.long 0x338 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x338 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x33C "MAR219,Memory Attribute Register 219"
|
|
bitfld.long 0x33C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x33C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x340 "MAR220,Memory Attribute Register 220"
|
|
bitfld.long 0x340 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x340 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x344 "MAR221,Memory Attribute Register 221"
|
|
bitfld.long 0x344 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x344 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x348 "MAR222,Memory Attribute Register 222"
|
|
bitfld.long 0x348 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x348 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x34C "MAR223,Memory Attribute Register 223"
|
|
bitfld.long 0x34C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x34C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x350 "MAR224,Memory Attribute Register 224"
|
|
bitfld.long 0x350 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x350 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x354 "MAR225,Memory Attribute Register 225"
|
|
bitfld.long 0x354 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x354 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x358 "MAR226,Memory Attribute Register 226"
|
|
bitfld.long 0x358 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x358 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x35C "MAR227,Memory Attribute Register 227"
|
|
bitfld.long 0x35C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x35C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x360 "MAR228,Memory Attribute Register 228"
|
|
bitfld.long 0x360 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x360 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x364 "MAR229,Memory Attribute Register 229"
|
|
bitfld.long 0x364 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x364 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x368 "MAR230,Memory Attribute Register 230"
|
|
bitfld.long 0x368 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x368 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x36C "MAR231,Memory Attribute Register 231"
|
|
bitfld.long 0x36C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x36C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x370 "MAR232,Memory Attribute Register 232"
|
|
bitfld.long 0x370 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x370 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x374 "MAR233,Memory Attribute Register 233"
|
|
bitfld.long 0x374 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x374 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x378 "MAR234,Memory Attribute Register 234"
|
|
bitfld.long 0x378 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x378 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x37C "MAR235,Memory Attribute Register 235"
|
|
bitfld.long 0x37C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x37C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x380 "MAR236,Memory Attribute Register 236"
|
|
bitfld.long 0x380 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x380 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x384 "MAR237,Memory Attribute Register 237"
|
|
bitfld.long 0x384 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x384 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x388 "MAR238,Memory Attribute Register 238"
|
|
bitfld.long 0x388 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x388 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x38C "MAR239,Memory Attribute Register 239"
|
|
bitfld.long 0x38C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x38C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x390 "MAR240,Memory Attribute Register 240"
|
|
bitfld.long 0x390 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x390 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x394 "MAR241,Memory Attribute Register 241"
|
|
bitfld.long 0x394 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x394 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x398 "MAR242,Memory Attribute Register 242"
|
|
bitfld.long 0x398 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x398 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x39C "MAR243,Memory Attribute Register 243"
|
|
bitfld.long 0x39C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x39C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3A0 "MAR244,Memory Attribute Register 244"
|
|
bitfld.long 0x3A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3A4 "MAR245,Memory Attribute Register 245"
|
|
bitfld.long 0x3A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3A8 "MAR246,Memory Attribute Register 246"
|
|
bitfld.long 0x3A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3AC "MAR247,Memory Attribute Register 247"
|
|
bitfld.long 0x3AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3B0 "MAR248,Memory Attribute Register 248"
|
|
bitfld.long 0x3B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3B4 "MAR249,Memory Attribute Register 249"
|
|
bitfld.long 0x3B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3B8 "MAR250,Memory Attribute Register 250"
|
|
bitfld.long 0x3B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3BC "MAR251,Memory Attribute Register 251"
|
|
bitfld.long 0x3BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C0 "MAR252,Memory Attribute Register 252"
|
|
bitfld.long 0x3C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C4 "MAR253,Memory Attribute Register 253"
|
|
bitfld.long 0x3C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3C8 "MAR254,Memory Attribute Register 254"
|
|
bitfld.long 0x3C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
line.long 0x3CC "MAR255,Memory Attribute Register 255"
|
|
bitfld.long 0x3CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x3CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
|
|
tree.end
|
|
width 10.
|
|
base d:0x0184a000
|
|
tree "Memory Protection Page Attribute Registers"
|
|
group.long 0x200++0x7f
|
|
line.long 0x0 "L2MPPA0,Level 2 Memory Protection Page Attribute Register 0"
|
|
bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x0 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x0 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x4 "L2MPPA1,Level 2 Memory Protection Page Attribute Register 1"
|
|
bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x4 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x4 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x8 "L2MPPA2,Level 2 Memory Protection Page Attribute Register 2"
|
|
bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x8 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x8 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0xC "L2MPPA3,Level 2 Memory Protection Page Attribute Register 3"
|
|
bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0xC 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0xC 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x10 "L2MPPA4,Level 2 Memory Protection Page Attribute Register 4"
|
|
bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x10 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x10 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x14 "L2MPPA5,Level 2 Memory Protection Page Attribute Register 5"
|
|
bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x14 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x14 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x18 "L2MPPA6,Level 2 Memory Protection Page Attribute Register 6"
|
|
bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x18 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x18 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x1C "L2MPPA7,Level 2 Memory Protection Page Attribute Register 7"
|
|
bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x20 "L2MPPA8,Level 2 Memory Protection Page Attribute Register 8"
|
|
bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x20 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x20 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x24 "L2MPPA9,Level 2 Memory Protection Page Attribute Register 9"
|
|
bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x24 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x24 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x28 "L2MPPA10,Level 2 Memory Protection Page Attribute Register 10"
|
|
bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x28 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x28 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x2C "L2MPPA11,Level 2 Memory Protection Page Attribute Register 11"
|
|
bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x30 "L2MPPA12,Level 2 Memory Protection Page Attribute Register 12"
|
|
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x30 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x30 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x34 "L2MPPA13,Level 2 Memory Protection Page Attribute Register 13"
|
|
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x34 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x34 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x38 "L2MPPA14,Level 2 Memory Protection Page Attribute Register 14"
|
|
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x38 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x38 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x3C "L2MPPA15,Level 2 Memory Protection Page Attribute Register 15"
|
|
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x40 "L2MPPA16,Level 2 Memory Protection Page Attribute Register 16"
|
|
bitfld.long 0x40 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x40 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x40 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x40 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x40 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x40 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x40 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x40 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x40 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x40 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x40 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x40 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x40 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x40 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x44 "L2MPPA17,Level 2 Memory Protection Page Attribute Register 17"
|
|
bitfld.long 0x44 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x44 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x44 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x44 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x44 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x44 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x44 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x44 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x44 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x44 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x44 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x44 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x44 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x44 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x48 "L2MPPA18,Level 2 Memory Protection Page Attribute Register 18"
|
|
bitfld.long 0x48 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x48 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x48 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x48 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x48 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x48 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x48 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x48 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x48 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x48 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x48 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x48 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x48 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x48 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x4C "L2MPPA19,Level 2 Memory Protection Page Attribute Register 19"
|
|
bitfld.long 0x4C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x4C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x4C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x4C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x4C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x4C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x4C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x4C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x4C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x4C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x4C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x4C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x50 "L2MPPA20,Level 2 Memory Protection Page Attribute Register 20"
|
|
bitfld.long 0x50 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x50 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x50 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x50 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x50 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x50 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x50 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x50 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x50 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x50 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x50 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x50 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x50 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x50 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x54 "L2MPPA21,Level 2 Memory Protection Page Attribute Register 21"
|
|
bitfld.long 0x54 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x54 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x54 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x54 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x54 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x54 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x54 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x54 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x54 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x54 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x54 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x54 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x54 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x54 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x58 "L2MPPA22,Level 2 Memory Protection Page Attribute Register 22"
|
|
bitfld.long 0x58 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x58 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x58 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x58 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x58 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x58 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x58 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x58 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x58 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x58 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x58 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x58 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x58 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x58 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x5C "L2MPPA23,Level 2 Memory Protection Page Attribute Register 23"
|
|
bitfld.long 0x5C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x5C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x5C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x5C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x5C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x5C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x5C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x5C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x5C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x5C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x5C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x5C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x5C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x5C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x60 "L2MPPA24,Level 2 Memory Protection Page Attribute Register 24"
|
|
bitfld.long 0x60 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x60 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x60 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x60 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x60 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x60 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x60 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x60 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x60 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x60 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x60 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x60 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x60 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x60 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x64 "L2MPPA25,Level 2 Memory Protection Page Attribute Register 25"
|
|
bitfld.long 0x64 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x64 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x64 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x64 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x64 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x64 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x64 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x64 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x64 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x64 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x64 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x64 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x64 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x64 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x68 "L2MPPA26,Level 2 Memory Protection Page Attribute Register 26"
|
|
bitfld.long 0x68 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x68 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x68 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x68 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x68 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x68 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x68 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x68 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x68 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x68 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x68 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x68 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x68 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x68 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x6C "L2MPPA27,Level 2 Memory Protection Page Attribute Register 27"
|
|
bitfld.long 0x6C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x6C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x6C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x6C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x6C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x6C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x6C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x6C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x6C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x6C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x6C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x6C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x6C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x6C 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x70 "L2MPPA28,Level 2 Memory Protection Page Attribute Register 28"
|
|
bitfld.long 0x70 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x70 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x70 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x70 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x70 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x70 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x70 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x70 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x70 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x70 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x70 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x70 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x70 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x70 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x74 "L2MPPA29,Level 2 Memory Protection Page Attribute Register 29"
|
|
bitfld.long 0x74 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x74 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x74 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x74 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x74 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x74 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x74 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x74 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x74 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x74 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x74 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x74 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x74 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x74 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x78 "L2MPPA30,Level 2 Memory Protection Page Attribute Register 30"
|
|
bitfld.long 0x78 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x78 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x78 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x78 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x78 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x78 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x78 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x78 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x78 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x78 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x78 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x78 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x78 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x78 0. " UX ,User execute access type" "Normal,User"
|
|
line.long 0x7C "L2MPPA31,Level 2 Memory Protection Page Attribute Register 31"
|
|
bitfld.long 0x7C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
|
|
bitfld.long 0x7C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted"
|
|
bitfld.long 0x7C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x7C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
|
|
bitfld.long 0x7C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted"
|
|
bitfld.long 0x7C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x7C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
|
|
bitfld.long 0x7C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
|
|
textline " "
|
|
bitfld.long 0x7C 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
bitfld.long 0x7C 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x7C 3. " SX ,Supervisor execute access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x7C 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x7C 1. " UW ,User write access type" "Normal,User"
|
|
bitfld.long 0x7C 0. " UX ,User execute access type" "Normal,User"
|
|
tree.end
|
|
width 9.
|
|
rgroup.long 0x000++0x7 "Memory Protection Fault Registers"
|
|
line.long 0x00 "L2MPFAR,Level 2 Memory Protection Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " FA ,Fault Address"
|
|
line.long 0x04 "L2MPFSR,Level 2 Memory Protection Fault Set Register"
|
|
hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor"
|
|
bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor"
|
|
bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor"
|
|
bitfld.long 0x04 2. " UR ,User read access type" "Normal,User"
|
|
bitfld.long 0x04 1. " UW ,User write access type" "Normal,User"
|
|
group.long 0x008++0x3
|
|
line.long 0x00 "L2MPFCR,Level 2 Memory Protection Fault Clear Register"
|
|
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Clear"
|
|
width 12.
|
|
wgroup.long 0x100++0xf "Memory Protection Lock Registers"
|
|
line.long 0x00 "L2MPLK0,Level 2 Memory Protection Lock 0"
|
|
hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0"
|
|
line.long 0x04 "L2MPLK1,Level 2 Memory Protection Lock 1"
|
|
hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32"
|
|
line.long 0x08 "L2MPLK2,Level 2 Memory Protection Lock 2"
|
|
hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64"
|
|
line.long 0x0c "L2MPLK3,Level 2 Memory Protection Lock 3"
|
|
hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96"
|
|
wgroup.long 0x110++0x3
|
|
line.long 0x00 "L2MPLKCMD,Level 2 Memory Protection Lock Command Register"
|
|
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
|
|
bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked"
|
|
bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "L2MPLKSTAT,Level 2 Memory Protection Lock Status Register"
|
|
bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged"
|
|
AUTOINDENT.ON right tree
|
|
base d:0x01846000
|
|
rgroup.long 0x4++0x3 "Error Detection Registers"
|
|
line.long 0x0 "L2EDSTAT,L2 Error Detection Status Register"
|
|
decmask.long.byte 0x0 16.--23. "BITPOS,Single Bit error position"
|
|
bitfld.long 0x0 8.--9. "NERR" "Single Bit error,Double Bit error,,Error in parity value"
|
|
newline
|
|
bitfld.long 0x0 7. "VERR,Error occurred on L2 victims" "False,True"
|
|
bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
|
|
bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True"
|
|
newline
|
|
bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True"
|
|
bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True"
|
|
bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "L2EDCMD, L2 Error Detection Command Register"
|
|
bitfld.long 0x0 7. "VCLR,Clears the victim parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
|
|
bitfld.long 0x0 4. "DCLR,Clears the data fetch parity error status" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
|
|
bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable"
|
|
bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "L2EDADDR,L2 Error Detection Address Register"
|
|
hexmask.long.long 0x0 5.--31. 32. "ADDR,Address of parity error (5 LSBs assumed to be 00000b)"
|
|
bitfld.long 0x0 8.--9. "L2WAY,Error detected in Way" "Way 0,Way 1,Way 2,Way 3"
|
|
bitfld.long 0x0 0. "RAM,Location where error was detected" "L2,RAM"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "L2EDCPEC,L2 Error Detection Correctable Parity Error Counter Register"
|
|
hexmask.long.byte 0x0 0.--7. "CNT,Counter value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "L2EDNPEC,L2 Error Detection Non-correctable Parity Error Counter Register"
|
|
hexmask.long.byte 0x0 0.--7. "CNT,Counter value"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "L2EDCEN,L2 Error Detection and Correction Enable Register"
|
|
bitfld.long 0x0 0. "SDMAEN,EDC on SDMA read from L2 RAM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "PL2SEN,EDC on L1P memory controller read from L2 RAM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "DL2SEN,EDC on L1D memory controller read from L2 RAM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "PL2CEN,EDC on L1P memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. "DL2CEN,EDC on L1D memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
|
|
AUTOINDENT.OFF
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "IDMA (Internal Direct Memory Access Controller)"
|
|
width 14.
|
|
base d:0x01820000
|
|
rgroup.long 0x00++0x3 "Channel 0"
|
|
line.long 0x00 "IDMA0_STAT,IDMA Channel 0 Status Register"
|
|
bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active"
|
|
group.long 0x04++0xf
|
|
line.long 0x00 "IDMA0_MASK,IDMA Channel 0 Mask Register"
|
|
bitfld.long 0x00 31. " M31 ,Mask bit 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " M30 ,Mask bit 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " M29 ,Mask bit 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " M28 ,Mask bit 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " M27 ,Mask bit 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " M26 ,Mask bit 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " M25 ,Mask bit 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " M24 ,Mask bit 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " M23 ,Mask bit 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " M22 ,Mask bit 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " M21 ,Mask bit 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " M20 ,Mask bit 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " M19 ,Mask bit 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " M18 ,Mask bit 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " M17 ,Mask bit 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " M16 ,Mask bit 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " M15 ,Mask bit 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " M14 ,Mask bit 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " M13 ,Mask bit 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " M12 ,Mask bit 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " M11 ,Mask bit 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " M10 ,Mask bit 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " M9 ,Mask bit 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " M8 ,Mask bit 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " M7 ,Mask bit 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " M6 ,Mask bit 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " M5 ,Mask bit 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M4 ,Mask bit 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " M3 ,Mask bit 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " M2 ,Mask bit 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M1 ,Mask bit 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " M0 ,Mask bit 0" "Not masked,Masked"
|
|
line.long 0x04 "IDMA0_SOURCE,IDMA Channel 0 Source Address Register"
|
|
hexmask.long 0x04 5.--31. 0x20 " SOURCEADDR ,Source address"
|
|
line.long 0x08 "IDMA0_DEST,IDMA Channel 0 Destination Address Register"
|
|
hexmask.long 0x08 5.--31. 0x20 " DESTADDR ,Destination address"
|
|
line.long 0x0c "IDMA0_COUNT,IDMA Channel 0 Count Register"
|
|
bitfld.long 0x0c 28. " INT ,CPU interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0.--3. " COUNT ,4-bit block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rgroup.long 0x100++0x3 "Channel 1"
|
|
line.long 0x00 "IDMA1_STAT,IDMA Channel 1 Status Register"
|
|
bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active"
|
|
group.long 0x108++0xb
|
|
line.long 0x00 "IDMA1_SOURCE,IDMA Channel 1 Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " SOURCEADDR ,Source address"
|
|
line.long 0x04 "IDMA1_DEST,IDMA Channel 1 Destination Address Register"
|
|
hexmask.long 0x04 2.--31. 0x4 " DESTADDR ,Destination address"
|
|
line.long 0x08 "IDMA1_COUNT,IDMA Channel 1 Count Register"
|
|
bitfld.long 0x08 29.--31. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 28. " INT ,CPU interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " FILL ,Block fill" "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " COUNT ,Byte count"
|
|
width 0xb
|
|
tree.end
|
|
tree "XMC (Extended Memory Controller)"
|
|
width 14.
|
|
AUTOINDENT.ON right tree
|
|
base d:0x08000000
|
|
group.long 0x00++0x7F "XMC MPAX Segment Registers"
|
|
line.long 0x0 "XMPAXL0,MPAX segment 0 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x0 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x0 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x0 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x0 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x0 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x0 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x0+0x4 "XMPAXH0,MPAX segment 0 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x0 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x8 "XMPAXL1,MPAX segment 1 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x8 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x8 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x8 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x8 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x8 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x8 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x8+0x4 "XMPAXH1,MPAX segment 1 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x8 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x10 "XMPAXL2,MPAX segment 2 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x10 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x10 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x10 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x10 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x10 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x10 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x10+0x4 "XMPAXH2,MPAX segment 2 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x10 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x18 "XMPAXL3,MPAX segment 3 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x18 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x18 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x18 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x18 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x18 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x18 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x18+0x4 "XMPAXH3,MPAX segment 3 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x18 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x20 "XMPAXL4,MPAX segment 4 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x20 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x20 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x20 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x20 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x20 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x20 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x20+0x4 "XMPAXH4,MPAX segment 4 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x20 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x28 "XMPAXL5,MPAX segment 5 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x28 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x28 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x28 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x28 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x28 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x28 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x28+0x4 "XMPAXH5,MPAX segment 5 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x28 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x30 "XMPAXL6,MPAX segment 6 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x30 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x30 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x30 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x30 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x30 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x30 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x30+0x4 "XMPAXH6,MPAX segment 6 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x30 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x38 "XMPAXL7,MPAX segment 7 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x38 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x38 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x38 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x38 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x38 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x38 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x38+0x4 "XMPAXH7,MPAX segment 7 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x38 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x40 "XMPAXL8,MPAX segment 8 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x40 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x40 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x40 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x40 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x40 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x40 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x40+0x4 "XMPAXH8,MPAX segment 8 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x40 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x48 "XMPAXL9,MPAX segment 9 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x48 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x48 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x48 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x48 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x48 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x48 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x48+0x4 "XMPAXH9,MPAX segment 9 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x48 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x50 "XMPAXL10,MPAX segment 10 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x50 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x50 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x50 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x50 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x50 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x50 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x50+0x4 "XMPAXH10,MPAX segment 10 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x50 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x58 "XMPAXL11,MPAX segment 11 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x58 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x58 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x58 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x58 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x58 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x58 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x58+0x4 "XMPAXH11,MPAX segment 11 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x58 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x60 "XMPAXL12,MPAX segment 12 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x60 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x60 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x60 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x60 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x60 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x60 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x60+0x4 "XMPAXH12,MPAX segment 12 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x60 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x68 "XMPAXL13,MPAX segment 13 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x68 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x68 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x68 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x68 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x68 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x68 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x68+0x4 "XMPAXH13,MPAX segment 13 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x68 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x70 "XMPAXL14,MPAX segment 14 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x70 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x70 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x70 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x70 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x70 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x70 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x70+0x4 "XMPAXH14,MPAX segment 14 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x70 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
line.long 0x78 "XMPAXL15,MPAX segment 15 low register"
|
|
hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
|
|
bitfld.long 0x78 5. "SR,Supervisor mode may read from segment" "False,True"
|
|
bitfld.long 0x78 4. "SW,Supervisor mode may write to segment" "False,True"
|
|
bitfld.long 0x78 3. "SX,Supervisor mode may execute from segment" "False,True"
|
|
bitfld.long 0x78 2. "UR,User mode may read from segment" "False,True"
|
|
bitfld.long 0x78 1. "UW,User mode may write to segment" "False,True"
|
|
bitfld.long 0x78 0. "UX,User mode may execute from segment" "False,True"
|
|
line.long 0x78+0x4 "XMPAXH15,MPAX segment 15 high register"
|
|
hexmask.long 0x0 12.--31. "BADDR,Base Address"
|
|
bitfld.long 0x78 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
textline ""
|
|
rgroup.long 0x200++0x3 "Memory Protection Fault Reporting Registers"
|
|
line.long 0. "XMPFAR,Memory Protection Fault Address Register"
|
|
hexmask.long 0x0 0.--31. "Fault Address,Fault Address"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0. "XMPFSR,Memory Protection Fault Status Register"
|
|
bitfld.long 0. 8. "LOCAL,Access was a LOCAL access" "False,True"
|
|
bitfld.long 0. 5. "SR,When set, indicates a supervisor read request" "False,True"
|
|
bitfld.long 0. 4. "SW,When set, indicates a supervisor write request" "False,True"
|
|
bitfld.long 0. 3. "SX,When set, indicates a supervisor program fetch request" "False,True"
|
|
bitfld.long 0. 2. "UR,When set, indicates a user read request" "False,True"
|
|
bitfld.long 0. 1. "UW,When set, indicates a user write request" "False,True"
|
|
bitfld.long 0. 0. "UX,When set, indicates a user program fetch request" "False,True"
|
|
group.long 0x208++0x3
|
|
line.long 0. "XMPFCR,Memory Protection Fault Clear Register"
|
|
bitfld.long 0. 0. "MPFCLR,Clear fault" "No effect,Clear"
|
|
group.long 0x280++0x3 "Prefetch Priority Register"
|
|
line.long 0. "MDMAARBX,MDMA Arbitration Priority Register"
|
|
bitfld.long 0. 16.--18. "PRI,Priority" "0 (highest),1,2,3,4,5,6,7 (lowest)"
|
|
rgroup.long 0x300++0x3 "Prefetch Buffer Registers"
|
|
line.long 0. "XPFCMD,Prefetch Command Register"
|
|
bitfld.long 0. 4. "ACRST,Analysis Counter Reset" "No effect,Reset"
|
|
hexmask.long.byte 0. 2.--3. "ACEN,Analysis Counter Enable"
|
|
bitfld.long 0. 1. "ACENL,Analysis Counter ENable (ACEN) Load" "False,True"
|
|
bitfld.long 0. 0. "INV,Invalidate prefetch buffer contents" "No effect,Invalidate"
|
|
rgroup.long 0x304++0x3 "Prefetch Buffer Performance Analysis Registers"
|
|
line.long 0. "XPFACS,Prefetch Analysis Counter Status"
|
|
rgroup.long 0x310++0xF
|
|
line.long 0x0 "XPFAC0,Prefetch Analysis Counter 0"
|
|
line.long 0x4 "XPFAC1,Prefetch Analysis Counter 1"
|
|
line.long 0x8 "XPFAC2,Prefetch Analysis Counter 2"
|
|
line.long 0xC "XPFAC3,Prefetch Analysis Counter 3"
|
|
rgroup.long 0x400++0x1F
|
|
line.long 0x0 "XPFADDR0,Prefetch Address for Slot 0"
|
|
line.long 0x4 "XPFADDR1,Prefetch Address for Slot 1"
|
|
line.long 0x8 "XPFADDR2,Prefetch Address for Slot 2"
|
|
line.long 0xC "XPFADDR3,Prefetch Address for Slot 3"
|
|
line.long 0x10 "XPFADDR4,Prefetch Address for Slot 4"
|
|
line.long 0x14 "XPFADDR5,Prefetch Address for Slot 5"
|
|
line.long 0x18 "XPFADDR6,Prefetch Address for Slot 6"
|
|
line.long 0x1C "XPFADDR7,Prefetch Address for Slot 7"
|
|
AUTOINDENT.OFF
|
|
width 0xb
|
|
tree.end
|
|
tree "Bandwith Management"
|
|
width 13.
|
|
base d:0x01841000
|
|
group.long 0x40++0xf "L1D"
|
|
line.long 0x00 "CPUARBD,L1D CPU Arbitration Control Register"
|
|
bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x04 "IDMAARBD,L1D IDMA Arbitration Control Register"
|
|
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x08 "SDMAARBD,L1D Slave DMA Arbitration Control Register"
|
|
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x0c "UCARBD,L1D User Coherence Arbitration Control Register"
|
|
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
width 13.
|
|
group.long 0x00++0xf "L2"
|
|
line.long 0x00 "CPUARBU,L2D CPU Arbitration Control Register"
|
|
bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x04 "IDMAARBU,L1D IDMA Arbitration Control Register"
|
|
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x08 "SDMAARBU,L1D Slave DMA Arbitration Control Register"
|
|
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x0c "UCARBU,L1D User Coherence Arbitration Control Register"
|
|
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
width 13.
|
|
base d:0x01820000
|
|
group.long 0x200++0xf "EMC"
|
|
line.long 0x00 "CPUARBE,EMC CPU Arbitration Control Register"
|
|
bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x04 "IDMAARBE,EMC IDMA Arbitration Control Register"
|
|
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x08 "SDMAARBE,EMC Slave DMA Arbitration Control Register"
|
|
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
|
|
line.long 0x0c "MDMAARBE,EMC Master DMA Arbitration Control Register"
|
|
bitfld.long 0x0c 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
|
|
width 0xb
|
|
tree.end
|
|
tree "Interrupt Controller"
|
|
width 11.
|
|
base d:0x01800000
|
|
group.long 0x00++0xf
|
|
line.long 0x00 "EVTFLAG0,Event Flag Register 0"
|
|
setclrfld.long 0x00 14. 0x20 14. 0x40 14. " EF14_set/clr ,State of event EVT14" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 13. 0x20 13. 0x40 13. " EF13_set/clr ,State of event EVT13" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x20 12. 0x40 12. " EF12_set/clr ,State of event EVT12" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 11. 0x20 11. 0x40 11. " EF11_set/clr ,State of event EVT11" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x20 9. 0x40 9. " EF9_set/clr ,State of event EVT9" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 8. 0x20 8. 0x40 8. " EF8_set/clr ,State of event EVT8" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x20 7. 0x40 7. " EF7_set/clr ,State of event EVT7" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 6. 0x20 6. 0x40 6. " EF6_set/clr ,State of event EVT6" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x20 5. 0x40 5. " EF5_set/clr ,State of event EVT5" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x20 4. 0x40 4. " EF4_set/clr ,State of event EVT4" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x20 3. 0x40 3. " EF3_set/clr ,State of event EVT3" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x20 2. 0x40 2. " EF2_set/clr ,State of event EVT2" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x20 1. 0x40 1. " EF1_set/clr ,State of event EVT1" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x20 0. 0x40 0. " EF0_set/clr ,State of event EVT0" "Not occurred,Occurred"
|
|
line.long 0x04 "EVTFLAG1,Event Flag Register 1"
|
|
setclrfld.long 0x04 28. 0x24 28. 0x44 28. " EF60_set/clr ,State of event EVT60" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 27. 0x24 27. 0x44 27. " EF59_set/clr ,State of event EVT59" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 24. 0x24 24. 0x44 24. " EF56_set/clr ,State of event EVT56" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 23. 0x24 23. 0x44 23. " EF55_set/clr ,State of event EVT55" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 22. 0x24 22. 0x44 22. " EF54_set/clr ,State of event EVT54" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 21. 0x24 21. 0x44 21. " EF53_set/clr ,State of event EVT53" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x24 19. 0x44 19. " EF51_set/clr ,State of event EVT51" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 18. 0x24 18. 0x44 18. " EF50_set/clr ,State of event EVT50" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x24 17. 0x44 17. " EF49_set/clr ,State of event EVT49" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 16. 0x24 16. 0x44 16. " EF48_set/clr ,State of event EVT48" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x24 15. 0x44 15. " EF47_set/clr ,State of event EVT47" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 11. 0x24 11. 0x44 11. " EF43_set/clr ,State of event EVT43" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x24 9. 0x44 9. " EF41_set/clr ,State of event EVT41" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 8. 0x24 8. 0x44 8. " EF40_set/clr ,State of event EVT40" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x24 7. 0x44 7. " EF39_set/clr ,State of event EVT39" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 6. 0x24 6. 0x44 6. " EF38_set/clr ,State of event EVT38" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x24 5. 0x44 5. " EF37_set/clr ,State of event EVT37" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 4. 0x24 4. 0x44 4. " EF36_set/clr ,State of event EVT36" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x24 3. 0x44 3. " EF35_set/clr ,State of event EVT35" "Not occurred,Occurred"
|
|
setclrfld.long 0x04 2. 0x24 2. 0x44 2. " EF34_set/clr ,State of event EVT34" "Not occurred,Occurred"
|
|
line.long 0x08 "EVTFLAG2,Event Flag Register 2"
|
|
setclrfld.long 0x08 21. 0x28 21. 0x48 21. " EF85_set/clr ,State of event EVT85" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 20. 0x28 20. 0x48 20. " EF84_set/clr ,State of event EVT84" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x28 19. 0x48 19. " EF83_set/clr ,State of event EVT83" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 18. 0x28 18. 0x48 18. " EF82_set/clr ,State of event EVT82" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x28 17. 0x48 17. " EF81_set/clr ,State of event EVT81" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 16. 0x28 16. 0x48 16. " EF80_set/clr ,State of event EVT80" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 14. 0x28 14. 0x48 14. " EF78_set/clr ,State of event EVT78" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 13. 0x28 13. 0x48 13. " EF77_set/clr ,State of event EVT77" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 12. 0x28 12. 0x48 12. " EF76_set/clr ,State of event EVT76" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 11. 0x28 11. 0x48 11. " EF75_set/clr ,State of event EVT75" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 10. 0x28 10. 0x48 10. " EF74_set/clr ,State of event EVT74" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 9. 0x28 9. 0x48 9. " EF73_set/clr ,State of event EVT73" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 8. 0x28 8. 0x48 8. " EF72_set/clr ,State of event EVT72" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 7. 0x28 7. 0x48 7. " EF71_set/clr ,State of event EVT71" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 6. 0x28 6. 0x48 6. " EF70_set/clr ,State of event EVT70" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 5. 0x28 5. 0x48 5. " EF69_set/clr ,State of event EVT69" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 4. 0x28 4. 0x48 4. " EF68_set/clr ,State of event EVT68" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 3. 0x28 3. 0x48 3. " EF67_set/clr ,State of event EVT67" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 2. 0x28 2. 0x48 2. " EF66_set/clr ,State of event EVT66" "Not occurred,Occurred"
|
|
setclrfld.long 0x08 1. 0x28 1. 0x48 1. " EF65_set/clr ,State of event EVT65" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x08 0. 0x28 0. 0x48 0. " EF64_set/clr ,State of event EVT64" "Not occurred,Occurred"
|
|
line.long 0x0c "EVTFLAG3,Event Flag Register 3"
|
|
setclrfld.long 0x0c 31. 0x2c 31. 0x4c 31. " EF127_set/clr ,State of event EVT127" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 30. 0x2c 30. 0x4c 30. " EF126_set/clr ,State of event EVT126" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 29. 0x2c 29. 0x4c 29. " EF125_set/clr ,State of event EVT125" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 28. 0x2c 28. 0x4c 28. " EF124_set/clr ,State of event EVT124" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 27. 0x2c 27. 0x4c 27. " EF123_set/clr ,State of event EVT123" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 26. 0x2c 26. 0x4c 26. " EF122_set/clr ,State of event EVT122" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x2c 25. 0x4c 25. " EF121_set/clr ,State of event EVT121" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 24. 0x2c 24. 0x4c 24. " EF120_set/clr ,State of event EVT120" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 23. 0x2c 23. 0x4c 23. " EF119_set/clr ,State of event EVT119" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 22. 0x2c 22. 0x4c 22. " EF118_set/clr ,State of event EVT118" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 21. 0x2c 21. 0x4c 21. " EF117_set/clr ,State of event EVT117" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 20. 0x2c 20. 0x4c 20. " EF116_set/clr ,State of event EVT116" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 17. 0x2c 17. 0x4c 17. " EF113_set/clr ,State of event EVT113" "Not occurred,Occurred"
|
|
setclrfld.long 0x0c 1. 0x2c 1. 0x4c 1. " EF97_set/clr ,State of event EVT97" "Not occurred,Occurred"
|
|
textline " "
|
|
setclrfld.long 0x0c 0. 0x2c 0. 0x4c 0. " EF96_set/clr ,State of event EVT96" "Not occurred,Occurred"
|
|
width 11.
|
|
group.long 0x80++0xf
|
|
line.long 0x00 "EVTMASK0,Event Mask Register 0"
|
|
bitfld.long 0x00 14. " EM14 ,Disables event EVT14 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 13. " EM13 ,Disables event EVT13 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 12. " EM12 ,Disables event EVT12 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EM11 ,Disables event EVT11 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 9. " EM9 ,Disables event EVT9 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 8. " EM8 ,Disables event EVT8 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EM7 ,Disables event EVT7 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 6. " EM6 ,Disables event EVT6 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 5. " EM5 ,Disables event EVT5 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EM4 ,Disables event EVT4 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 3. " EM3 ,Disables event EVT3 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 2. " EM2 ,Disables event EVT2 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EM1 ,Disables event EVT1 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 0. " EM0 ,Disables event EVT0 from being used as input to the event combiner" "Combined,Disabled"
|
|
line.long 0x04 "EVTMASK1,Event Mask Register 1"
|
|
bitfld.long 0x04 28. " EM60 ,Disables event EVT60 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 27. " EM59 ,Disables event EVT59 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 24. " EM56 ,Disables event EVT56 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " EM55 ,Disables event EVT55 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 22. " EM54 ,Disables event EVT54 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 21. " EM53 ,Disables event EVT53 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EM51 ,Disables event EVT51 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 18. " EM50 ,Disables event EVT50 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 17. " EM49 ,Disables event EVT49 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " EM48 ,Disables event EVT48 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 15. " EM47 ,Disables event EVT47 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 11. " EM43 ,Disables event EVT43 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EM41 ,Disables event EVT41 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 8. " EM40 ,Disables event EVT40 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 7. " EM39 ,Disables event EVT39 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " EM38 ,Disables event EVT38 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 5. " EM37 ,Disables event EVT37 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 4. " EM36 ,Disables event EVT36 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EM35 ,Disables event EVT35 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 2. " EM34 ,Disables event EVT34 from being used as input to the event combiner" "Combined,Disabled"
|
|
line.long 0x08 "EVTMASK2,Event Mask Register 2"
|
|
bitfld.long 0x08 21. " EM85 ,Disables event EVT85 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 20. " EM84 ,Disables event EVT84 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 19. " EM83 ,Disables event EVT83 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " EM82 ,Disables event EVT82 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 17. " EM81 ,Disables event EVT81 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 16. " EM80 ,Disables event EVT80 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " EM78 ,Disables event EVT78 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 13. " EM77 ,Disables event EVT77 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 12. " EM76 ,Disables event EVT76 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " EM75 ,Disables event EVT75 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 10. " EM74 ,Disables event EVT74 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 9. " EM73 ,Disables event EVT73 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " EM72 ,Disables event EVT72 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 7. " EM71 ,Disables event EVT71 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 6. " EM70 ,Disables event EVT70 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " EM69 ,Disables event EVT69 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 4. " EM68 ,Disables event EVT68 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 3. " EM67 ,Disables event EVT67 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EM66 ,Disables event EVT66 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 1. " EM65 ,Disables event EVT65 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 0. " EM64 ,Disables event EVT64 from being used as input to the event combiner" "Combined,Disabled"
|
|
line.long 0x0c "EVTMASK3,Event Mask Register 3"
|
|
bitfld.long 0x0c 31. " EM127 ,Disables event EVT127 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 30. " EM126 ,Disables event EVT126 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 29. " EM125 ,Disables event EVT125 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " EM124 ,Disables event EVT124 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 27. " EM123 ,Disables event EVT123 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 26. " EM122 ,Disables event EVT122 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " EM121 ,Disables event EVT121 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 24. " EM120 ,Disables event EVT120 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 23. " EM119 ,Disables event EVT119 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " EM118 ,Disables event EVT118 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 21. " EM117 ,Disables event EVT117 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 20. " EM116 ,Disables event EVT116 from being used as input to the event combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " EM113 ,Disables event EVT113 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 1. " EM97 ,Disables event EVT97 from being used as input to the event combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 0. " EM96 ,Disables event EVT96 from being used as input to the event combiner" "Combined,Disabled"
|
|
group.long 0xc0++0xf
|
|
line.long 0x00 "EXPMASK0,Exception Mask Register 0"
|
|
bitfld.long 0x00 14. " XM14 ,Event EVT14 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 13. " XM13 ,Event EVT13 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 12. " XM12 ,Event EVT12 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XM11 ,Event EVT11 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 9. " XM9 ,Event EVT9 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 8. " XM8 ,Event EVT8 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XM7 ,Event EVT7 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 6. " XM6 ,Event EVT6 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 5. " XM5 ,Event EVT5 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " XM4 ,Event EVT4 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 3. " XM3 ,Event EVT3 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 2. " XM2 ,Event EVT2 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XM1 ,Event EVT1 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x00 0. " XM0 ,Event EVT0 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
line.long 0x04 "EXPMASK1,Exception Mask Register 1"
|
|
bitfld.long 0x04 28. " XM60 ,Event EVT60 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 27. " XM59 ,Event EVT59 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 24. " XM56 ,Event EVT56 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " XM55 ,Event EVT55 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 22. " XM54 ,Event EVT54 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 21. " XM53 ,Event EVT53 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " XM51 ,Event EVT51 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 18. " XM50 ,Event EVT50 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 17. " XM49 ,Event EVT49 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " XM48 ,Event EVT48 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 15. " XM47 ,Event EVT47 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 11. " XM43 ,Event EVT43 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XM41 ,Event EVT41 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 8. " XM40 ,Event EVT40 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 7. " XM39 ,Event EVT39 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " XM38 ,Event EVT38 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 5. " XM37 ,Event EVT37 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 4. " XM36 ,Event EVT36 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XM35 ,Event EVT35 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x04 2. " XM34 ,Event EVT34 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
line.long 0x08 "EXPMASK2,Exception Mask Register 2"
|
|
bitfld.long 0x08 21. " XM85 ,Event EVT85 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 20. " XM84 ,Event EVT84 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 19. " XM83 ,Event EVT83 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " XM82 ,Event EVT82 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 17. " XM81 ,Event EVT81 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 16. " XM80 ,Event EVT80 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " XM78 ,Event EVT78 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 13. " XM77 ,Event EVT77 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 12. " XM76 ,Event EVT76 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XM75 ,Event EVT75 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 10. " XM74 ,Event EVT74 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 9. " XM73 ,Event EVT73 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XM72 ,Event EVT72 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 7. " XM71 ,Event EVT71 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 6. " XM70 ,Event EVT70 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XM69 ,Event EVT69 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 4. " XM68 ,Event EVT68 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 3. " XM67 ,Event EVT67 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " XM66 ,Event EVT66 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 1. " XM65 ,Event EVT65 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x08 0. " XM64 ,Event EVT64 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
line.long 0x0c "EXPMASK3,Exception Mask Register 3"
|
|
bitfld.long 0x0c 31. " XM127 ,Event EVT127 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 30. " XM126 ,Event EVT126 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 29. " XM125 ,Event EVT125 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " XM124 ,Event EVT124 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 27. " XM123 ,Event EVT123 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 26. " XM122 ,Event EVT122 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " XM121 ,Event EVT121 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 24. " XM120 ,Event EVT120 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 23. " XM119 ,Event EVT119 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " XM118 ,Event EVT118 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 21. " XM117 ,Event EVT117 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 20. " XM116 ,Event EVT116 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " XM113 ,Event EVT113 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 1. " XM97 ,Event EVT97 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
bitfld.long 0x0c 0. " XM96 ,Event EVT96 disabled from being used in the exception combiner" "Combined,Disabled"
|
|
width 11.
|
|
rgroup.long 0xa0++0xf
|
|
line.long 0x00 "MEVTFLAG0,Masked Event Flag Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " MEF[31:0] ,Displays content of EF when EM=0"
|
|
line.long 0x04 "MEVTFLAG1,Masked Event Flag Register 1"
|
|
hexmask.long 0x04 0.--31. 1. " MEF[63:32] ,Displays content of EF when EM=0"
|
|
line.long 0x08 "MEVTFLAG2,Masked Event Flag Register 2"
|
|
hexmask.long 0x08 0.--31. 1. " MEF[95:64] ,Displays content of EF when EM=0"
|
|
line.long 0x0c "MEVTFLAG3,Masked Event Flag Register 3"
|
|
hexmask.long 0x0c 0.--31. 1. " MEF[127:96] ,Displays content of EF when EM=0"
|
|
rgroup.long 0xe0++0xf
|
|
line.long 0x00 "MEXPFLAG0,Masked Exception Flag Register 0"
|
|
line.long 0x04 "MEXPFLAG1,Masked ExceptionFlag Register 1"
|
|
line.long 0x08 "MEXPFLAG2,Masked Exception Flag Register 2"
|
|
line.long 0x0c "MEXPFLAG3,Masked Exception Flag Register 3"
|
|
width 11.
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "INTMUX1,Interrupt Mux Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " INTSEL7 ,Number of the event that maps to CPUINT7"
|
|
hexmask.long.byte 0x00 16.--22. 1. " INTSEL6 ,Number of the event that maps to CPUINT6"
|
|
hexmask.long.byte 0x00 8.--14. 1. " INTSEL5 ,Number of the event that maps to CPUINT5"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INTSEL4 ,Number of the event that maps to CPUINT4"
|
|
line.long 0x04 "INTMUX2,Interrupt Mux Register 2"
|
|
hexmask.long.byte 0x04 24.--30. 1. " INTSEL11 ,Number of the event that maps to CPUINT11"
|
|
hexmask.long.byte 0x04 16.--22. 1. " INTSEL10 ,Number of the event that maps to CPUINT10"
|
|
hexmask.long.byte 0x04 8.--14. 1. " INTSEL9 ,Number of the event that maps to CPUINT9"
|
|
hexmask.long.byte 0x04 0.--6. 1. " INTSEL8 ,Number of the event that maps to CPUINT8"
|
|
line.long 0x08 "INTMUX3,Interrupt Mux Register 3"
|
|
hexmask.long.byte 0x08 24.--30. 1. " INTSEL15 ,Number of the event that maps to CPUINT15"
|
|
hexmask.long.byte 0x08 16.--22. 1. " INTSEL14 ,Number of the event that maps to CPUINT14"
|
|
hexmask.long.byte 0x08 8.--14. 1. " INTSEL13 ,Number of the event that maps to CPUINT13"
|
|
hexmask.long.byte 0x08 0.--6. 1. " INTSEL12 ,Number of the event that maps to CPUINT12"
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x00 "INTXSTAT,Interrupt Exception Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYSINT ,System Event number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUINT ,CPU interrupt number"
|
|
bitfld.long 0x00 0. " DROP ,Dropped event flag" "No event dropped,Event dropped"
|
|
width 11.
|
|
wgroup.long 0x184++0x3
|
|
line.long 0x00 "INTXCLR,Interrupt Exception Clear Register"
|
|
bitfld.long 0x00 0. " CLEAR ,Clears the interrupt exception status" "No effect,Cleared"
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x00 "INTDMASK,Dropped Interrupt Mask Register"
|
|
bitfld.long 0x00 15. " IDM15 ,Disables CPUINT15 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 14. " IDM14 ,Disables CPUINT14 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 13. " IDM13 ,Disables CPUINT13 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDM12 ,Disables CPUINT12 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 11. " IDM11 ,Disables CPUINT11 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 10. " IDM10 ,Disables CPUINT10 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDM9 ,Disables CPUINT9 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 8. " IDM8 ,Disables CPUINT8 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 7. " IDM7 ,Disables CPUINT7 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDM6 ,Disables CPUINT6 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 5. " IDM5 ,Disables CPUINT5 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
bitfld.long 0x00 4. " IDM4 ,Disables CPUINT4 from being detected by the drop detection hardware" "No effect,Ignored"
|
|
width 11.
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "AEGMUX0,Advanced Event Generator Mux Registers"
|
|
hexmask.long.byte 0x00 24.--31. 1. " AEGSEL3 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x00 16.--23. 1. " AEGSEL2 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x00 8.--15. 1. " AEGSEL1 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AEGSEL0 ,Advanced Event Generator Select"
|
|
line.long 0x04 "AEGMUX1,Advanced Event Generator Mux Registers"
|
|
hexmask.long.byte 0x04 24.--31. 1. " AEGSEL7 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x04 16.--23. 1. " AEGSEL6 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x04 8.--15. 1. " AEGSEL5 ,Advanced Event Generator Select"
|
|
hexmask.long.byte 0x04 0.--7. 1. " AEGSEL4 ,Advanced Event Generator Select"
|
|
width 0xb
|
|
tree.end
|
|
tree "Power-Down Controller"
|
|
width 8.
|
|
base d:0x01810000
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PDCCMD,Power-Down Controller Command Register"
|
|
bitfld.long 0x00 16. " MEGPD ,Power-down during IDLE" "Normal,Sleep mode"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
endif
|
|
sif (CORENAME()=="CORTEXR5F")
|
|
tree "Core Registers (Cortex-R5F)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
width 0x8
|
|
; --------------------------------------------------------------------------------
|
|
; Identification registers
|
|
; --------------------------------------------------------------------------------
|
|
tree "ID Registers"
|
|
rgroup.long c15:0x00++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
|
|
textline " "
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
|
|
bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c15:0x100++0x00
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
rgroup.long c15:0x400--0x400
|
|
line.long 0x0 "MPUIR,MPU type register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
|
|
bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
|
|
rgroup.long c15:0x500++0x00
|
|
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
|
|
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
|
|
textline " "
|
|
rgroup.long c15:0x0410++0x00
|
|
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..."
|
|
bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0510++0x00
|
|
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c15:0x0610++0x00
|
|
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c15:0x0710++0x00
|
|
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x020++0x00
|
|
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x120++0x00
|
|
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x220++0x00
|
|
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x320++0x00
|
|
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x420++0x00
|
|
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0520++0x00
|
|
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
|
|
rgroup.long c15:0x0620++0x00
|
|
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
|
|
rgroup.long c15:0x0720++0x00
|
|
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
|
|
rgroup.long c15:0x010++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x110++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
rgroup.long c15:0x210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c15:0x310++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c15:0x02f++0x00
|
|
line.long 0x00 "BO1R,Build Options 1 Register"
|
|
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM"
|
|
bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
|
|
group.long c15:0x12f++0x00
|
|
line.long 0x00 "BO2R,Build Options 2 Register"
|
|
bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2"
|
|
bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No"
|
|
bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
|
|
bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No"
|
|
bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
|
|
bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
|
|
bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
|
|
bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
|
|
bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
|
|
bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
|
|
bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes"
|
|
group.long c15:0x72f++0x00
|
|
line.long 0x00 "POR,Pin Options Register"
|
|
bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High"
|
|
bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High"
|
|
bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High"
|
|
tree.end
|
|
width 0x8
|
|
tree "System Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x101++0x00
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable"
|
|
bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
|
|
bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
|
|
bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
|
|
bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
|
|
bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x0f++0x00
|
|
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
|
|
bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x000b++0x00
|
|
line.long 0x00 "SPCR,Slave Port Control Register"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x05++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x15++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x06++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group.long c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group.long c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
width 0x08
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RBAR12,Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RSER12,Region Size and Enable Register 12"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RACR12,Region Access Control Register 12"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RBAR13,Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RSER13,Region Size and Enable Register 13"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RACR13,Region Access Control Register 13"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RBAR14,Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RSER14,Region Size and Enable Register 14"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RACR14,Region Access Control Register 14"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RBAR15,Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RSER15,Region Size and Enable Register 15"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RACR15,Region Access Control Register 15"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
textline " "
|
|
group.long c15:0x10f++0x00
|
|
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
group.long c15:0x20f++0x00
|
|
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
group.long c15:0x30f++0x00
|
|
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x00
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1700++0x00
|
|
line.long 0x00 "AIDR,Auxiliary ID Register"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000++0x00
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
group.long c15:0x5f++0x00
|
|
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
group.long c15:0xef++0x00
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Event Count Register"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree "Validation Registers"
|
|
group.long c15:0x01f++0x00
|
|
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x11f++0x00
|
|
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x21f++0x00
|
|
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x31f++0x00
|
|
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
group.long c15:0x41f++0x00
|
|
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x51f++0x00
|
|
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x61f++0x00
|
|
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x71f++0x00
|
|
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
tree.end
|
|
tree.end
|
|
width 11.
|
|
width 18.
|
|
tree "Debug Registers"
|
|
tree "Processor Identifier Registers"
|
|
rgroup.long c14:832.++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup.long c14:833.++0x00
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup.long c14:834.++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
group.long c14:835.++0x00
|
|
line.long 0x00 "AMIDR,Alias of MIDR"
|
|
rgroup.long c14:836.++0x00
|
|
line.long 0x00 "MPUTR,MPU Type Register"
|
|
rgroup.long c14:837.++0x00
|
|
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
|
|
group.long c14:838.++0x00
|
|
line.long 0x00 "AMIDR0,Alias of MIDR"
|
|
group.long c14:839.++0x00
|
|
line.long 0x00 "AMIDR1,Alias of MIDR"
|
|
rgroup.long c14:840.++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:841.++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:842.++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c14:843.++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c14:844.++0x00
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:845.++0x00
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c14:846.++0x00
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c14:847.++0x00
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:848.++0x00
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:849.++0x00
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:850.++0x00
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:851.++0x00
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:852.++0x00
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:853.++0x00
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 15.
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x00
|
|
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration"
|
|
group.long c14:1000.++0x00
|
|
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set"
|
|
group.long c14:1001.++0x00
|
|
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked"
|
|
rgroup.long c14:1006.++0x00
|
|
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled"
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
tree.end
|
|
textline " "
|
|
width 12.
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
textline " "
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
group.long c14:0x7++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled"
|
|
hgroup.long c14:32.++0x0
|
|
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group.long c14:35.++0x00
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group.long c14:10.++0x0
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes"
|
|
bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
textline " "
|
|
rgroup.long c14:193.++0x0
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
|
|
group.long c14:196.++0x0
|
|
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
|
|
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group.long c14:64.++0x0
|
|
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group.long c14:80.++0x0
|
|
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:65.++0x0
|
|
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group.long c14:81.++0x0
|
|
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:66.++0x0
|
|
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group.long c14:82.++0x0
|
|
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:67.++0x0
|
|
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group.long c14:83.++0x0
|
|
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:68.++0x0
|
|
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group.long c14:84.++0x0
|
|
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:69.++0x0
|
|
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group.long c14:85.++0x0
|
|
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:70.++0x0
|
|
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group.long c14:86.++0x0
|
|
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:71.++0x0
|
|
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group.long c14:87.++0x0
|
|
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:96.++0x0
|
|
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:112.++0x0
|
|
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:97.++0x0
|
|
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:113.++0x0
|
|
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:98.++0x0
|
|
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:114.++0x0
|
|
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:99.++0x0
|
|
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:115.++0x0
|
|
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:100.++0x0
|
|
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:116.++0x0
|
|
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:101.++0x0
|
|
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:117.++0x0
|
|
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:102.++0x0
|
|
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:118.++0x0
|
|
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:103.++0x0
|
|
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:119.++0x0
|
|
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:6.++0x0
|
|
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
width 11.
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (CORENAME()=="CORTEXM4")
|
|
tree.close "Core Registers (Cortex-M4)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
|
|
bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
|
|
bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
|
|
rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
|
|
bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
|
|
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "USAFAULT,Usage Fault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x07
|
|
line.long 0x00 "HFSR,Hard Fault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
line.long 0x04 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
|
|
bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
|
|
bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
|
|
group.long 0xD34++0x0B
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x04 "BFAR,BusFault Address Register"
|
|
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
|
|
width 10.
|
|
tree "Feature Registers"
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AWR2944DSP"))
|
|
tree "DSP_ICFG"
|
|
base ad:0x1800000
|
|
repeat 4. (list 0x3 0x2 0x1 0x0)(list 0x0 0x0 0x0 0x0)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "EVTFLAG0_$1,Event flags"
|
|
hexmask.long 0x0 0.--31. 1. "EF,"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "EVTFLAG1_$1,Event flags"
|
|
hexmask.long 0x0 0.--31. 1. "EF,"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "EVTFLAG2_$1,Event flags"
|
|
hexmask.long 0x0 0.--31. 1. "EF,"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "EVTFLAG3_$1,Event flags"
|
|
hexmask.long 0x0 0.--31. 1. "EF,"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "EVTSET0_$1,Event set command register"
|
|
hexmask.long 0x0 0.--31. 1. "ES,Event set command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x24)++0x3
|
|
line.long 0x0 "EVTSET1_$1,Event set command register"
|
|
hexmask.long 0x0 0.--31. 1. "ES,Event set command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "EVTSET2_$1,Event set command register"
|
|
hexmask.long 0x0 0.--31. 1. "ES,Event set command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVTSET3_$1,Event set command register"
|
|
hexmask.long 0x0 0.--31. 1. "ES,Event set command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "EVTCLR0_$1,Event clear command register"
|
|
hexmask.long 0x0 0.--31. 1. "EC,Event clear command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x44)++0x3
|
|
line.long 0x0 "EVTCLR1_$1,Event clear command register"
|
|
hexmask.long 0x0 0.--31. 1. "EC,Event clear command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x48)++0x3
|
|
line.long 0x0 "EVTCLR2_$1,Event clear command register"
|
|
hexmask.long 0x0 0.--31. 1. "EC,Event clear command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x4C)++0x3
|
|
line.long 0x0 "EVTCLR3_$1,Event clear command register"
|
|
hexmask.long 0x0 0.--31. 1. "EC,Event clear command"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "EVTMASK0_$1,Event mask register"
|
|
hexmask.long 0x0 0.--31. 1. "EM,Event mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x84)++0x3
|
|
line.long 0x0 "EVTMASK1_$1,Event mask register"
|
|
hexmask.long 0x0 0.--31. 1. "EM,Event mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x88)++0x3
|
|
line.long 0x0 "EVTMASK2_$1,Event mask register"
|
|
hexmask.long 0x0 0.--31. 1. "EM,Event mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x8C)++0x3
|
|
line.long 0x0 "EVTMASK3_$1,Event mask register"
|
|
hexmask.long 0x0 0.--31. 1. "EM,Event mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xA0)++0x3
|
|
line.long 0x0 "MEVTFLAG0_$1,Masked event flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEVTFLAG,Masked event flags"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xA4)++0x3
|
|
line.long 0x0 "MEVTFLAG1_$1,Masked event flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEVTFLAG,Masked event flags"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xA8)++0x3
|
|
line.long 0x0 "MEVTFLAG2_$1,Masked event flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEVTFLAG,Masked event flags"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xAC)++0x3
|
|
line.long 0x0 "MEVTFLAG3_$1,Masked event flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEVTFLAG,Masked event flags"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xC0)++0x3
|
|
line.long 0x0 "EXPMASK0_$1,Exception mask register"
|
|
hexmask.long 0x0 0.--31. 1. "XM,Exception mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xC4)++0x3
|
|
line.long 0x0 "EXPMASK1_$1,Exception mask register"
|
|
hexmask.long 0x0 0.--31. 1. "XM,Exception mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xC8)++0x3
|
|
line.long 0x0 "EXPMASK2_$1,Exception mask register"
|
|
hexmask.long 0x0 0.--31. 1. "XM,Exception mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xCC)++0x3
|
|
line.long 0x0 "EXPMASK3_$1,Exception mask register"
|
|
hexmask.long 0x0 0.--31. 1. "XM,Exception mask"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xE0)++0x3
|
|
line.long 0x0 "MEXPFLAG0_$1,Masked exception flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEXPFLAG,Masked exception flags"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xE4)++0x3
|
|
line.long 0x0 "MEXPFLAG1_$1,Masked exception flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEXPFLAG,Masked exception flags"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xE8)++0x3
|
|
line.long 0x0 "MEXPFLAG2_$1,Masked exception flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEXPFLAG,Masked exception flags"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xEC)++0x3
|
|
line.long 0x0 "MEXPFLAG3_$1,Masked exception flags"
|
|
hexmask.long 0x0 0.--31. 1. "MEXPFLAG,Masked exception flags"
|
|
repeat.end
|
|
repeat 3. (list 0x1 0x2 0x3)(list 0x0 0x4 0x8)
|
|
group.long ($2+0x104)++0x3
|
|
line.long 0x0 "INTMUX$1,Interrupt Mux Register"
|
|
bitfld.long 0x0 31. "_RESV3,Always read as 0. Writes have no affect." "0,1"
|
|
hexmask.long.byte 0x0 24.--30. 1. "INTSEL7,Interrupt selector 7"
|
|
bitfld.long 0x0 23. "_RESV2,Always read as 0. Writes have no affect." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "INTSEL6,Interrupt selector 6"
|
|
bitfld.long 0x0 15. "_RESV1,Always read as 0. Writes have no affect." "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "INTSEL5,Interrupt selector 5"
|
|
newline
|
|
bitfld.long 0x0 7. "_RESV0,Always read as 0. Writes have no affect." "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INTSEL4,Interrupt selector 4"
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "AEGMUX$1,AEG Event Mux Register"
|
|
hexmask.long.byte 0x0 24.--30. 1. "AEGSEL3,AEG event selector 3"
|
|
hexmask.long.byte 0x0 16.--22. 1. "AEGSEL2,AEG event selector 2"
|
|
hexmask.long.byte 0x0 8.--14. 1. "AEGSEL1,AEG event selector 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "AEGSEL0,AEG event selector 0"
|
|
repeat.end
|
|
group.long 0x180++0xB
|
|
line.long 0x0 "INTXSTAT,Interrupt Exception Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SYSINT,System event number"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CPUINT,CPU interrupt number"
|
|
hexmask.long.word 0x0 1.--15. 1. "_RESV3,Always read as 0. Writes have no affect."
|
|
newline
|
|
rbitfld.long 0x0 0. "DROP,Dropped event flag" "0,1"
|
|
line.long 0x4 "INTXCLR,Interrupt Exception Clear Register"
|
|
hexmask.long 0x4 1.--31. 1. "_RESV3,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x4 0. "CLEAR,Clear interrupt exception status" "0,1"
|
|
line.long 0x8 "INTDMASK,Dropped Interrupt Mask Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "_RESV1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x8 4.--15. 1. "IDM,Interrupt drop mask"
|
|
hexmask.long.byte 0x8 0.--3. 1. "_RESV0,Always read as 0. Writes have no affect."
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "EVTASRT,Event Assert Register"
|
|
bitfld.long 0x0 31. "MRA,Maximal Reset Request Assert" "0,1"
|
|
bitfld.long 0x0 30. "SRA,System Reset Request Assert" "0,1"
|
|
bitfld.long 0x0 29. "CRA,Chip Reset Request Assert" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LRA,Local Reset Request Assert" "0,1"
|
|
hexmask.long.tbyte 0x0 8.--27. 1. "_RESV0,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 0.--7. 1. "EA,Event Assert"
|
|
group.long 0x10000++0x3
|
|
line.long 0x0 "PDCCMD,"
|
|
hexmask.long.word 0x0 17.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 16. "GEMPD,Enable power-down during IDLE" "0,1"
|
|
bitfld.long 0x0 14.--15. "RESV_2,Always read as 0. Writes have no affect." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EMCLOG,EMC SRAM Sleep Mode" "0,1,2,3"
|
|
bitfld.long 0x0 10.--11. "RESV_3,Always read as 0. Writes have no affect." "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "UMCLOG,UMC SRAM Sleep Mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DMCMEM,DMC Logic Clock Gating" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "DMCLOG,DMC SRAM Sleep Mode" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "PMCMEM,PMC Logic Clock Gating" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PMCLOG,PMC SRAM Sleep Mode" "0,1,2,3"
|
|
group.long 0x12000++0x3
|
|
line.long 0x0 "MM_REVID,"
|
|
hexmask.long 0x0 0.--31. 1. "MM_REVID,"
|
|
group.long 0x20000++0x13
|
|
line.long 0x0 "IDMA0_STAT,IDMA Channel 0 Status"
|
|
hexmask.long 0x0 2.--31. 1. "_RESV1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 1. "PEND,Command pending" "0,1"
|
|
rbitfld.long 0x0 0. "ACTV,Command active" "0,1"
|
|
line.long 0x4 "IDMA0_MASK,IDMA Channel 0 Register Mask"
|
|
hexmask.long 0x4 0.--31. 1. "MASK,Register mask"
|
|
line.long 0x8 "IDMA0_SOURCE,IDMA Channel 0 Source Address"
|
|
hexmask.long 0x8 5.--31. 1. "SOURCEADDR,Source address"
|
|
hexmask.long.byte 0x8 0.--4. 1. "_RESV1,Always read as 0. Writes have no affect."
|
|
line.long 0xC "IDMA0_DEST,IDMA Channel 0 Destination Address"
|
|
hexmask.long 0xC 5.--31. 1. "DESTADDR,Destination address"
|
|
hexmask.long.byte 0xC 0.--4. 1. "_RESV1,Always read as 0. Writes have no affect."
|
|
line.long 0x10 "IDMA0_COUNT,IDMA Channel 0 Count"
|
|
bitfld.long 0x10 29.--31. "_RESV1,Always read as 0. Writes have no affect." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 28. "INT,Interrupt enable" "0,1"
|
|
hexmask.long.tbyte 0x10 4.--27. 1. "_RESV2,Always read as 0. Writes have no affect."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "COUNT,Transfer frame count"
|
|
group.long 0x20100++0x3
|
|
line.long 0x0 "IDMA1_STAT,"
|
|
hexmask.long 0x0 2.--31. 1. "_RESV1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 1. "PEND,Command pending" "0,1"
|
|
rbitfld.long 0x0 0. "ACTV,Command active" "0,1"
|
|
group.long 0x20108++0xB
|
|
line.long 0x0 "IDMA1_SOURCE,"
|
|
hexmask.long 0x0 2.--31. 1. "SOURCEADDR,Source address"
|
|
bitfld.long 0x0 0.--1. "_RESV1,Always read as 0. Writes have no affect." "0,1,2,3"
|
|
line.long 0x4 "IDMA1_DEST,"
|
|
hexmask.long 0x4 2.--31. 1. "DESTADDR,Destination address"
|
|
bitfld.long 0x4 0.--1. "_RESV1,Always read as 0. Writes have no affect." "0,1,2,3"
|
|
line.long 0x8 "IDMA1_COUNT,"
|
|
bitfld.long 0x8 29.--31. "PRI,Priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "INT,Interrupt enable" "0,1"
|
|
hexmask.long.word 0x8 17.--27. 1. "_RESV1,Always read as 0. Writes have no affect."
|
|
newline
|
|
bitfld.long 0x8 16. "FILL,Fill/Copy Mode Select" "0,1"
|
|
hexmask.long.word 0x8 2.--15. 1. "COUNT,Transfer word count"
|
|
bitfld.long 0x8 0.--1. "_RESV2,Always read as 0. Writes have no affect." "0,1,2,3"
|
|
group.long 0x20200++0xB
|
|
line.long 0x0 "CPUARBE,"
|
|
hexmask.long.word 0x0 19.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 16.--18. "PRI,Priority" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 6.--15. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MAXWAIT,Max wait count"
|
|
line.long 0x4 "IDMAARBE,"
|
|
hexmask.long 0x4 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x4 0.--5. 1. "MAXWAIT,Max wait count"
|
|
line.long 0x8 "SDMAARBE,"
|
|
hexmask.long 0x8 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x8 0.--5. 1. "MAXWAIT,Max wait count"
|
|
group.long 0x20210++0x3
|
|
line.long 0x0 "ECFGARBE,"
|
|
hexmask.long.word 0x0 19.--31. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 16.--18. "PRI,Priority" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--15. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rgroup.long 0x20300++0x3
|
|
line.long 0x0 "ICFGMPFAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,"
|
|
group.long 0x20304++0x7
|
|
line.long 0x0 "ICFGMPFSR,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 8.--15. 1. "FID,PrivID of faulting requestor"
|
|
rbitfld.long 0x0 7. "SECE,Security Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RESV_2,Always read as 0. Writes have no affect." "0,1"
|
|
rbitfld.long 0x0 5. "SR,Fault due to Supervisor Read" "0,1"
|
|
rbitfld.long 0x0 4. "SW,Fault due to Supervisor Write" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "SX,Fault due to Supervisor Execute" "0,1"
|
|
rbitfld.long 0x0 2. "UR,Fault due to User Read" "0,1"
|
|
rbitfld.long 0x0 1. "UW,Fault due to User Write" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "UX,Fault due to User Execute" "0,1"
|
|
line.long 0x4 "ICFGMPFCR,"
|
|
hexmask.long 0x4 1.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x4 0. "MPFCLR," "0,1"
|
|
group.long 0x20408++0x7
|
|
line.long 0x0 "ECFGERR,"
|
|
rbitfld.long 0x0 29.--31. "ERR,Error" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x0 12.--28. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 8.--11. 1. "XID,XID"
|
|
newline
|
|
hexmask.long.byte 0x0 3.--7. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 0.--2. "STAT,Status" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "ECFGERRCLR,"
|
|
hexmask.long 0x4 1.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x4 0. "CLR,Error clear" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x20500)++0x3
|
|
line.long 0x0 "PAMAP$1,PAMAP register"
|
|
hexmask.long 0x0 3.--31. 1. "_RESV1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 0.--2. "AID,AID" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
group.long 0x31100++0x23
|
|
line.long 0x0 "EDCINTMASK,This read write registers contains the masks for the exceptions generated by each of the EDC error detection units added in this change. Also contained in this register are the bit fields indicating which module has issued an exception. Reads.."
|
|
hexmask.long 0x0 7.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x0 6. "L1PTAG,L1PTAG Exception Enable: 1 enables the propagation of the exceptions generated from the error detector. Write 0 to disable exceptions." "0,1"
|
|
bitfld.long 0x0 5. "L2LRU,L2LRU Exception Enable: 1 enables the propagation of the exceptions generated from the error detector. Write 0 to disable exceptions." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "L2SNOP,L2SNOP Exception Enable: 1 enables the propagation of the exceptions generated from the error detector. Write 0 to disable exceptions." "0,1"
|
|
bitfld.long 0x0 3. "L2TAG,L2TAG Exception Enable: 1 enables the propagation of the exceptions generated from the error detector. Write 0 to disable exceptions." "0,1"
|
|
bitfld.long 0x0 2. "L2MPPA,L2DMPPA Exception Enable: 1 enables the propagation of the exceptions generated from the error detector. Write 0 to disable exceptions." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "L1DTAG,L1DTAG Exception Enable: 1 enables the propagation of the exceptions generated from the error detector. Write 0 to disable exceptions." "0,1"
|
|
bitfld.long 0x0 0. "L1DDATA,L1DDATA Exception Enable: 1 enables the propagation of the exceptions generated from the error detector. Write 0 to disable exceptions." "0,1"
|
|
line.long 0x4 "EDCINTFLG,This register loads the interrupt flags upon issue by the EDC detection module. These flags are loaded independently of any other flags. Upon a read operation all flags are cleared."
|
|
hexmask.long 0x4 7.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x4 6. "L1PTAG,L1P TAG Exception: 1 indicates that an exception has been issued from this error detector. Read of register clears bit." "0,1"
|
|
bitfld.long 0x4 5. "L2LRU,L2 LRU Exception: 1 indicates that an exception has been issued from this error detector. Read of register clears bit." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "L2MPPA,L2 MPPA Exception: 1 indicates that an exception has been issued from this error detector. Read of register clears bit." "0,1"
|
|
bitfld.long 0x4 3. "L2SNOP,L2 SNOP Exception: 1 indicates that an exception has been issued from this error detector. Read of register clears bit." "0,1"
|
|
bitfld.long 0x4 2. "L2TAG,L2TAG Exception: 1 indicates that an exception has been issued from this error detector. Read of register clears bit." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "L1DTAG,L1DTAG Exception: 1 indicates that an exception has been issued from this error detector. Read of register clears bit." "0,1"
|
|
bitfld.long 0x4 0. "L1DDATA,L1DDATA Exception: 1 indicates that an exception has been issued from this error detector. Read of register clears bit." "0,1"
|
|
line.long 0x8 "L1DEDCMD,This write only register provides control for enabling and disabling the ECC logic ofr the DMC. This register controls the parameters which are accumulated for the Data and Tag RAMs in the DMC. Enabling the ECC allows the counting of recoverable.."
|
|
hexmask.long.byte 0x8 26.--31. 1. "Reserved_4,Reserved"
|
|
bitfld.long 0x8 25. "CCLRTAG,Correctable Error Clear: Writing 1 clears the correctable error count in the DMCEDPECNT register This is a one-shot register and is cleared immediately." "0,1"
|
|
bitfld.long 0x8 24. "CCLRDATA,Non-Correctable Error Clear: Writeing 1 clears the noncorrectable error count in the DMCEDPECNT register. This is a one-shot register and is cleared immediately." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 18.--23. 1. "Reserved_3,Reserved"
|
|
bitfld.long 0x8 17. "NCCLTAG,Correctable Error Clear: Writing 1 clears the correctable error count in the DMCEDPECNT register This is a one-shot register and is cleared immediately." "0,1"
|
|
bitfld.long 0x8 16. "NCCLRDATA,Non-Correctable Error Clear: Writeing 1 clears the noncorrectable error count in the DMCEDPECNT register. This is a one-shot register and is cleared immediately." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 9.--15. 1. "Reserved_2,Reserved"
|
|
bitfld.long 0x8 8. "SUSPDATA,Suspend TAG: Write 1 to prevent hamming codes from being written into memory but allows data to be written." "0,1"
|
|
hexmask.long.byte 0x8 2.--7. 1. "Reserved,Reserved"
|
|
newline
|
|
bitfld.long 0x8 1. "ENTAG,Enable Data: Initialized to the active state (1) to disable EDC on Data write 0" "0,1"
|
|
bitfld.long 0x8 0. "ENDATA,Enable TAG: Initialized to the active state (1) to disable EDC on TAG write 0." "0,1"
|
|
line.long 0xC "L1DDCSTAT,This read only regsister contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located. . The error.."
|
|
bitfld.long 0xC 31. "CERR1,Correctable Error 1: Indicates that one correctable error has occurred and that they BANK BYTE and BITPOS values are valid. Cleared upon writing a 1 to L1DEDCMD.CCLRDATA" "?,1: Indicates that one correctable error has.."
|
|
bitfld.long 0xC 30. "CERR2,Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK BYTE and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L1DEDCMD.CCLRDATA" "0,1"
|
|
hexmask.long.tbyte 0xC 10.--29. 1. "Reserved,Reserved"
|
|
newline
|
|
bitfld.long 0xC 7.--9. "BANK,BANK Number: This value indicates the bank number of the error indicated when CERR1 is 1. This value is the lowest numbered bank if multiple banks error simultaneously. This value is set upon the first error occurring and is cleared by writing a 1.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 5.--6. "BYTE,Byte Number: This value indicates the byte number ot the error indicated when CERR1 is 1. This value is the lowest numbered byte if multiple bytes error simultaneously in the same bank.This value is set upon the first error occurring and is cleared.." "0,1,2,3"
|
|
bitfld.long 0xC 2.--4. "BITPOS,Bit Position: This value indicates the bit position of the error indicated when CERR1 is 1. This value is the specific single error bits from the byte indicated by BYTE and the bank indicated by BANK. This value is set upon the first error.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 1. "SUSP,Suspend: EDC logic is in suspend mode this value is representative of the state of the last write to L1DEDCMD.SUSPDATA." "0,1"
|
|
bitfld.long 0xC 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L1DEDCMD.ENDATA." "0,1"
|
|
line.long 0x10 "L1DDNCSTAT,This read only register contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located. This.."
|
|
bitfld.long 0x10 31. "NCERR1,Non-Correctable Error 1: Indicates that one correctable error has occurred and that they BANK BYTE and BITPOS values are valid. Cleared upon writing a 1 to L1DEDCMD.NCCLRDATA" "?,1: Indicates that one correctable error has.."
|
|
bitfld.long 0x10 30. "NCERR2,Non-Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK BYTE and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L1DEDCMD.NCCLRDATA" "0,1"
|
|
hexmask.long.tbyte 0x10 10.--29. 1. "Reserved,Reserved"
|
|
newline
|
|
bitfld.long 0x10 7.--9. "BANK,BANK Number: This value indicates the bank number of the error indicated when NCERR1 is 1. This value is the lowest numbered bank if multiple banks error simultaneously. This value is set upon the first error occurring and is cleared by writing a 1.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 5.--6. "BYTE,Byte Number: This value indicates the byte number ot the error indicated when NCERR1 is 1. This value is the lowest numbered byte if multiple bytes error simultaneously in the same bank.This value is set upon the first error occurring and is cleared.." "0,1,2,3"
|
|
bitfld.long 0x10 2.--4. "Reserved_2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 1. "SUSP,Suspend: EDC logic is in suspend mode this value is representative of the state of the last write to L1DEDCMD.SUSPDATA" "0,1"
|
|
bitfld.long 0x10 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L1DEDCMD.ENDATA." "0,1"
|
|
line.long 0x14 "L1DTCSTAT,This read only regsister contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located. The error.."
|
|
bitfld.long 0x14 31. "CERR1,Correctable Error 1: Indicates that one correctable error has occurred and that they BANK and BITPOS values are valid. Cleared upon writing a 1 to L1DEDCMD.CCLRDTAG" "?,1: Indicates that one correctable error has.."
|
|
bitfld.long 0x14 30. "CERR2,Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L1DEDCMD.CCLRTAG" "0,1"
|
|
hexmask.long.tbyte 0x14 9.--29. 1. "Reserved,Reserved"
|
|
newline
|
|
rbitfld.long 0x14 8. "BANK,Bank: Value indicates which bank the correctable error occurred in." "0,1"
|
|
bitfld.long 0x14 7. "CHANNEL,Channel: Access to the banks of the L1D TAG memory are split into channels: 1 = [53:43] [31:16] 2 = [42:32] [15:0] Bit Position is an index in the respective channels this will yield the error bit position." "0,1"
|
|
hexmask.long.byte 0x14 2.--6. 1. "BITPOS,Bit Position: This value indicates the bit position of the error indicated when CERR1 is 1. This value is the specific single error bits from the byte indicated by BYTE and the bank indicated by BANK. This value is set upon the first error.."
|
|
newline
|
|
bitfld.long 0x14 1. "SUSP,Suspend: EDC logic is in suspend mode this value is representative of the state of the last write to L1DEDCMD.SUSPDATA" "0,1"
|
|
bitfld.long 0x14 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L1DEDCMD.ENDATA." "0,1"
|
|
line.long 0x18 "L1DTNCSTAT,L1D Error Detect TAG Non-Correctable Status Register"
|
|
bitfld.long 0x18 31. "NCERR1,Non-Correctable Error 1: Indicates that one correctable error has occurred and that they BANK BYTE and BITPOS values are valid. Cleared upon writing a 1 to L1DEDCMD.NCCLRTAG" "?,1: Indicates that one correctable error has.."
|
|
bitfld.long 0x18 30. "NCERR2,Non-Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK BYTE and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L1DEDCMD.NCCLRTAG" "0,1"
|
|
hexmask.long.tbyte 0x18 8.--29. 1. "Reserved_2,Reserved"
|
|
newline
|
|
bitfld.long 0x18 7. "BANK,BANK Number: This value indicates the bank number of the error indicated when NCERR1 is 1. This value is the lowest numbered bank if multiple banks error simultaneously. This value is set upon the first error occurring and is cleared by writing a 1.." "0,1"
|
|
hexmask.long.byte 0x18 2.--6. 1. "Reserved,Reserved"
|
|
bitfld.long 0x18 1. "SUSP,Suspend: EDC logic is in suspend mode this value is representative of the state of the last write to L1DEDCMD.SUSPDATA" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L1DEDCMD.ENDATA." "0,1"
|
|
line.long 0x1C "L1DDEDADDR,The L1D Correctable Error Detection Address Register pair contain the additional information on correctable errors reported in the STATUS registers. The addresses for both correctable and noncorrectable errors are held in this register. The.."
|
|
hexmask.long.byte 0x1C 27.--31. 1. "Reserved_2,Reserved"
|
|
hexmask.long.word 0x1C 16.--26. 1. "NCADDR,Non-Correctable Address: The value in this field is qualified by L1DEDDNCSTATE.NCERR1 when that field is written to a 1 the address of the noncorrectable error is written to this register field. . Cleared upon writing a 1 to L1DEDCMD.NCCLRDATA"
|
|
hexmask.long.byte 0x1C 11.--15. 1. "Reserved,Reserved"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--10. 1. "CADDR,Correctable Address: The value in this field is qualified by L1DEDDNCSTATE.CERR1 when that field is written to a 1 the address of the non-correctable error is written to this register field. . Cleared upon writing a 1 to L1DEDCMD.NCCLRDATA"
|
|
line.long 0x20 "L1DTEDADDR,The L1D Correctable Error Detection Address Register pair contain the additional information on correctable errors reported in the STATUS registers. The address for both correctable and noncorrectable errors are held in this register. The.."
|
|
hexmask.long.byte 0x20 27.--31. 1. "Reserved_2,Reserved"
|
|
hexmask.long.word 0x20 16.--26. 1. "NCADDR,Non-Correctable Address: The value in this field is qualified by L1DEDDNCSTATE.NCERR1 when that field is written to a 1 the address of the noncorrectable error is written to this register field. . Cleared upon writing a 1 to L1DEDCMD.NCCLRDATA"
|
|
hexmask.long.byte 0x20 11.--15. 1. "Reserved,Reserved"
|
|
newline
|
|
hexmask.long.word 0x20 0.--10. 1. "CADDR,Correctable Address: The value in this field is qualified by L1DEDDNCSTATE.CERR1 when that field is written to a 1 the address of the non-correctable error is written to this register field. . Cleared upon writing a 1 to L1DEDCMD.NCCLRDATA"
|
|
rgroup.long 0x31124++0x3
|
|
line.long 0x0 "L1DEDCNT,The L1D TAG Error Detection Error Count Register.stores the error counts for correctable and noncorrectable errors which occur in the L1D Cache Memories. these counts are accumulated regardless of the exception mapping in the L1DEDCMD.."
|
|
hexmask.long.word 0x0 16.--31. 1. "NCPECNT,Non-correctable EDC error count. Shows the number of non-correctable errors which have occurred in the DMC memories since last reset. This counter is cleared by writing a zero value to the counter."
|
|
hexmask.long.word 0x0 0.--15. 1. "CPECNT,Correctable EDC error count: Shows the number of correctable errors which have occurred in the DMC memories since last reset. This counter is cleared by writing a zero value to the counter."
|
|
group.long 0x31128++0x2F
|
|
line.long 0x0 "L2TEDCMD,This write only register provides control for enabling and disabling the ECC logic ofr the UMC. This register controls the parameters which are accumulated for the Data and Tag RAMs in the DMC. Enabling the ECC allows the counting of recoverable.."
|
|
hexmask.long.word 0x0 20.--31. 1. "Reserved_3,Reserved"
|
|
bitfld.long 0x0 19. "CCLRSNOP,Correctable Error Clear SNOP: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
bitfld.long 0x0 18. "CCLRLRU,Correctable Error Clear LRU: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CCLRMPPA,Correctable Error Clear MPPA: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
bitfld.long 0x0 16. "CCLRTAG,Correctable Error Clear TAG: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "Reserved_2,Reserved"
|
|
newline
|
|
bitfld.long 0x0 11. "NCCLRSNOP,Non- Correctable Error Clear SNOP: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
bitfld.long 0x0 10. "NCCLRLRU,Non- Correctable Error Clear LRU: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
bitfld.long 0x0 9. "NCCLRMPPA,Non- Correctable Error Clear MPPA: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NCCLRTAG,Non- Correctable Error Clear TAG: writing 1 to this register cause the corresponding counter to be cleared. The value written to this register is a one shot event." "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "Reserved,Reserved"
|
|
bitfld.long 0x0 3. "SNPEDCEN,Enable EDC: writing a 1 to this register enables EDC on the SNOOP Memory" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LRUEDCEN,Enable EDC: writing a 1 to this register enables EDC on the LRU Memory" "0,1"
|
|
bitfld.long 0x0 1. "MPPAEDCEN,Enable EDC: writing a 1 to this register enables EDC on the MPPA Memory" "0,1"
|
|
bitfld.long 0x0 0. "TAGEDCEN,Enable EDC: writing a 1 to this register enables the EDC modules for this memory. This bit is persistent and must be actively written to 0 to disable the EDC modules." "0,1"
|
|
line.long 0x4 "L2TCSTAT,This read only regsister contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located."
|
|
rbitfld.long 0x4 31. "CERR1,Correctable Error 1: Indicates that one correctable error has occurred and that they BANK and BITPOS values are valid. Cleared upon writing a 1 to L2EDCMD.CCLRDTAG" "?,1: Indicates that one correctable error has.."
|
|
rbitfld.long 0x4 30. "CERR2,Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L2EDCMD.CCLRTAG" "0,1"
|
|
hexmask.long.tbyte 0x4 9.--29. 1. "Reserved_2,Reserved"
|
|
newline
|
|
rbitfld.long 0x4 8. "BANK,Bank: indicates which of the two banks (0 = BANK0 1 = BANK1) contains the correctable error. Cleared upon writing a 1 to L2EDCMD.CCLRTAG" "0: BANK0,1: BANK1) contains the correctable error"
|
|
rbitfld.long 0x4 7. "CHANNEL,Channel: Access to a bank are split therefore an indication of channel 1 = [41:21] 2 = [20:0] Bit Position is qualified from these as displacements within the channel." "0,1"
|
|
hexmask.long.byte 0x4 2.--6. 1. "BITPOS,Bit Position: This value indicates the bit position of the error indicated when CERR1 is 1. This value is the specific single error bits from the byte indicated by BYTE and the bank indicated by BANK. This value is set upon the first error.."
|
|
newline
|
|
bitfld.long 0x4 1. "Reserved,Reserved" "0,1"
|
|
rbitfld.long 0x4 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L1DEDCMD.ENDATA." "0,1"
|
|
line.long 0x8 "L2TNCSTAT,This read only register contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located."
|
|
rbitfld.long 0x8 31. "NCERR1,Non-Correctable Error 1: Indicates that one correctable error has occurred and that they BANK BYTE and BITPOS values are valid. Cleared upon writing a 1 to L1DEDCMD.NCCLRTAG" "?,1: Indicates that one correctable error has.."
|
|
rbitfld.long 0x8 30. "NCERR2,Non-Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK BYTE and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L1DEDCMD.NCCLRTAG" "0,1"
|
|
hexmask.long.tbyte 0x8 9.--29. 1. "Reserved_2,Reserved"
|
|
newline
|
|
rbitfld.long 0x8 8. "BANK,Bank: indicates which of the two banks (0 = BANK0 1 = BANK1) contains the correctable error. Cleared upon writing a 1 to L2EDCMD.CCLRTAG" "0: BANK0,1: BANK1) contains the correctable error"
|
|
hexmask.long.byte 0x8 1.--7. 1. "Reserved,Reserved"
|
|
rbitfld.long 0x8 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L1DEDCMD.ENDATA." "0,1"
|
|
line.long 0xC "L2TEDADDR,The L2Correctable Error Detection Address Register pair contain the additional information on correctable errors reported in1.3.1.12. With both exceptions activated. the TAG exception will take priority on simultaneous exceptions. The addres in.."
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|
hexmask.long.byte 0xC 27.--31. 1. "Reserved_2,Reserved"
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|
hexmask.long.word 0xC 16.--26. 1. "NCADDR,Non-Correctable Address: The value in this field is qualified by L2EDDNCSTATE.NCERR1 when that field is written to a 1 the address of the noncorrectable error is written to this register field. . Cleared upon writing a 1 to L2EDCMD.NCCLRDATA"
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hexmask.long.byte 0xC 11.--15. 1. "Reserved,Reserved"
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|
newline
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|
hexmask.long.word 0xC 0.--10. 1. "CADDR,Correctable Address: The value in this field is qualified by L2EDDNCSTATE.CERR1 when that field is written to a 1 the address of the non-correctable error is written to this register field. . Cleared upon writing a 1 to L2EDCMD.NCCLRDATA"
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|
line.long 0x10 "L2MCSTAT,This register is non-functional as the memory is protected by parity alone and thus is non-correctable."
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|
line.long 0x14 "L2MNCSTAT,This read only register contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located."
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rbitfld.long 0x14 31. "NCERR1,Non-Correctable Error 1: Indicates that one correctable error has occurred and that they BANK BYTE and BITPOS values are valid. Cleared upon writing a 1 to L2EDCMD.NCCLRMPPA" "?,1: Indicates that one correctable error has.."
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rbitfld.long 0x14 30. "NCERR2,Non-Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK BYTE and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L2EDCMD.NCCLRMPPA" "0,1"
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|
hexmask.long 0x14 1.--29. 1. "Reserved,Reserved"
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|
newline
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|
rbitfld.long 0x14 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L1DEDCMD.ENEDC" "0,1"
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|
line.long 0x18 "L2MEDADDR,The L2Correctable Error Detection Address Register pair contain the additional information on correctable errors reported in1.3.1.12. With both exceptions activated. the TAG exception will take priority on simultaneous exceptions."
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hexmask.long.byte 0x18 27.--31. 1. "Reserved_2,Reserved"
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hexmask.long.word 0x18 16.--26. 1. "NCADDR,Non-Correctable Address: The value in this field is qualified by L2EDSNCSTATE.NCERR1 when that field is written to a 1 the address of the non-correctable error is written to this register field. . Cleared upon writing a 1 to L2EDCMD.NCCLRMPPA"
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hexmask.long.word 0x18 0.--15. 1. "Reserved,Reserved"
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line.long 0x1C "L2SCSTAT,This read only regsister contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located."
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rbitfld.long 0x1C 31. "CERR1,Correctable Error 1: Indicates that one correctable error has occurred and that they BANK and BITPOS values are valid. Cleared upon writing a 1 to L2EDCMD.CCLRDSNOP" "?,1: Indicates that one correctable error has.."
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rbitfld.long 0x1C 30. "CERR2,Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L2EDCMD.CCLRSNOP" "0,1"
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hexmask.long.tbyte 0x1C 7.--29. 1. "Reserved_2,Reserved"
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|
newline
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hexmask.long.byte 0x1C 2.--6. 1. "BITPOS,Bit Position: This value indicates the bit position of the error indicated when CERR1 is 1. This value is the specific single error bits from the byte indicated by BYTE and the bank indicated by BANK. This value is set upon the first error.."
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bitfld.long 0x1C 1. "Reserved,Reserved" "0,1"
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rbitfld.long 0x1C 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L2EDCMD.ENEDC" "0,1"
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line.long 0x20 "L2SNCSTAT,This read only register contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located."
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rbitfld.long 0x20 31. "NCERR1,Non-Correctable Error 1: Indicates that one correctable error has occurred and that they BANK BYTE and BITPOS values are valid. Cleared upon writing a 1 to L2EDCMD.NCCLRSNOP" "?,1: Indicates that one correctable error has.."
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rbitfld.long 0x20 30. "NCERR2,Non-Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK BYTE and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L2EDCMD.NCCLRSNOP" "0,1"
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hexmask.long 0x20 1.--29. 1. "Reserved,Reserved"
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|
newline
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rbitfld.long 0x20 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L2EDCMD.ENEDC" "0,1"
|
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line.long 0x24 "L2SEDADDR,The L2Correctable Error Detection Address Register pair contain the additional information on correctable errors reported in1.3.1.12. With both exceptions activated. the TAG exception will take priority on simultaneous exceptions."
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hexmask.long.byte 0x24 26.--30. 1. "Reserved_2,Reserved"
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hexmask.long.word 0x24 16.--25. 1. "NCADDR,Non-Correctable Address: The value in this field is qualified by L2EDDNCSTATE.NCERR1 when that field is written to a 1 the address of the noncorrectable error is written to this register field. . Cleared upon writing a 1 to L2EDCMD.NCCLRSNOP"
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hexmask.long.byte 0x24 10.--15. 1. "Reserved,Reserved"
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|
newline
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hexmask.long.word 0x24 0.--9. 1. "CADDR,Correctable Address: The value in this field is qualified by L2EDDNCSTATE.CERR1 when that field is written to a 1 the address of the non-correctable error is written to this register field. . Cleared upon writing a 1 to L2EDCMD.NCCLRSNOP"
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line.long 0x28 "L2LCSTAT,This read only regsister contains the current error data for Correctable ECC errors. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located."
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rbitfld.long 0x28 31. "CERR1,Correctable Error 1: Indicates that one correctable error has occurred and that they BANK and BITPOS values are valid. Cleared upon writing a 1 to L2EDCMD.CCLRDLRU" "?,1: Indicates that one correctable error has.."
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rbitfld.long 0x28 30. "CERR2,Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L2EDCMD.CCLRLRU" "0,1"
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hexmask.long.tbyte 0x28 7.--29. 1. "Reserved_2,Reserved"
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|
newline
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hexmask.long.byte 0x28 2.--6. 1. "BITPOS,Bit Position: This value indicates the bit position of the error indicated when CERR1 is 1. This value is the specific single error bits from the byte indicated by BYTE and the bank indicated by BANK. This value is set upon the first error.."
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bitfld.long 0x28 1. "Reserved,Reserved" "0,1"
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rbitfld.long 0x28 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L2EDCMD.ENEDC" "0,1"
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line.long 0x2C "L2LNCSTAT,"
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bitfld.long 0x2C 31. "NCERR1,Non-Correctable Error 1: Indicates that one correctable error has occurred and that they BANK BYTE and BITPOS values are valid. Cleared upon writing a 1 to L2EDCMD.NCCLR:LRU" "?,1: Indicates that one correctable error has.."
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bitfld.long 0x2C 30. "NCERR2,Non-Correctable Error 2: Indicates that a subsequent correctable error has occurred BANK BYTE and BITPOS values are valid but apply to the error reported in CERR1. Cleared upon writing a 1 to L2EDCMD.NCCLRLRU" "0,1"
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hexmask.long 0x2C 1.--29. 1. "Reserved,Reserved"
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|
newline
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bitfld.long 0x2C 0. "EN,EDC Enable: Indicates EDC logic is enabled this value is representative of the state of the last write to L2EDCMD.ENEDC" "0,1"
|
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rgroup.long 0x31158++0x7
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line.long 0x0 "L2LEDADDR,The L2Correctable Error Detection Address Register pair contain the additional information on correctable errors reported in1.3.1.12. With both exceptions activated. the TAG exception will take priority on simultaneous exceptions."
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hexmask.long.word 0x0 16.--25. 1. "NCADDR,Non-Correctable Address: The value in this field is qualified by L2EDDNCSTATE.NCERR1 when that field is written to a 1 the address of the noncorrectable error is written to this register field. . Cleared upon writing a 1 to L2EDCMD.NCCLRLRU"
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hexmask.long.word 0x0 0.--9. 1. "CADDR,Correctable Address: The value in this field is qualified by L2EDDNCSTATE.CERR1 when that field is written to a 1 the address of the non-correctable error is written to this register field. . Cleared upon writing a 1 to L2EDCMD.NCCLRLRU"
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line.long 0x4 "L2TEDCNT,The L2 Error Detection Error Count Register.stores the error conts for correctable and non-correctable errors which occur in the L1D Data Memory. these counts are accumulated regardless of the exception mapping in the L1DEDCMD (0x0182_1108).."
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hexmask.long.word 0x4 16.--31. 1. "NCPECNT,Non-correctable EDC error count. Shows the number of non-correctable errors which have occurred in the DMC memories since last reset. This counter is cleared by writing a zero value to the counter. CPECNT 15-0 0 Correctable EDC error count:"
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hexmask.long.word 0x4 0.--15. 1. "CPECNT,Correctable EDC error count: Shows the number of correctable errors which have occurred in the DMC memories since last reset. This counter is cleared by writing a zero value to the counter."
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group.long 0x31160++0xF
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line.long 0x0 "L1PTEDCMD,This write only register provides control for enabling and disabling the Parity logic ofr the PMC. This register controls the parameters which are accumulated for the Data and Tag RAMs in the PMC. Enabling the Parity allows the counting of.."
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hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved"
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bitfld.long 0x0 5. "NCCLR,Non-Correctable Error Clear: Clears the non-correctable error count in the DMCEDPECNT register" "0,1"
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hexmask.long.byte 0x0 1.--4. 1. "Reserved,Reserved"
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newline
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bitfld.long 0x0 0. "EN,Enable Parity: Enables the Parity logic (parity_enable)" "0,1"
|
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line.long 0x4 "L1PTEDSTAT,This read only regsister contains the current error. The register provides information on whether the error was correctable or non-correctable. the requestor. and what position the error was located."
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rbitfld.long 0x4 31. "NCERR2,Non-Correctable Error: Indicates that there was a seconde non-correctable error Also indicates the logged error is valid." "0,1"
|
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rbitfld.long 0x4 30. "NCERR1,Non-Correctable Error: Indicates the first error was noncorrectable." "0,1"
|
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hexmask.long 0x4 1.--29. 1. "Reserved,Reserved"
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newline
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rbitfld.long 0x4 0. "EN,Enable: reflects the current state of the EN bit from L1PEDCMD" "0,1"
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line.long 0x8 "L1PTEDADDR,The address error registers for correctable and non-correctable errors are identical in structure. the indication applies to the correctable and non-correctable errors. they are both covered in this section. The register provides a record of.."
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hexmask.long.byte 0x8 27.--31. 1. "Reserved_2,Reserved"
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hexmask.long.word 0x8 16.--26. 1. "NCADDR,Non-Correctable Address: The value in this field is qualified by L1PEDDNCSTATE.NCERR when that field is written to a 1 the address of the non-correctable error is written to this register field. . Cleared upon writing a 1 to L1PEDCMD.NCCLRLR"
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hexmask.long.word 0x8 0.--15. 1. "Reserved,Reserved"
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line.long 0xC "L1DTEDCNT,This read only register contains the counts of correctable and non-correctable errors which have occurred. To reset these counts write to the DMCEDCMD register in the appropriate bit."
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hexmask.long.word 0xC 16.--31. 1. "NCPECNT,Non-correctable EDC error count. Shows the number of non-correctable errors which have occurred in the DMC memories since last reset. This counter is cleared by writing a zero value to the counter."
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hexmask.long.word 0xC 0.--15. 1. "Reserved,Reserved"
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group.long 0x40000++0x3
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line.long 0x0 "L2CFG,"
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hexmask.long.byte 0x0 28.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
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hexmask.long.byte 0x0 24.--27. 1. "NUM_MM,"
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hexmask.long.byte 0x0 20.--23. 1. "RESV_2,Always read as 0. Writes have no affect."
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newline
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hexmask.long.byte 0x0 16.--19. 1. "MMID,"
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hexmask.long.byte 0x0 10.--15. 1. "RESV_3,Always read as 0. Writes have no affect."
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bitfld.long 0x0 9. "IP," "0,1"
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newline
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bitfld.long 0x0 8. "ID," "0,1"
|
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bitfld.long 0x0 5.--7. "RESV_4,Always read as 0. Writes have no affect." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 3.--4. "L2CC," "0,1,2,3"
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newline
|
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bitfld.long 0x0 0.--2. "L2MODE," "0,1,2,3,4,5,6,7"
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group.long 0x40020++0x7
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line.long 0x0 "L1PCFG,"
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hexmask.long 0x0 3.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
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bitfld.long 0x0 0.--2. "L1PMODE," "0,1,2,3,4,5,6,7"
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line.long 0x4 "L1PCC,"
|
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hexmask.long.word 0x4 19.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
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rbitfld.long 0x4 16.--18. "POPER," "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x4 3.--15. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
newline
|
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bitfld.long 0x4 0.--2. "OPER," "0,1,2,3,4,5,6,7"
|
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group.long 0x40040++0x7
|
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line.long 0x0 "L1DCFG,"
|
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hexmask.long 0x0 3.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
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bitfld.long 0x0 0.--2. "L1DMODE," "0,1,2,3,4,5,6,7"
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line.long 0x4 "L1DCC,"
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hexmask.long.word 0x4 19.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
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rbitfld.long 0x4 16.--18. "POPER," "0,1,2,3,4,5,6,7"
|
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hexmask.long.word 0x4 3.--15. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
newline
|
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bitfld.long 0x4 0.--2. "OPER," "0,1,2,3,4,5,6,7"
|
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group.long 0x41000++0x13
|
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line.long 0x0 "CPUARBU,"
|
|
hexmask.long.word 0x0 19.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
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bitfld.long 0x0 16.--18. "PRI,Priority" "0,1,2,3,4,5,6,7"
|
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hexmask.long.word 0x0 6.--15. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "MAXWAIT,Max wait count"
|
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line.long 0x4 "IDMAARBU,"
|
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hexmask.long 0x4 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
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hexmask.long.byte 0x4 0.--5. 1. "MAXWAIT,Max wait count"
|
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line.long 0x8 "SDMAARBU,"
|
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hexmask.long 0x8 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x8 0.--5. 1. "MAXWAIT,Max wait count"
|
|
line.long 0xC "UCARBU,"
|
|
hexmask.long 0xC 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0xC 0.--5. 1. "MAXWAIT,Max wait count"
|
|
line.long 0x10 "MDMAARBU,"
|
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hexmask.long.byte 0x10 27.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x10 24.--26. "UPRI,Elevated priority" "0,1,2,3,4,5,6,7"
|
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hexmask.long.byte 0x10 19.--23. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
newline
|
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bitfld.long 0x10 16.--18. "PRI,Default priority" "0,1,2,3,4,5,6,7"
|
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hexmask.long.word 0x10 0.--15. 1. "RESV_3,Always read as 0. Writes have no affect."
|
|
group.long 0x41040++0xF
|
|
line.long 0x0 "CPUARBD,"
|
|
hexmask.long.word 0x0 19.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 16.--18. "PRI,Priority" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 6.--15. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "MAXWAIT,Max wait count"
|
|
line.long 0x4 "IDMAARBD,"
|
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hexmask.long 0x4 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x4 0.--5. 1. "MAXWAIT,Max wait count"
|
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line.long 0x8 "SDMAARBD,"
|
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hexmask.long 0x8 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x8 0.--5. 1. "MAXWAIT,Max wait count"
|
|
line.long 0xC "UCARBD,"
|
|
hexmask.long 0xC 6.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0xC 0.--5. 1. "MAXWAIT,Max wait count"
|
|
wgroup.long 0x44000++0x3
|
|
line.long 0x0 "L2WBAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Write only address register."
|
|
group.long 0x44004++0x3
|
|
line.long 0x0 "L2WWC,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x0 0.--15. 1. "WC,"
|
|
wgroup.long 0x44010++0x3
|
|
line.long 0x0 "L2WIBAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Write only address register."
|
|
group.long 0x44014++0x3
|
|
line.long 0x0 "L2WIWC,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x0 0.--15. 1. "WC,"
|
|
wgroup.long 0x44018++0x3
|
|
line.long 0x0 "L2IBAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Write only address register."
|
|
group.long 0x4401C++0x3
|
|
line.long 0x0 "L2IWC,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x0 0.--15. 1. "WC,"
|
|
wgroup.long 0x44020++0x3
|
|
line.long 0x0 "L1PIBAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Write only address register."
|
|
group.long 0x44024++0x3
|
|
line.long 0x0 "L1PIWC,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x0 0.--15. 1. "WC,"
|
|
wgroup.long 0x44030++0x3
|
|
line.long 0x0 "L1DWIBAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Write only address register"
|
|
group.long 0x44034++0x3
|
|
line.long 0x0 "L1DWIWC,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x0 0.--15. 1. "WC,"
|
|
wgroup.long 0x44040++0x3
|
|
line.long 0x0 "L1DWBAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Write only address register"
|
|
group.long 0x44044++0x3
|
|
line.long 0x0 "L1DWWC,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x0 0.--15. 1. "WC,"
|
|
wgroup.long 0x44048++0x3
|
|
line.long 0x0 "L1DIBAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Write only address register"
|
|
group.long 0x4404C++0x3
|
|
line.long 0x0 "L1DIWC,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.word 0x0 0.--15. 1. "WC,"
|
|
group.long 0x45000++0xB
|
|
line.long 0x0 "L2WB,"
|
|
hexmask.long 0x0 0.--31. 1. "C,"
|
|
line.long 0x4 "L2WBINV,"
|
|
hexmask.long 0x4 0.--31. 1. "C,"
|
|
line.long 0x8 "L2INV,"
|
|
hexmask.long 0x8 0.--31. 1. "I,"
|
|
group.long 0x45028++0x3
|
|
line.long 0x0 "L1PINV,"
|
|
hexmask.long 0x0 0.--31. 1. "I,"
|
|
group.long 0x45040++0xB
|
|
line.long 0x0 "L1DWB,"
|
|
hexmask.long 0x0 0.--31. 1. "C,"
|
|
line.long 0x4 "L1DWBINV,"
|
|
hexmask.long 0x4 0.--31. 1. "C,"
|
|
line.long 0x8 "L1DINV,"
|
|
hexmask.long 0x8 0.--31. 1. "I,"
|
|
group.long 0x46004++0xB
|
|
line.long 0x0 "L2EDSTAT,L2 EDC Status register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 16.--23. 1. "BITPOS,Bit position of Error"
|
|
hexmask.long.byte 0x0 10.--15. 1. "RESV2,Always read as 0. Writes have no affect."
|
|
newline
|
|
rbitfld.long 0x0 8.--9. "NERR,Non correctable Error" "0,1,2,3"
|
|
rbitfld.long 0x0 7. "VERR,Victim EDC Error" "0,1"
|
|
rbitfld.long 0x0 6. "DMAERR,DMA EDC Error" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "PERR,PMC Data EDC Error" "0,1"
|
|
rbitfld.long 0x0 4. "DERR,DMC Data EDC Error" "0,1"
|
|
rbitfld.long 0x0 3. "SUSP,EDC Suspend" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "DIS,EDC Disable" "0,1"
|
|
bitfld.long 0x0 1. "RESV3,Always read as 0. Writes have no affect." "0,1"
|
|
rbitfld.long 0x0 0. "EN,EDC Enable" "0,1"
|
|
line.long 0x4 "L2EDCMD,L2 EDC Command register"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x4 7. "VCLR,Victim EDC Error" "0,1"
|
|
bitfld.long 0x4 6. "DMACLR,DMA EDC Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PCLR,PMC Data EDC Error" "0,1"
|
|
bitfld.long 0x4 4. "DCLR,DMC Data EDC Error" "0,1"
|
|
bitfld.long 0x4 3. "SUSP,EDC Suspend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DIS,EDC Disable" "0,1"
|
|
bitfld.long 0x4 1. "RESV3,Always read as 0. Writes have no affect." "0,1"
|
|
bitfld.long 0x4 0. "EN,EDC Enable" "0,1"
|
|
line.long 0x8 "L2EDADDR,L2 EDC error address"
|
|
hexmask.long 0x8 5.--31. 1. "ADDR,L2 Error detection address"
|
|
rbitfld.long 0x8 3.--4. "WAY,Addr way" "0,1,2,3"
|
|
bitfld.long 0x8 1.--2. "RESV1,Always read as 0. Writes have no affect." "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x8 0. "RAM,Addr is sram" "0,1"
|
|
group.long 0x46018++0xF
|
|
line.long 0x0 "L2EDCPEC,L2 EDC correctable error count"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNT,count"
|
|
line.long 0x4 "L2EDCNEC,L2 EDC noncorrectable error count"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CNT,count"
|
|
line.long 0x8 "MDMAERR,"
|
|
rbitfld.long 0x8 29.--31. "ERR,Error" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x8 12.--28. 1. "RESV_2,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x8 8.--11. 1. "XID,XID"
|
|
newline
|
|
hexmask.long.byte 0x8 3.--7. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x8 0.--2. "STAT,Status" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "MDMAERRCLR,"
|
|
hexmask.long 0xC 1.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0xC 0. "CLR,Error clear" "0,1"
|
|
group.long 0x46030++0x3
|
|
line.long 0x0 "L2EDCEN,L2 EDC enable register"
|
|
hexmask.long 0x0 5.--31. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 4. "SDMAEN,Enable edc on sdma reads to l2 sram" "0,1"
|
|
bitfld.long 0x0 3. "PL2SEN,Enable edc on pmc hits to l2 sram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DL2SEN,Enable edc on dmc hits to l2 sram" "0,1"
|
|
bitfld.long 0x0 1. "PL2CEN,Enable edc on pmc hits to l2 cache" "0,1"
|
|
bitfld.long 0x0 0. "DL2CEN,Enable edc on dmc hits to l2 cache" "0,1"
|
|
group.long 0x46404++0xB
|
|
line.long 0x0 "L1PEDSTAT,L1P EDC Status register"
|
|
hexmask.long 0x0 7.--31. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 6. "DMAERR,DMA Error" "0,1"
|
|
rbitfld.long 0x0 5. "PERR,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RESV2,Always read as 0. Writes have no affect." "0,1"
|
|
rbitfld.long 0x0 3. "SUSP,EDC Suspend" "0,1"
|
|
rbitfld.long 0x0 2. "DIS,EDC Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RESV3,Always read as 0. Writes have no affect." "0,1"
|
|
rbitfld.long 0x0 0. "EN,EDC Enable" "0,1"
|
|
line.long 0x4 "L1PEDCMD,L1P EDC Command register"
|
|
hexmask.long 0x4 7.--31. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x4 6. "DMACLR,Clear DMA Error" "0,1"
|
|
bitfld.long 0x4 5. "PCLR,Clear Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RESV2,Always read as 0. Writes have no affect." "0,1"
|
|
bitfld.long 0x4 3. "SUSP,EDC Suspend" "0,1"
|
|
bitfld.long 0x4 2. "DIS,EDC Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RESV3,Always read as 0. Writes have no affect." "0,1"
|
|
bitfld.long 0x4 0. "EN,EDC Enable" "0,1"
|
|
line.long 0x8 "L1PEDADDR,L1P EDC error address"
|
|
hexmask.long 0x8 5.--31. 1. "ADDR,L1P Error detection address"
|
|
hexmask.long.byte 0x8 1.--4. 1. "RESV1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x8 0. "RAM,Addr is sram" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F)(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F)(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF)(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF)(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF)(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF)(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF)(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC)
|
|
group.long ($2+0x48000)++0x3
|
|
line.long 0x0 "MAR_$1,MAR register"
|
|
hexmask.long 0x0 4.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x0 3. "PFX,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 2. "PCX,Hard coded to 0" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "WTE,Hard coded to 0" "0,1"
|
|
rbitfld.long 0x0 0. "PC,Hard coded to 1" "0,1"
|
|
repeat.end
|
|
rgroup.long 0x4A000++0x3
|
|
line.long 0x0 "L2MPFAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,"
|
|
group.long 0x4A004++0x7
|
|
line.long 0x0 "L2MPFSR,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 9.--15. 1. "FID,PrivID of faulting requestor"
|
|
rbitfld.long 0x0 8. "LOCAL,Fault due to local CPU access" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 7. "NS,Fault due to non-secure code" "0,1"
|
|
bitfld.long 0x0 6. "RESV_2,Always read as 0. Writes have no affect." "0,1"
|
|
rbitfld.long 0x0 5. "SR,Fault due to Supervisor Read" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "SW,Fault due to Supervisor Write" "0,1"
|
|
rbitfld.long 0x0 3. "SX,Fault due to Supervisor Execute" "0,1"
|
|
rbitfld.long 0x0 2. "UR,Fault due to User Read" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "UW,Fault due to User Write" "0,1"
|
|
rbitfld.long 0x0 0. "UX,Fault due to User Execute" "0,1"
|
|
line.long 0x4 "L2MPFCR,"
|
|
hexmask.long 0x4 1.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x4 0. "MPFCLR," "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x4A200)++0x3
|
|
line.long 0x0 "L2MPPA_$1,L2 Memory Protection Page Attribute register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 15. "AID5,Allow ID 5 to access page" "0,1"
|
|
bitfld.long 0x0 14. "AID4,Allow ID 4 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AID3,Allow ID 3 to access page" "0,1"
|
|
bitfld.long 0x0 12. "AID2,Allow ID 2 to access page" "0,1"
|
|
bitfld.long 0x0 11. "AID1,Allow ID 1 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "AID0,Allow ID 0 to access page" "0,1"
|
|
bitfld.long 0x0 9. "AIDX,Allow IDs > 5 to access page" "0,1"
|
|
bitfld.long 0x0 8. "LOCAL,Allow CPU to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "NS,Non-secure (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 6. "EMU,Emulatable (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 5. "SR,Supervisor Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SW,Supervisor Write Access" "0,1"
|
|
bitfld.long 0x0 3. "SX,Supervisor Execute Access" "0,1"
|
|
bitfld.long 0x0 2. "UR,User Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "UW,User Write Access" "0,1"
|
|
bitfld.long 0x0 0. "UX,User Execute Access" "0,1"
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
group.long ($2+0x4A200)++0x3
|
|
line.long 0x0 "L2MPPA_$1,L2 Memory Protection Page Attribute register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 15. "AID5,Allow ID 5 to access page" "0,1"
|
|
bitfld.long 0x0 14. "AID4,Allow ID 4 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AID3,Allow ID 3 to access page" "0,1"
|
|
bitfld.long 0x0 12. "AID2,Allow ID 2 to access page" "0,1"
|
|
bitfld.long 0x0 11. "AID1,Allow ID 1 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "AID0,Allow ID 0 to access page" "0,1"
|
|
bitfld.long 0x0 9. "AIDX,Allow IDs > 5 to access page" "0,1"
|
|
bitfld.long 0x0 8. "LOCAL,Allow CPU to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "NS,Non-secure (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 6. "EMU,Emulatable (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 5. "SR,Supervisor Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SW,Supervisor Write Access" "0,1"
|
|
bitfld.long 0x0 3. "SX,Supervisor Execute Access" "0,1"
|
|
bitfld.long 0x0 2. "UR,User Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "UW,User Write Access" "0,1"
|
|
bitfld.long 0x0 0. "UX,User Execute Access" "0,1"
|
|
repeat.end
|
|
rgroup.long 0x4A400++0x3
|
|
line.long 0x0 "L1PMPFAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,"
|
|
group.long 0x4A404++0x7
|
|
line.long 0x0 "L1PMPFSR,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 9.--15. 1. "FID,PrivID of faulting requestor"
|
|
rbitfld.long 0x0 8. "LOCAL,Fault due to local CPU access" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 7. "NS,Fault due to non-secure code" "0,1"
|
|
bitfld.long 0x0 6. "RESV_2,Always read as 0. Writes have no affect." "0,1"
|
|
rbitfld.long 0x0 5. "SR,Fault due to Supervisor Read" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "SW,Fault due to Supervisor Write" "0,1"
|
|
rbitfld.long 0x0 3. "SX,Fault due to Supervisor Execute" "0,1"
|
|
rbitfld.long 0x0 2. "UR,Fault due to User Read" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "UW,Fault due to User Write" "0,1"
|
|
rbitfld.long 0x0 0. "UX,Fault due to User Execute" "0,1"
|
|
line.long 0x4 "L1PMPFCR,"
|
|
hexmask.long 0x4 1.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x4 0. "MPFCLR," "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x4A640)++0x3
|
|
line.long 0x0 "L1PMPPA_$1,L1P Memory Protection Page Attribute register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 15. "AID5,Allow ID 5 to access page" "0,1"
|
|
bitfld.long 0x0 14. "AID4,Allow ID 4 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AID3,Allow ID 3 to access page" "0,1"
|
|
bitfld.long 0x0 12. "AID2,Allow ID 2 to access page" "0,1"
|
|
bitfld.long 0x0 11. "AID1,Allow ID 1 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "AID0,Allow ID 0 to access page" "0,1"
|
|
bitfld.long 0x0 9. "AIDX,Allow IDs > 5 to access page" "0,1"
|
|
bitfld.long 0x0 8. "LOCAL,Allow CPU to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "NS,Non-secure (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 6. "EMU,Emulatable (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 5. "SR,Supervisor Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SW,Supervisor Write Access" "0,1"
|
|
bitfld.long 0x0 3. "SX,Supervisor Execute Access" "0,1"
|
|
bitfld.long 0x0 2. "UR,User Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "UW,User Write Access" "0,1"
|
|
bitfld.long 0x0 0. "UX,User Execute Access" "0,1"
|
|
repeat.end
|
|
rgroup.long 0x4AC00++0x3
|
|
line.long 0x0 "L1DMPFAR,"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,"
|
|
group.long 0x4AC04++0x7
|
|
line.long 0x0 "L1DMPFSR,"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
hexmask.long.byte 0x0 9.--15. 1. "FID,PrivID of faulting requestor"
|
|
rbitfld.long 0x0 8. "LOCAL,Fault due to local CPU access" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 7. "NS,Fault due to non-secure code" "0,1"
|
|
bitfld.long 0x0 6. "RESV_2,Always read as 0. Writes have no affect." "0,1"
|
|
rbitfld.long 0x0 5. "SR,Fault due to Supervisor Read" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "SW,Fault due to Supervisor Write" "0,1"
|
|
rbitfld.long 0x0 3. "SX,Fault due to Supervisor Execute" "0,1"
|
|
rbitfld.long 0x0 2. "UR,Fault due to User Read" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 1. "UW,Fault due to User Write" "0,1"
|
|
rbitfld.long 0x0 0. "UX,Fault due to User Execute" "0,1"
|
|
line.long 0x4 "L1DMPFCR,"
|
|
hexmask.long 0x4 1.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x4 0. "MPFCLR," "0,1"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
wgroup.long ($2+0x4AD00)++0x3
|
|
line.long 0x0 "MPLK_$1,MPLK register"
|
|
hexmask.long 0x0 0.--31. 1. "MPLK,"
|
|
repeat.end
|
|
group.long 0x4AD10++0x7
|
|
line.long 0x0 "MPLKCMD,"
|
|
hexmask.long 0x0 3.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 2. "KEYR," "0,1"
|
|
bitfld.long 0x0 1. "LOCK," "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UNLOCK," "0,1"
|
|
line.long 0x4 "MPLKSTAT,"
|
|
hexmask.long 0x4 2.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
rbitfld.long 0x4 1. "NSL," "0,1"
|
|
rbitfld.long 0x4 0. "LK," "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x4AE40)++0x3
|
|
line.long 0x0 "L1DMPPA_$1,L1D Memory Protection Page Attribute register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RESV_1,Always read as 0. Writes have no affect."
|
|
bitfld.long 0x0 15. "AID5,Allow ID 5 to access page" "0,1"
|
|
bitfld.long 0x0 14. "AID4,Allow ID 4 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AID3,Allow ID 3 to access page" "0,1"
|
|
bitfld.long 0x0 12. "AID2,Allow ID 2 to access page" "0,1"
|
|
bitfld.long 0x0 11. "AID1,Allow ID 1 to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "AID0,Allow ID 0 to access page" "0,1"
|
|
bitfld.long 0x0 9. "AIDX,Allow IDs > 5 to access page" "0,1"
|
|
bitfld.long 0x0 8. "LOCAL,Allow CPU to access page" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "NS,Non-secure (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 6. "EMU,Emulatable (Secure devices only)" "0,1"
|
|
bitfld.long 0x0 5. "SR,Supervisor Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SW,Supervisor Write Access" "0,1"
|
|
bitfld.long 0x0 3. "SX,Supervisor Execute Access" "0,1"
|
|
bitfld.long 0x0 2. "UR,User Read Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "UW,User Write Access" "0,1"
|
|
bitfld.long 0x0 0. "UX,User Execute Access" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "DSS_CBUFF"
|
|
base ad:0x6040000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CONFIG_REG_0,Basic Config register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "dbussel,TI Internal feature. 1 : This selects the debug bus mode transmission on LVDS"
|
|
newline
|
|
bitfld.long 0x0 27. "cswcrst,CBUFF controller SW Reset 1 => RESET the CBUFF Controller 0 => RELEASE RESET for CBUFF Controller" "0: RELEASE RESET for CBUFF Controller,1: RESET the CBUFF Controller"
|
|
newline
|
|
bitfld.long 0x0 26. "cswlrst,TI Internal Feature. LVDS logic SW Reset. Debug feature. 1 => RESET the FSM 0 => RELEASE RESET" "0: RELEASE RESET,1: RESET the FSM"
|
|
newline
|
|
bitfld.long 0x0 25. "CFG_FRAME_START_TRIG,SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CFG_CHIRP_AVAIL_TRIG,SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "CFG_VBUSP_BURST_EN,TI Internal Feature. Only required for 900 Mbps 4 lane trasnmission CSI2 only Programming : 0xA : Burst Enable. Set this only for transmission at 900 Mbps Others : Burst disable."
|
|
newline
|
|
bitfld.long 0x0 19. "dbusen,TC2 Mode selection. TI Internal feature. 0 : Normal 1 : When in TC2 mode setting this bit will enable debug bus to sent via LVDS" "0: Normal,1: When in TC2 mode"
|
|
newline
|
|
bitfld.long 0x0 18. "ccfwpen,TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_PROCESSING_EN 0 : Use the fifo_free_words directly from CSI2 by vbusp_mstr to decide how many more words to send. 1 : Process the fifo_free_words and use it by.." "0: Use the fifo_free_words directly from CSI2 by..,1: Process the fifo_free_words and use it by.."
|
|
newline
|
|
bitfld.long 0x0 16.--17. "cvc3en,CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 3 is generated at end of Frame 3 : A VSYNC Start.." "0: No Vsync packet is sent at Frame boundary,1: A VSYNC Start packet on Virtual Channel 3 is..,2: A VSYNC End packet on Virtual Channel 3 is..,3: A VSYNC Start packet on Virtual Channel 3 is.."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "cvc2en,CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 2 is generated at end of Frame 3 : A VSYNC Start.." "0: No Vsync packet is sent at Frame boundary,1: A VSYNC Start packet on Virtual Channel 2 is..,2: A VSYNC End packet on Virtual Channel 2 is..,3: A VSYNC Start packet on Virtual Channel 2 is.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "cvc1en,CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 1 is generated at end of Frame 3 : A VSYNC Start.." "0: No Vsync packet is sent at Frame boundary,1: A VSYNC Start packet on Virtual Channel 1 is..,2: A VSYNC End packet on Virtual Channel 1 is..,3: A VSYNC Start packet on Virtual Channel 1 is.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "cvc0en,CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 0 is generated at end of Frame 3 : A VSYNC Start.." "0: No Vsync packet is sent at Frame boundary,1: A VSYNC Start packet on Virtual Channel 0 is..,2: A VSYNC End packet on Virtual Channel 0 is..,3: A VSYNC Start packet on Virtual Channel 0 is.."
|
|
newline
|
|
bitfld.long 0x0 9. "crdthsel,TI Internal Feature. Debug only. CSI2 only Programming : CFG_RDTHRESHOLD_SEL . This is a Debug feature. Not requred in Programming model 0 : The read threshold is selected based on the Write Side parsing engine 1 : The read threshold is.." "0: The read threshold is selected based on the..,1: The read threshold is selected based on the Read.."
|
|
newline
|
|
bitfld.long 0x0 8. "ccfwlen,TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_LOAD_SW_EN. This is a Debug feature. Not requred in Programming model When CFG_CSI2_FIFO_WORDS_PROCESSING_EN==1 and CFG_CSI2_FIFO_WORDS_LOAD_SW_EN==1 then a fixed.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "NU1,"
|
|
newline
|
|
bitfld.long 0x0 3. "CFG_SW_TRIG_EN,Select Chirp Available Trigger Source 0 : Chirp Available trigger will be generated by HW 1 : Chirp Available trigger will be generated by SW" "0: Chirp Available trigger will be generated by HW,1: Chirp Available trigger will be generated by SW"
|
|
newline
|
|
bitfld.long 0x0 2. "cftrigen,Select Frame Start Trigger Source 0 : Frame trigger will be generated by HW 1 : Frame trigger will be generated by SW" "0: Frame trigger will be generated by HW,1: Frame trigger will be generated by SW"
|
|
newline
|
|
bitfld.long 0x0 1. "CFG_ECC_EN,0 : Disable ECC on the CBUF FIFO 1 : Enable ECC on the CBUF FIFO" "0: Disable ECC on the CBUF FIFO,1: Enable ECC on the CBUF FIFO"
|
|
newline
|
|
bitfld.long 0x0 0. "CFG_1LVDS_0CSI,0 : Send data over CSI-2 1 : Send data over LVDS" "0: Send data over CSI-2,1: Send data over LVDS"
|
|
line.long 0x4 "CFG_SPHDR_ADDRESS,Short Packet Header Address"
|
|
hexmask.long 0x4 0.--31. 1. "CFG_SPHDR_ADDRESS,CSI2 Programming : Configure the CSI_PROTOCOL_ENGINE__CSI_VC_SHORT_PACKET_HEADER Address in the CSI Protocol Engine LVDS Programming : Configure with the static value : 0x55555555"
|
|
line.long 0x8 "CFG_CMD_HSVAL,HSYNC Value"
|
|
hexmask.long 0x8 0.--31. 1. "CFG_CMD_HSVAL,CSI2 Programming : Configure the HSync Start Short Packet Value LVDS Programming : If LVDS CRC is enabled : Configure with the static value : 0x55555555 If LVDS CRC is disbaled : Configure with the static value : 0xAAAAAAAA"
|
|
line.long 0xC "CFG_CMD_HEVAL,HEND Value"
|
|
hexmask.long 0xC 0.--31. 1. "CFG_CMD_HEVAL,CSI2 Programming : Configure the HSync End Short Packet Value LVDS Programming : If LVDS CRC is enabled : Configure with the static value : 0x33333333 If LVDS CRC is disbaled : Configure with the static value : 0xAAAAAAAA"
|
|
line.long 0x10 "CFG_CMD_VSVAL,VSYNC Value"
|
|
hexmask.long 0x10 0.--31. 1. "CFG_CMD_VSVAL,CSI2 Programming : Configure the VSync Start Short Packet Value LVDS Programming : Configure with the static value : 0xAAAAAAAA"
|
|
line.long 0x14 "CFG_CMD_VEVAL,VEND Value"
|
|
hexmask.long 0x14 0.--31. 1. "CFG_CMD_VEVAL,CSI2 Programming : Configure the VSync End Short Packet Value LVDS Programming : Configure with the static value : 0xAAAAAAAA"
|
|
line.long 0x18 "CFG_LPHDR_ADDRESS,Long Packet Address"
|
|
hexmask.long 0x18 0.--31. 1. "CFG_LPHDR_ADDRESS,CSI2 Programming : Configure the CSI_PROTOCOL_ENGINE__CSI_VC_LONG_PACKET_HEADER Address in the CSI Protocol Engine LVDS Programming : Configure with the static value : 0x55555555"
|
|
group.long 0x20++0x1CB
|
|
line.long 0x0 "CFG_CHIRPS_PER_FRAME,Number of Chirps per Frame"
|
|
hexmask.long 0x0 0.--31. 1. "CFG_CHIRPS_PER_FRAME,Configure the number of Chirps in a Frame"
|
|
line.long 0x4 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO threshold for transferring data from CBUFF to CSI2"
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hexmask.long.byte 0x4 24.--31. 1. "CFG_FIFO_FREE_THRESHOLD3,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO3 in the CSI Protocol engine. CBUFF will send data to the Protocol Engine only if there is a larger number of Free slots that that.."
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newline
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hexmask.long.byte 0x4 16.--23. 1. "CFG_FIFO_FREE_THRESHOLD2,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO2 in the CSI Protocol engine. CBUFF will send data to the Protocol Engine only if there is a larger number of Free slots that that.."
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newline
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hexmask.long.byte 0x4 8.--15. 1. "CFG_FIFO_FREE_THRESHOLD1,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO1 in the CSI Protocol engine. CBUFF will send data to the Protocol Engine only if there is a larger number of Free slots that that.."
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newline
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hexmask.long.byte 0x4 0.--7. 1. "CFG_FIFO_FREE_THRESHOLD0,CSI2 only Programming : Configure the threshold used to fill the FIFO0 in the CSI Protocol engine. CBUFF will send data to the Protocol Engine only if there is a larger number of Free slots that that configured in this register"
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line.long 0x8 "CFG_LPPYLD_ADDRESS,Long payload Address"
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hexmask.long 0x8 0.--31. 1. "CFG_LPPYLD_ADDRESS,CSI2 only Programming : Configure the CSI_PROTOCOL_ENGINE__CSI_VC_LONG_PACKET_PAYLOAD Address in the CSI Protocol Engine"
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line.long 0xC "CFG_DELAY_CONFIG,Delay Config Registers"
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hexmask.long.byte 0xC 24.--31. 1. "NU,"
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newline
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hexmask.long.byte 0xC 16.--23. 1. "CFG_DATA_WR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Payload. This is a Debug feature. Not requred in Programming model"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "CFG_LPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Header. This is a Debug feature. Not requred in Programming model"
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newline
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hexmask.long.byte 0xC 0.--7. 1. "CFG_SPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Short packet. This is a Debug feature. Not requred in Programming model"
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line.long 0x10 "CFG_DATA_LL0,Payload Description : Linked list entry 0"
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bitfld.long 0x10 31. "LL0_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x10 30. "LL0_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x10 29. "LL0_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x10 28. "LL0_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x10 27. "LL0_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x10 26. "LL0_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x10 23.--25. "LL0_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x10 9.--22. 1. "LL0_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x10 8. "LL0_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x10 7. "LL0_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x10 5.--6. "LL0_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x10 3.--4. "LL0_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x10 2. "LL0_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x10 1. "LL0_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x10 0. "LL0_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x14 "CFG_DATA_LL0_LPHDR_VAL,Payload Description : Linked list entry 0"
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hexmask.long 0x14 0.--31. 1. "LL0_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x18 "CFG_DATA_LL0_THRESHOLD,"
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hexmask.long.word 0x18 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x18 16.--18. "ll0dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x18 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x18 8.--14. 1. "LL0_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x18 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x18 0.--6. 1. "LL0_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x1C "CFG_DATA_LL1,"
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bitfld.long 0x1C 31. "LL1_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x1C 30. "LL1_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x1C 29. "LL1_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x1C 28. "LL1_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x1C 27. "LL1_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x1C 26. "LL1_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x1C 23.--25. "LL1_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x1C 9.--22. 1. "LL1_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x1C 8. "LL1_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x1C 7. "LL1_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x1C 5.--6. "LL1_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x1C 3.--4. "LL1_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x1C 2. "LL1_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x1C 1. "LL1_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x1C 0. "LL1_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x20 "CFG_DATA_LL1_LPHDR_VAL,"
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hexmask.long 0x20 0.--31. 1. "LL1_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x24 "CFG_DATA_LL1_THRESHOLD,"
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hexmask.long.word 0x24 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x24 16.--18. "ll1dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x24 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x24 8.--14. 1. "LL1_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x24 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x24 0.--6. 1. "LL1_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x28 "CFG_DATA_LL2,"
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bitfld.long 0x28 31. "LL2_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x28 30. "LL2_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x28 29. "LL2_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x28 28. "LL2_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x28 27. "LL2_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x28 26. "LL2_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x28 23.--25. "LL2_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x28 9.--22. 1. "LL2_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x28 8. "LL2_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x28 7. "LL2_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x28 5.--6. "LL2_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x28 3.--4. "LL2_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x28 2. "LL2_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x28 1. "LL2_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x28 0. "LL2_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x2C "CFG_DATA_LL2_LPHDR_VAL,"
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hexmask.long 0x2C 0.--31. 1. "LL2_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x30 "CFG_DATA_LL2_THRESHOLD,"
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hexmask.long.word 0x30 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x30 16.--18. "ll2dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x30 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x30 8.--14. 1. "LL2_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x30 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x30 0.--6. 1. "LL2_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x34 "CFG_DATA_LL3,"
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bitfld.long 0x34 31. "LL3_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x34 30. "LL3_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x34 29. "LL3_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x34 28. "LL3_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x34 27. "LL3_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x34 26. "LL3_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x34 23.--25. "LL3_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x34 9.--22. 1. "LL3_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x34 8. "LL3_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x34 7. "LL3_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x34 5.--6. "LL3_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x34 3.--4. "LL3_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x34 2. "LL3_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x34 1. "LL3_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x34 0. "LL3_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x38 "CFG_DATA_LL3_LPHDR_VAL,"
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hexmask.long 0x38 0.--31. 1. "LL3_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x3C "CFG_DATA_LL3_THRESHOLD,"
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hexmask.long.word 0x3C 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x3C 16.--18. "ll3dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x3C 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x3C 8.--14. 1. "LL3_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x3C 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x3C 0.--6. 1. "LL3_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x40 "CFG_DATA_LL4,"
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bitfld.long 0x40 31. "LL4_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x40 30. "LL4_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x40 29. "LL4_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x40 28. "LL4_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x40 27. "LL4_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x40 26. "LL4_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x40 23.--25. "LL4_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x40 9.--22. 1. "LL4_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x40 8. "LL4_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x40 7. "LL4_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x40 5.--6. "LL4_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x40 3.--4. "LL4_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x40 2. "LL4_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x40 1. "LL4_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x40 0. "LL4_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x44 "CFG_DATA_LL4_LPHDR_VAL,"
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hexmask.long 0x44 0.--31. 1. "LL4_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x48 "CFG_DATA_LL4_THRESHOLD,"
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hexmask.long.word 0x48 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x48 16.--18. "ll4dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x48 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x48 8.--14. 1. "LL4_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x48 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x48 0.--6. 1. "LL4_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x4C "CFG_DATA_LL5,"
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bitfld.long 0x4C 31. "LL5_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x4C 30. "LL5_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x4C 29. "LL5_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x4C 28. "LL5_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x4C 27. "LL5_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x4C 26. "LL5_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x4C 23.--25. "LL5_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
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hexmask.long.word 0x4C 9.--22. 1. "LL5_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x4C 8. "LL5_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x4C 7. "LL5_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x4C 5.--6. "LL5_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x4C 3.--4. "LL5_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x4C 2. "LL5_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x4C 1. "LL5_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x4C 0. "LL5_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x50 "CFG_DATA_LL5_LPHDR_VAL,"
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hexmask.long 0x50 0.--31. 1. "LL5_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x54 "CFG_DATA_LL5_THRESHOLD,"
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hexmask.long.word 0x54 19.--31. 1. "NU3,"
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|
newline
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bitfld.long 0x54 16.--18. "ll5dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x54 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x54 8.--14. 1. "LL5_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x54 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x54 0.--6. 1. "LL5_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x58 "CFG_DATA_LL6,"
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bitfld.long 0x58 31. "LL6_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x58 30. "LL6_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x58 29. "LL6_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x58 28. "LL6_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x58 27. "LL6_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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|
newline
|
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bitfld.long 0x58 26. "LL6_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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|
newline
|
|
bitfld.long 0x58 23.--25. "LL6_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
|
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hexmask.long.word 0x58 9.--22. 1. "LL6_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
|
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newline
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bitfld.long 0x58 8. "LL6_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x58 7. "LL6_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x58 5.--6. "LL6_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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|
newline
|
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bitfld.long 0x58 3.--4. "LL6_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
|
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bitfld.long 0x58 2. "LL6_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
|
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bitfld.long 0x58 1. "LL6_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x58 0. "LL6_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x5C "CFG_DATA_LL6_LPHDR_VAL,"
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hexmask.long 0x5C 0.--31. 1. "LL6_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x60 "CFG_DATA_LL6_THRESHOLD,"
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hexmask.long.word 0x60 19.--31. 1. "NU3,"
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|
newline
|
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bitfld.long 0x60 16.--18. "ll6dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
|
|
newline
|
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rbitfld.long 0x60 15. "NU2," "0,1"
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|
newline
|
|
hexmask.long.byte 0x60 8.--14. 1. "LL6_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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|
newline
|
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rbitfld.long 0x60 7. "NU1," "0,1"
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|
newline
|
|
hexmask.long.byte 0x60 0.--6. 1. "LL6_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
|
|
line.long 0x64 "CFG_DATA_LL7,"
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bitfld.long 0x64 31. "LL7_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
|
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bitfld.long 0x64 30. "LL7_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
|
|
bitfld.long 0x64 29. "LL7_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
|
|
newline
|
|
bitfld.long 0x64 28. "LL7_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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|
newline
|
|
bitfld.long 0x64 27. "LL7_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
|
|
newline
|
|
bitfld.long 0x64 26. "LL7_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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|
newline
|
|
bitfld.long 0x64 23.--25. "LL7_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x64 9.--22. 1. "LL7_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
|
|
newline
|
|
bitfld.long 0x64 8. "LL7_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
|
|
newline
|
|
bitfld.long 0x64 7. "LL7_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
|
|
newline
|
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bitfld.long 0x64 5.--6. "LL7_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x64 3.--4. "LL7_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
|
|
newline
|
|
bitfld.long 0x64 2. "LL7_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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|
newline
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bitfld.long 0x64 1. "LL7_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x64 0. "LL7_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x68 "CFG_DATA_LL7_LPHDR_VAL,"
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hexmask.long 0x68 0.--31. 1. "LL7_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x6C "CFG_DATA_LL7_THRESHOLD,"
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hexmask.long.word 0x6C 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x6C 16.--18. "ll7dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x6C 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x6C 8.--14. 1. "LL7_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x6C 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x6C 0.--6. 1. "LL7_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x70 "CFG_DATA_LL8,"
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bitfld.long 0x70 31. "LL8_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x70 30. "LL8_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x70 29. "LL8_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x70 28. "LL8_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x70 27. "LL8_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x70 26. "LL8_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x70 23.--25. "LL8_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x70 9.--22. 1. "LL8_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x70 8. "LL8_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x70 7. "LL8_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x70 5.--6. "LL8_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x70 3.--4. "LL8_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x70 2. "LL8_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x70 1. "LL8_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x70 0. "LL8_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x74 "CFG_DATA_LL8_LPHDR_VAL,"
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hexmask.long 0x74 0.--31. 1. "LL8_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x78 "CFG_DATA_LL8_THRESHOLD,"
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hexmask.long.word 0x78 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x78 16.--18. "ll8dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x78 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x78 8.--14. 1. "LL8_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x78 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x78 0.--6. 1. "LL8_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x7C "CFG_DATA_LL9,"
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bitfld.long 0x7C 31. "LL9_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x7C 30. "LL9_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x7C 29. "LL9_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x7C 28. "LL9_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x7C 27. "LL9_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x7C 26. "LL9_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x7C 23.--25. "LL9_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
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hexmask.long.word 0x7C 9.--22. 1. "LL9_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x7C 8. "LL9_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x7C 7. "LL9_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x7C 5.--6. "LL9_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x7C 3.--4. "LL9_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x7C 2. "LL9_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x7C 1. "LL9_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x7C 0. "LL9_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x80 "CFG_DATA_LL9_LPHDR_VAL,"
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hexmask.long 0x80 0.--31. 1. "LL9_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x84 "CFG_DATA_LL9_THRESHOLD,"
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hexmask.long.word 0x84 19.--31. 1. "NU3,"
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|
newline
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bitfld.long 0x84 16.--18. "ll9dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x84 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x84 8.--14. 1. "LL9_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x84 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x84 0.--6. 1. "LL9_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x88 "CFG_DATA_LL10,"
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bitfld.long 0x88 31. "LL10_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x88 30. "LL10_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x88 29. "LL10_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x88 28. "LL10_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x88 27. "LL10_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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|
newline
|
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bitfld.long 0x88 26. "LL10_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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|
newline
|
|
bitfld.long 0x88 23.--25. "LL10_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
|
|
hexmask.long.word 0x88 9.--22. 1. "LL10_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x88 8. "LL10_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x88 7. "LL10_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x88 5.--6. "LL10_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x88 3.--4. "LL10_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x88 2. "LL10_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x88 1. "LL10_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x88 0. "LL10_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x8C "CFG_DATA_LL10_LPHDR_VAL,"
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hexmask.long 0x8C 0.--31. 1. "LL10_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x90 "CFG_DATA_LL10_THRESHOLD,"
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hexmask.long.word 0x90 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x90 16.--18. "ll10dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
|
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rbitfld.long 0x90 15. "NU2," "0,1"
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|
newline
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hexmask.long.byte 0x90 8.--14. 1. "LL10_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x90 7. "NU1," "0,1"
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|
newline
|
|
hexmask.long.byte 0x90 0.--6. 1. "LL10_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x94 "CFG_DATA_LL11,"
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bitfld.long 0x94 31. "LL11_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
|
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bitfld.long 0x94 30. "LL11_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
|
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bitfld.long 0x94 29. "LL11_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
|
|
newline
|
|
bitfld.long 0x94 28. "LL11_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
|
|
bitfld.long 0x94 27. "LL11_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
|
|
newline
|
|
bitfld.long 0x94 26. "LL11_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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|
newline
|
|
bitfld.long 0x94 23.--25. "LL11_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x94 9.--22. 1. "LL11_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
|
|
newline
|
|
bitfld.long 0x94 8. "LL11_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
|
|
newline
|
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bitfld.long 0x94 7. "LL11_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
|
|
newline
|
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bitfld.long 0x94 5.--6. "LL11_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x94 3.--4. "LL11_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
|
|
newline
|
|
bitfld.long 0x94 2. "LL11_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x94 1. "LL11_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x94 0. "LL11_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x98 "CFG_DATA_LL11_LPHDR_VAL,"
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hexmask.long 0x98 0.--31. 1. "LL11_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x9C "CFG_DATA_LL11_THRESHOLD,"
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hexmask.long.word 0x9C 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x9C 16.--18. "ll11dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x9C 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x9C 8.--14. 1. "LL11_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x9C 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x9C 0.--6. 1. "LL11_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xA0 "CFG_DATA_LL12,"
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bitfld.long 0xA0 31. "LL12_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xA0 30. "LL12_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xA0 29. "LL12_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xA0 28. "LL12_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xA0 27. "LL12_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0xA0 26. "LL12_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0xA0 23.--25. "LL12_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xA0 9.--22. 1. "LL12_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xA0 8. "LL12_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xA0 7. "LL12_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0xA0 5.--6. "LL12_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0xA0 3.--4. "LL12_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0xA0 2. "LL12_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xA0 1. "LL12_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xA0 0. "LL12_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xA4 "CFG_DATA_LL12_LPHDR_VAL,"
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hexmask.long 0xA4 0.--31. 1. "LL12_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xA8 "CFG_DATA_LL12_THRESHOLD,"
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hexmask.long.word 0xA8 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xA8 16.--18. "ll12dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xA8 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xA8 8.--14. 1. "LL12_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xA8 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xA8 0.--6. 1. "LL12_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xAC "CFG_DATA_LL13,"
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bitfld.long 0xAC 31. "LL13_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xAC 30. "LL13_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xAC 29. "LL13_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xAC 28. "LL13_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xAC 27. "LL13_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0xAC 26. "LL13_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0xAC 23.--25. "LL13_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xAC 9.--22. 1. "LL13_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xAC 8. "LL13_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xAC 7. "LL13_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0xAC 5.--6. "LL13_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0xAC 3.--4. "LL13_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0xAC 2. "LL13_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xAC 1. "LL13_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xAC 0. "LL13_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xB0 "CFG_DATA_LL13_LPHDR_VAL,"
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hexmask.long 0xB0 0.--31. 1. "LL13_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xB4 "CFG_DATA_LL13_THRESHOLD,"
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hexmask.long.word 0xB4 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xB4 16.--18. "ll13dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xB4 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xB4 8.--14. 1. "LL13_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xB4 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xB4 0.--6. 1. "LL13_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xB8 "CFG_DATA_LL14,"
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bitfld.long 0xB8 31. "LL14_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xB8 30. "LL14_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xB8 29. "LL14_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xB8 28. "LL14_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xB8 27. "LL14_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0xB8 26. "LL14_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0xB8 23.--25. "LL14_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xB8 9.--22. 1. "LL14_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xB8 8. "LL14_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xB8 7. "LL14_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0xB8 5.--6. "LL14_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0xB8 3.--4. "LL14_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0xB8 2. "LL14_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xB8 1. "LL14_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xB8 0. "LL14_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xBC "CFG_DATA_LL14_LPHDR_VAL,"
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hexmask.long 0xBC 0.--31. 1. "LL14_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xC0 "CFG_DATA_LL14_THRESHOLD,"
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hexmask.long.word 0xC0 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xC0 16.--18. "ll14dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xC0 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xC0 8.--14. 1. "LL14_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xC0 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xC0 0.--6. 1. "LL14_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xC4 "CFG_DATA_LL15,"
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bitfld.long 0xC4 31. "LL15_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xC4 30. "LL15_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xC4 29. "LL15_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xC4 28. "LL15_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xC4 27. "LL15_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
|
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bitfld.long 0xC4 26. "LL15_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
|
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bitfld.long 0xC4 23.--25. "LL15_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
|
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hexmask.long.word 0xC4 9.--22. 1. "LL15_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xC4 8. "LL15_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xC4 7. "LL15_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
|
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bitfld.long 0xC4 5.--6. "LL15_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
|
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bitfld.long 0xC4 3.--4. "LL15_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
|
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bitfld.long 0xC4 2. "LL15_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xC4 1. "LL15_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xC4 0. "LL15_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xC8 "CFG_DATA_LL15_LPHDR_VAL,"
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hexmask.long 0xC8 0.--31. 1. "LL15_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xCC "CFG_DATA_LL15_THRESHOLD,"
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hexmask.long.word 0xCC 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xCC 16.--18. "ll15dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xCC 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xCC 8.--14. 1. "LL15_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xCC 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xCC 0.--6. 1. "LL15_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xD0 "CFG_DATA_LL16,"
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bitfld.long 0xD0 31. "LL16_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xD0 30. "LL16_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xD0 29. "LL16_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xD0 28. "LL16_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xD0 27. "LL16_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0xD0 26. "LL16_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0xD0 23.--25. "LL16_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xD0 9.--22. 1. "LL16_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xD0 8. "LL16_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xD0 7. "LL16_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0xD0 5.--6. "LL16_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0xD0 3.--4. "LL16_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0xD0 2. "LL16_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xD0 1. "LL16_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xD0 0. "LL16_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xD4 "CFG_DATA_LL16_LPHDR_VAL,"
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hexmask.long 0xD4 0.--31. 1. "LL16_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xD8 "CFG_DATA_LL16_THRESHOLD,"
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hexmask.long.word 0xD8 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xD8 16.--18. "ll16dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xD8 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xD8 8.--14. 1. "LL16_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xD8 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xD8 0.--6. 1. "LL16_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xDC "CFG_DATA_LL17,"
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bitfld.long 0xDC 31. "LL17_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xDC 30. "LL17_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xDC 29. "LL17_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xDC 28. "LL17_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xDC 27. "LL17_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0xDC 26. "LL17_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0xDC 23.--25. "LL17_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xDC 9.--22. 1. "LL17_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xDC 8. "LL17_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xDC 7. "LL17_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0xDC 5.--6. "LL17_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0xDC 3.--4. "LL17_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0xDC 2. "LL17_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xDC 1. "LL17_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xDC 0. "LL17_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xE0 "CFG_DATA_LL17_LPHDR_VAL,"
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hexmask.long 0xE0 0.--31. 1. "LL17_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xE4 "CFG_DATA_LL17_THRESHOLD,"
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hexmask.long.word 0xE4 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xE4 16.--18. "ll17dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xE4 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xE4 8.--14. 1. "LL17_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xE4 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xE4 0.--6. 1. "LL17_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xE8 "CFG_DATA_LL18,"
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bitfld.long 0xE8 31. "LL18_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xE8 30. "LL18_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xE8 29. "LL18_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xE8 28. "LL18_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xE8 27. "LL18_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0xE8 26. "LL18_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0xE8 23.--25. "LL18_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xE8 9.--22. 1. "LL18_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xE8 8. "LL18_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xE8 7. "LL18_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0xE8 5.--6. "LL18_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0xE8 3.--4. "LL18_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0xE8 2. "LL18_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xE8 1. "LL18_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xE8 0. "LL18_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xEC "CFG_DATA_LL18_LPHDR_VAL,"
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hexmask.long 0xEC 0.--31. 1. "LL18_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xF0 "CFG_DATA_LL18_THRESHOLD,"
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hexmask.long.word 0xF0 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xF0 16.--18. "ll18dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xF0 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xF0 8.--14. 1. "LL18_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xF0 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xF0 0.--6. 1. "LL18_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0xF4 "CFG_DATA_LL19,"
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bitfld.long 0xF4 31. "LL19_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xF4 30. "LL19_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xF4 29. "LL19_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0xF4 28. "LL19_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0xF4 27. "LL19_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0xF4 26. "LL19_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0xF4 23.--25. "LL19_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xF4 9.--22. 1. "LL19_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0xF4 8. "LL19_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0xF4 7. "LL19_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0xF4 5.--6. "LL19_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0xF4 3.--4. "LL19_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0xF4 2. "LL19_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0xF4 1. "LL19_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0xF4 0. "LL19_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0xF8 "CFG_DATA_LL19_LPHDR_VAL,"
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hexmask.long 0xF8 0.--31. 1. "LL19_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0xFC "CFG_DATA_LL19_THRESHOLD,"
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hexmask.long.word 0xFC 19.--31. 1. "NU3,"
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newline
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bitfld.long 0xFC 16.--18. "ll19dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0xFC 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0xFC 8.--14. 1. "LL19_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0xFC 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0xFC 0.--6. 1. "LL19_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x100 "CFG_DATA_LL20,"
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bitfld.long 0x100 31. "LL20_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x100 30. "LL20_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x100 29. "LL20_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x100 28. "LL20_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x100 27. "LL20_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x100 26. "LL20_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x100 23.--25. "LL20_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x100 9.--22. 1. "LL20_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x100 8. "LL20_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x100 7. "LL20_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x100 5.--6. "LL20_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x100 3.--4. "LL20_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x100 2. "LL20_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x100 1. "LL20_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x100 0. "LL20_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x104 "CFG_DATA_LL20_LPHDR_VAL,"
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hexmask.long 0x104 0.--31. 1. "LL20_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x108 "CFG_DATA_LL20_THRESHOLD,"
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hexmask.long.word 0x108 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x108 16.--18. "ll20dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x108 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x108 8.--14. 1. "LL20_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x108 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x108 0.--6. 1. "LL20_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x10C "CFG_DATA_LL21,"
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bitfld.long 0x10C 31. "LL21_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x10C 30. "LL21_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x10C 29. "LL21_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x10C 28. "LL21_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x10C 27. "LL21_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x10C 26. "LL21_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x10C 23.--25. "LL21_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x10C 9.--22. 1. "LL21_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x10C 8. "LL21_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x10C 7. "LL21_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x10C 5.--6. "LL21_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x10C 3.--4. "LL21_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x10C 2. "LL21_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x10C 1. "LL21_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x10C 0. "LL21_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x110 "CFG_DATA_LL21_LPHDR_VAL,"
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hexmask.long 0x110 0.--31. 1. "LL21_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x114 "CFG_DATA_LL21_THRESHOLD,"
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hexmask.long.word 0x114 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x114 16.--18. "ll21dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x114 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x114 8.--14. 1. "LL21_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x114 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x114 0.--6. 1. "LL21_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x118 "CFG_DATA_LL22,"
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bitfld.long 0x118 31. "LL22_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x118 30. "LL22_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x118 29. "LL22_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x118 28. "LL22_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x118 27. "LL22_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x118 26. "LL22_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x118 23.--25. "LL22_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x118 9.--22. 1. "LL22_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x118 8. "LL22_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x118 7. "LL22_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x118 5.--6. "LL22_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x118 3.--4. "LL22_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x118 2. "LL22_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x118 1. "LL22_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x118 0. "LL22_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x11C "CFG_DATA_LL22_LPHDR_VAL,"
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hexmask.long 0x11C 0.--31. 1. "LL22_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x120 "CFG_DATA_LL22_THRESHOLD,"
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hexmask.long.word 0x120 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x120 16.--18. "ll22dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x120 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x120 8.--14. 1. "LL22_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x120 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x120 0.--6. 1. "LL22_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x124 "CFG_DATA_LL23,"
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bitfld.long 0x124 31. "LL23_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x124 30. "LL23_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x124 29. "LL23_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x124 28. "LL23_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x124 27. "LL23_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
|
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bitfld.long 0x124 26. "LL23_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x124 23.--25. "LL23_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.word 0x124 9.--22. 1. "LL23_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x124 8. "LL23_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x124 7. "LL23_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x124 5.--6. "LL23_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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|
newline
|
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bitfld.long 0x124 3.--4. "LL23_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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|
newline
|
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bitfld.long 0x124 2. "LL23_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x124 1. "LL23_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x124 0. "LL23_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x128 "CFG_DATA_LL23_LPHDR_VAL,"
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hexmask.long 0x128 0.--31. 1. "LL23_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x12C "CFG_DATA_LL23_THRESHOLD,"
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hexmask.long.word 0x12C 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x12C 16.--18. "ll23dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x12C 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x12C 8.--14. 1. "LL23_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x12C 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x12C 0.--6. 1. "LL23_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x130 "CFG_DATA_LL24,"
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bitfld.long 0x130 31. "LL24_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x130 30. "LL24_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x130 29. "LL24_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x130 28. "LL24_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x130 27. "LL24_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x130 26. "LL24_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x130 23.--25. "LL24_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x130 9.--22. 1. "LL24_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x130 8. "LL24_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x130 7. "LL24_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x130 5.--6. "LL24_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x130 3.--4. "LL24_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x130 2. "LL24_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x130 1. "LL24_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x130 0. "LL24_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x134 "CFG_DATA_LL24_LPHDR_VAL,"
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hexmask.long 0x134 0.--31. 1. "LL24_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x138 "CFG_DATA_LL24_THRESHOLD,"
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hexmask.long.word 0x138 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x138 16.--18. "ll24dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x138 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x138 8.--14. 1. "LL24_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x138 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x138 0.--6. 1. "LL24_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x13C "CFG_DATA_LL25,"
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bitfld.long 0x13C 31. "LL25_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x13C 30. "LL25_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x13C 29. "LL25_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x13C 28. "LL25_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x13C 27. "LL25_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x13C 26. "LL25_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x13C 23.--25. "LL25_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
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hexmask.long.word 0x13C 9.--22. 1. "LL25_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x13C 8. "LL25_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x13C 7. "LL25_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x13C 5.--6. "LL25_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x13C 3.--4. "LL25_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x13C 2. "LL25_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x13C 1. "LL25_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x13C 0. "LL25_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x140 "CFG_DATA_LL25_LPHDR_VAL,"
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hexmask.long 0x140 0.--31. 1. "LL25_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x144 "CFG_DATA_LL25_THRESHOLD,"
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hexmask.long.word 0x144 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x144 16.--18. "ll25dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x144 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x144 8.--14. 1. "LL25_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x144 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x144 0.--6. 1. "LL25_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x148 "CFG_DATA_LL26,"
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bitfld.long 0x148 31. "LL26_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x148 30. "LL26_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x148 29. "LL26_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x148 28. "LL26_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x148 27. "LL26_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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|
newline
|
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bitfld.long 0x148 26. "LL26_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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|
newline
|
|
bitfld.long 0x148 23.--25. "LL26_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
|
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hexmask.long.word 0x148 9.--22. 1. "LL26_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x148 8. "LL26_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x148 7. "LL26_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x148 5.--6. "LL26_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x148 3.--4. "LL26_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x148 2. "LL26_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x148 1. "LL26_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x148 0. "LL26_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x14C "CFG_DATA_LL26_LPHDR_VAL,"
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hexmask.long 0x14C 0.--31. 1. "LL26_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x150 "CFG_DATA_LL26_THRESHOLD,"
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hexmask.long.word 0x150 19.--31. 1. "NU3,"
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newline
|
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bitfld.long 0x150 16.--18. "ll26dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
|
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rbitfld.long 0x150 15. "NU2," "0,1"
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|
newline
|
|
hexmask.long.byte 0x150 8.--14. 1. "LL26_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
|
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rbitfld.long 0x150 7. "NU1," "0,1"
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|
newline
|
|
hexmask.long.byte 0x150 0.--6. 1. "LL26_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x154 "CFG_DATA_LL27,"
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bitfld.long 0x154 31. "LL27_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
|
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bitfld.long 0x154 30. "LL27_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
|
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bitfld.long 0x154 29. "LL27_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
|
|
newline
|
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bitfld.long 0x154 28. "LL27_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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|
newline
|
|
bitfld.long 0x154 27. "LL27_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
|
|
newline
|
|
bitfld.long 0x154 26. "LL27_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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|
newline
|
|
bitfld.long 0x154 23.--25. "LL27_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
|
|
hexmask.long.word 0x154 9.--22. 1. "LL27_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
|
|
newline
|
|
bitfld.long 0x154 8. "LL27_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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|
newline
|
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bitfld.long 0x154 7. "LL27_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
|
|
newline
|
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bitfld.long 0x154 5.--6. "LL27_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x154 3.--4. "LL27_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
|
|
newline
|
|
bitfld.long 0x154 2. "LL27_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x154 1. "LL27_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x154 0. "LL27_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x158 "CFG_DATA_LL27_LPHDR_VAL,"
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hexmask.long 0x158 0.--31. 1. "LL27_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x15C "CFG_DATA_LL27_THRESHOLD,"
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hexmask.long.word 0x15C 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x15C 16.--18. "ll27dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x15C 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x15C 8.--14. 1. "LL27_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x15C 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x15C 0.--6. 1. "LL27_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x160 "CFG_DATA_LL28,"
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bitfld.long 0x160 31. "LL28_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x160 30. "LL28_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x160 29. "LL28_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x160 28. "LL28_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x160 27. "LL28_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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newline
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bitfld.long 0x160 26. "LL28_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x160 23.--25. "LL28_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x160 9.--22. 1. "LL28_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x160 8. "LL28_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x160 7. "LL28_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x160 5.--6. "LL28_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x160 3.--4. "LL28_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x160 2. "LL28_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x160 1. "LL28_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x160 0. "LL28_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x164 "CFG_DATA_LL28_LPHDR_VAL,"
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hexmask.long 0x164 0.--31. 1. "LL28_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x168 "CFG_DATA_LL28_THRESHOLD,"
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hexmask.long.word 0x168 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x168 16.--18. "ll28dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x168 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x168 8.--14. 1. "LL28_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x168 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x168 0.--6. 1. "LL28_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x16C "CFG_DATA_LL29,"
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bitfld.long 0x16C 31. "LL29_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x16C 30. "LL29_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x16C 29. "LL29_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x16C 28. "LL29_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
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bitfld.long 0x16C 27. "LL29_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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|
newline
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bitfld.long 0x16C 26. "LL29_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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newline
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bitfld.long 0x16C 23.--25. "LL29_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
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hexmask.long.word 0x16C 9.--22. 1. "LL29_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
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newline
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bitfld.long 0x16C 8. "LL29_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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newline
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bitfld.long 0x16C 7. "LL29_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
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bitfld.long 0x16C 5.--6. "LL29_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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newline
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bitfld.long 0x16C 3.--4. "LL29_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
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bitfld.long 0x16C 2. "LL29_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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newline
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bitfld.long 0x16C 1. "LL29_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x16C 0. "LL29_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x170 "CFG_DATA_LL29_LPHDR_VAL,"
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hexmask.long 0x170 0.--31. 1. "LL29_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x174 "CFG_DATA_LL29_THRESHOLD,"
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hexmask.long.word 0x174 19.--31. 1. "NU3,"
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newline
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bitfld.long 0x174 16.--18. "ll29dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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newline
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rbitfld.long 0x174 15. "NU2," "0,1"
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newline
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hexmask.long.byte 0x174 8.--14. 1. "LL29_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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newline
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rbitfld.long 0x174 7. "NU1," "0,1"
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newline
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hexmask.long.byte 0x174 0.--6. 1. "LL29_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x178 "CFG_DATA_LL30,"
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bitfld.long 0x178 31. "LL30_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x178 30. "LL30_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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newline
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bitfld.long 0x178 29. "LL30_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
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bitfld.long 0x178 28. "LL30_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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newline
|
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bitfld.long 0x178 27. "LL30_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
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|
newline
|
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bitfld.long 0x178 26. "LL30_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
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|
newline
|
|
bitfld.long 0x178 23.--25. "LL30_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
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|
newline
|
|
hexmask.long.word 0x178 9.--22. 1. "LL30_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
|
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newline
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bitfld.long 0x178 8. "LL30_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
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|
newline
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bitfld.long 0x178 7. "LL30_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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newline
|
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bitfld.long 0x178 5.--6. "LL30_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
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|
newline
|
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bitfld.long 0x178 3.--4. "LL30_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
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newline
|
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bitfld.long 0x178 2. "LL30_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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|
newline
|
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bitfld.long 0x178 1. "LL30_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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newline
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bitfld.long 0x178 0. "LL30_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x17C "CFG_DATA_LL30_LPHDR_VAL,"
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hexmask.long 0x17C 0.--31. 1. "LL30_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x180 "CFG_DATA_LL30_THRESHOLD,"
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hexmask.long.word 0x180 19.--31. 1. "NU3,"
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newline
|
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bitfld.long 0x180 16.--18. "ll30dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
|
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newline
|
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rbitfld.long 0x180 15. "NU2," "0,1"
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|
newline
|
|
hexmask.long.byte 0x180 8.--14. 1. "LL30_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
|
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newline
|
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rbitfld.long 0x180 7. "NU1," "0,1"
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|
newline
|
|
hexmask.long.byte 0x180 0.--6. 1. "LL30_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x184 "CFG_DATA_LL31,"
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bitfld.long 0x184 31. "LL31_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
|
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bitfld.long 0x184 30. "LL31_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
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|
newline
|
|
bitfld.long 0x184 29. "LL31_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG. This is a Debug feature. Not requred in Programming model" "0,1"
|
|
newline
|
|
bitfld.long 0x184 28. "LL31_CRC_EN,0 : CRC is disbaled 1 : This linklist corresponds to ADC Buffer data. Enable the CRC check from ADC Buffer to CBUFF" "0: CRC is disbaled,1: This linklist corresponds to ADC Buffer data"
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|
newline
|
|
bitfld.long 0x184 27. "LL31_LPHDR_EN,CSI2 Programming : 1 : Entry is start of a new CSI-2 packet. Send the LP Payload Header before sending data corresponind to this Linklist 0 : Link list is not the start of a Long packet but part of previous packet and hence directly send.." "0: Entry is not the start of the new LVDS Frame,1: Entry is start of a new LVDS Frame"
|
|
newline
|
|
bitfld.long 0x184 26. "LL31_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement 1 : Wait for packet sent signal ack from CSI2 to move forward 0 : Do not wait for packet sent" "0: Do not wait for packet sent,1: Wait for packet sent signal ack from CSI2 to.."
|
|
newline
|
|
bitfld.long 0x184 23.--25. "LL31_BITPOS_SEL,TI Internal Feature. Reserved for future use to select which of the 12-bits or 14-bits to be picked up from 16-bit CBUFF unit" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x184 9.--22. 1. "LL31_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes). Sample refers to a 16 bit CBUFF Unit"
|
|
newline
|
|
bitfld.long 0x184 8. "LL31_FMT_IN,0 : The incoming data sources for this Linklist is aligned to 128-bit 1 : The incoming data sources for this Linklist is aligned to 96-bit" "0: The incoming data sources for this Linklist is..,1: The incoming data sources for this Linklist is.."
|
|
newline
|
|
bitfld.long 0x184 7. "LL31_FMT_MAP,LVDS only : 0 : Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y 1 : Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y" "0: Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,1: Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
|
|
newline
|
|
bitfld.long 0x184 5.--6. "LL31_FMT,Specify the LVDS/CSI2 output format. 00 - 16bit 01 - 14-bit 10 - 12-bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x184 3.--4. "LL31_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "?,?,2: Configure the Virtual Channel Number for the..,?"
|
|
newline
|
|
bitfld.long 0x184 2. "LL31_HS,CSI-2 : 0 : Do not send an Hsync Start packet before sending this data 1 : Send an Hsync Start Packet before sending this data LVDS : 0 : Entry is not the first data of LVDS Frame 1 : Entry is the first data in the LVDS Frame" "0: Entry is not the first data of LVDS Frame,1: Entry is the first data in the LVDS Frame"
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|
newline
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bitfld.long 0x184 1. "LL31_HE,CSI-2 : 0 : Do not send an Hsync End packet after sending this data 1 : Send an Hsync End Packet after sending this data LVDS : 0 : Entry is not the last data of LVDS Frame 1 : Entry is the last data in the LVDS Frame" "0: Entry is not the last data of LVDS Frame,1: Entry is the last data in the LVDS Frame"
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bitfld.long 0x184 0. "LL31_VALID,0 : Linklist entry is invalid 1 : Linklist entry is valid" "0: Linklist entry is invalid,1: Linklist entry is valid"
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line.long 0x188 "CFG_DATA_LL31_LPHDR_VAL,"
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hexmask.long 0x188 0.--31. 1. "LL31_LPHDR_VAL,CSI-2 Programming : Configure the Long Packet Header to be sent to the Protocol Engine if the LPHDR_EN field is set for the linklist. LVDS Programming : Configure with the static value : 0xBBBBBBBB"
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line.long 0x18C "CFG_DATA_LL31_THRESHOLD,"
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hexmask.long.word 0x18C 19.--31. 1. "NU3,"
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bitfld.long 0x18C 16.--18. "ll31dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet 0 : Send a Request on DMA HW Req output line 0 1 : Send a Request on DMA HW Req output line 1 2 : Send a Request on DMA HW Req.." "0: Send a Request on DMA HW Req output line 0,1: Send a Request on DMA HW Req output line 1,2: Send a Request on DMA HW Req output line 2,3: Send a Request on DMA HW Req output line 3,4: Send a Request on DMA HW Req output line 4,5: Send a Request on DMA HW Req output line 5,6: Send a Request on DMA HW Req output line 6,7: Do not generate dma trigger"
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rbitfld.long 0x18C 15. "NU2," "0,1"
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hexmask.long.byte 0x18C 8.--14. 1. "LL31_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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rbitfld.long 0x18C 7. "NU1," "0,1"
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hexmask.long.byte 0x18C 0.--6. 1. "LL31_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO. Static configuration. This can be programmed to fixed value mentioned in the Programming Model"
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line.long 0x190 "CFG_LVDS_MAPPING_LANE0_FMT_0,"
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hexmask.long.byte 0x190 28.--31. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_H,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x190 24.--27. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_G,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x190 20.--23. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_F,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x190 16.--19. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_E,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x190 12.--15. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_D,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x190 8.--11. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_C,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x190 4.--7. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_B,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x190 0.--3. 1. "CFG_LVDS_MAPPING_LANE0_FMT_0_A,Lane 0 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 0 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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line.long 0x194 "CFG_LVDS_MAPPING_LANE1_FMT_0,"
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hexmask.long.byte 0x194 28.--31. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_H,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x194 24.--27. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_G,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x194 20.--23. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_F,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x194 16.--19. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_E,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x194 12.--15. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_D,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x194 8.--11. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_C,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x194 4.--7. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_B,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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hexmask.long.byte 0x194 0.--3. 1. "CFG_LVDS_MAPPING_LANE1_FMT_0_A,Lane 1 mapping if Format 0 is selected. Bit [2:0] : 0-7 : Selects the CBUFF unit from the 8 CBUFF units to be sent on Lane 1 Bit 3 0 : Entry is not valid 1 : Entry is valid Please refer to LVDS Mapping Format in.."
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line.long 0x198 "CFG_LVDS_MAPPING_LANE2_FMT_0,"
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hexmask.long.byte 0x198 28.--31. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x198 24.--27. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x198 20.--23. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x198 16.--19. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x198 12.--15. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x198 8.--11. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x198 4.--7. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x198 0.--3. 1. "CFG_LVDS_MAPPING_LANE2_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details"
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line.long 0x19C "CFG_LVDS_MAPPING_LANE3_FMT_0,"
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hexmask.long.byte 0x19C 28.--31. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x19C 24.--27. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x19C 20.--23. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x19C 16.--19. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x19C 12.--15. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x19C 8.--11. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x19C 4.--7. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x19C 0.--3. 1. "CFG_LVDS_MAPPING_LANE3_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details"
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line.long 0x1A0 "CFG_LVDS_MAPPING_LANE0_FMT_1,"
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hexmask.long.byte 0x1A0 28.--31. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A0 24.--27. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A0 20.--23. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details"
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newline
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hexmask.long.byte 0x1A0 16.--19. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A0 12.--15. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A0 8.--11. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A0 4.--7. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details"
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newline
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hexmask.long.byte 0x1A0 0.--3. 1. "CFG_LVDS_MAPPING_LANE0_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details"
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line.long 0x1A4 "CFG_LVDS_MAPPING_LANE1_FMT_1,"
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hexmask.long.byte 0x1A4 28.--31. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A4 24.--27. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A4 20.--23. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A4 16.--19. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A4 12.--15. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A4 8.--11. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A4 4.--7. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A4 0.--3. 1. "CFG_LVDS_MAPPING_LANE1_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details"
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line.long 0x1A8 "CFG_LVDS_MAPPING_LANE2_FMT_1,"
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hexmask.long.byte 0x1A8 28.--31. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A8 24.--27. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A8 20.--23. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A8 16.--19. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A8 12.--15. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A8 8.--11. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A8 4.--7. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1A8 0.--3. 1. "CFG_LVDS_MAPPING_LANE2_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details"
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line.long 0x1AC "CFG_LVDS_MAPPING_LANE3_FMT_1,"
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hexmask.long.byte 0x1AC 28.--31. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1AC 24.--27. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1AC 20.--23. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details"
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newline
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hexmask.long.byte 0x1AC 16.--19. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details"
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newline
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hexmask.long.byte 0x1AC 12.--15. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details"
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newline
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hexmask.long.byte 0x1AC 8.--11. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details"
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newline
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hexmask.long.byte 0x1AC 4.--7. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details"
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hexmask.long.byte 0x1AC 0.--3. 1. "CFG_LVDS_MAPPING_LANE3_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details"
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line.long 0x1B0 "CFG_LVDS_GEN_0,"
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bitfld.long 0x1B0 30.--31. "cpz,LVDS Clock config. 1 : Clock alignment enabled Others : Internal clock alignment not enabled This needs to be set to 0x1 for correct functionality" "?,1: Clock alignment enabled Others : Internal clock..,?,?"
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bitfld.long 0x1B0 29. "cblpen,TI Internal CFG_LASTPULSE_EN" "0,1"
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bitfld.long 0x1B0 28. "cbcrcen,LVDS Frame CRC 0 : CRC is not sent at the end of LVDS Frame 1 : CRC is sent at the end of the LVDS Frame" "0: CRC is not sent at the end of LVDS Frame,1: CRC is sent at the end of the LVDS Frame"
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hexmask.long.byte 0x1B0 24.--27. 1. "cfdly,LVDS FIFO Initial Threshold. This is a Static configuration and sould be set to a fixed value as mention in the Programming model"
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bitfld.long 0x1B0 23. "cmsbf,1 : Data is sent out on the LVDS lane MSB first 0 : Data is sent out on the LVDS lane LSB first" "0: Data is sent out on the LVDS lane LSB first,1: Data is sent out on the LVDS lane MSB first"
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bitfld.long 0x1B0 22. "cpossel,0 : When a new chirp is starting align first sample start to negedge of DDR clock. 1 : When a new chirp is starting align first sample start to posedge of DDR clock (recommended)" "0: When a new chirp is starting,1: When a new chirp is starting"
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hexmask.long.byte 0x1B0 16.--21. 1. "cckdiv,TI Internal feature. CFG_LVDS_CLK_DIV"
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bitfld.long 0x1B0 15. "cclksel1,TRM Description : 0 : DDR mode clock mux 1 : SDR mode clock mux TI Restricted Description : CFG_LVDS_CLK_SEL1 0-> Use div-by-2 (Q2 path ) 1 -> Used for direct (Q1 path)" "0: DDR mode clock mux,1: Used for direct"
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bitfld.long 0x1B0 14. "cclksel,TI Internal feature. CFG_LVDS_CLK_SEL (between div-by-N and CLK_HSI_DIG) 1 -> CLK_HSI_DIG; 0 - through div-by-N (N is programmed in CFG_LVDS_CLK_DIV)" "?,1: CLK_HSI_DIG; 0"
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bitfld.long 0x1B0 12.--13. "ckchar,TI Internal feature. CFG_K_CHAR_SEL" "0,1,2,3"
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bitfld.long 0x1B0 11. "ccsmen,TRM Description : As per alignment TI Restricted Description : 0 : Regular operation 1 : Continuous Streaming Mode Enabled (Not supported internally also in AR16xx)" "0: Regular operation,1: Continuous Streaming Mode Enabled"
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bitfld.long 0x1B0 10. "CFG_BIT_CLK_MODE,Bit Clock Mode 0 : SDR clocking mode 1 : DDR clocking mode" "0: SDR clocking mode,1: DDR clocking mode"
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bitfld.long 0x1B0 8.--9. "CFG_LINE_MODE,TI Internal feature. Reserved." "0,1,2,3"
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bitfld.long 0x1B0 7. "cpkfmt,TI Internal feature. CFG_PACK_FORMAT: While packing in 12/14 bit whether to use CSI like packing or general packing." "0,1"
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bitfld.long 0x1B0 6. "cacdsel,TI Internal feature. CFG_ALL_CHL_READY_DELAY_SEL This bit is added to take of the fast to slow transition in the ADC Buffer. 0 => If the LVDS clock frequency (SDR) is >= 200MHz 1 => If the LVDS clock frequency (SDR) is < 200MHz" "0: If the LVDS clock frequency,1: If the LVDS clock frequency"
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bitfld.long 0x1B0 5. "ctc2en,TI Internal feature. 0 : Regular operation 1: TC2MODE Enable (Not supported internally also in AR16xx)" "0: Regular operation,1: TC2MODE Enable"
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bitfld.long 0x1B0 4. "CFG_8B10B_EN,TI Internal Feature. Reserved. For Furture enhancement. Not supported in this version 0 : No encoding 1: 8B10B encoding" "0: No encoding 1: 8B10B encoding,?"
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bitfld.long 0x1B0 3. "CFG_LVDS_LANE3_EN,LVDS only programming : 0 : LVDS Lane 3 is disbaled 1 : LVDS Lane 3 is enabled" "0: LVDS Lane 3 is disbaled,1: LVDS Lane 3 is enabled"
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bitfld.long 0x1B0 2. "CFG_LVDS_LANE2_EN,LVDS only programming : 0 : LVDS Lane 2 is disbaled 1 : LVDS Lane 2 is enabled" "0: LVDS Lane 2 is disbaled,1: LVDS Lane 2 is enabled"
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bitfld.long 0x1B0 1. "CFG_LVDS_LANE1_EN,LVDS only programming : 0 : LVDS Lane 1 is disbaled 1 : LVDS Lane 1 is enabled" "0: LVDS Lane 1 is disbaled,1: LVDS Lane 1 is enabled"
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bitfld.long 0x1B0 0. "CFG_LVDS_LANE0_EN,LVDS only programming : 0 : LVDS Lane 0 is disbaled 1 : LVDS Lane 0 is enabled" "0: LVDS Lane 0 is disbaled,1: LVDS Lane 0 is enabled"
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line.long 0x1B4 "CFG_LVDS_GEN_1,"
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hexmask.long.word 0x1B4 19.--31. 1. "NU2,RESERVED"
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bitfld.long 0x1B4 18. "cgbcen,TI Internal Feature. 0 : Bit clk is free running 1 : Bit clk is valid only during the valid frame." "0: Bit clk is free running,1: Bit clk is valid only during the valid frame"
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bitfld.long 0x1B4 17. "cfcpol,TI Internal Feature. 0 : During IDLE Frame clock will be 0. Start of the valid sample is indicated by the rise edge 1 : During IDLE. Frame clock will be 1. Start of the valid sample is indicated by the fall edge." "0: During IDLE,1: During IDLE"
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bitfld.long 0x1B4 16. "clfven,TI Internal feature. Extend the Single Ended Frame Valid When the frame_valid is used as a single ended signal then make this 1. 0 : Regular Operation. Frame Valid will exactly match with the valid data. 1 : The frame_valid would start early by.." "0: Regular Operation,1: The frame_valid would start early by about 10.."
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newline
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bitfld.long 0x1B4 14.--15. "ctpsel3,TI Internal feature. This is used when Test Pattern Generation Enabled is enabled. 0 :Incremental pattern - For Lane 3" "0: Incremental pattern,?,?,?"
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newline
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bitfld.long 0x1B4 12.--13. "ctpsel2,TI Internal feature. This is used when Test Pattern Generation Enabled is enabled. 0 :Incremental pattern - For Lane 2" "0: Incremental pattern,?,?,?"
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newline
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bitfld.long 0x1B4 10.--11. "ctpsel1,TI Internal feature. This is used when Test Pattern Generation Enabled is enabled. 0 :Incremental pattern - For Lane 1" "0: Incremental pattern,?,?,?"
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newline
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bitfld.long 0x1B4 8.--9. "ctpsel0,TI Internal feature. This is used when Test Pattern Generation Enabled is enabled. 0 :Incremental pattern - For Lane 0" "0: Incremental pattern,?,?,?"
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newline
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rbitfld.long 0x1B4 7. "NU1,RESERVED" "0,1"
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newline
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bitfld.long 0x1B4 4.--6. "ctiddly,TI Internal feature. Configure the skew delay in terms on number of cycles" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x1B4 3. "NU3," "0,1"
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newline
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bitfld.long 0x1B4 2. "c3c3l,LVDS Only Programming: 0 : Regular Operation 1 : Enable 3Ch-3Lane mode in LVDS. Refer to Programming model for more details" "0: Regular Operation,1: Enable 3Ch-3Lane mode in LVDS"
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newline
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bitfld.long 0x1B4 1. "csdrinv,TI Internal feature. Configure the clock inversion during SDR mode. 0 : No inversion 1 : Inversion" "0: No inversion,1: Inversion"
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newline
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bitfld.long 0x1B4 0. "ctpen,TI Internal feature. 0 : Regular Operation 1 : LVDS Testpattern Enable" "0: Regular Operation,1: LVDS Testpattern Enable"
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line.long 0x1B8 "CFG_LVDS_GEN_2,"
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hexmask.long 0x1B8 0.--31. 1. "CFG_LVDS_GEN_2,CFG_LVDS_GEN_2[0]: Configure LSB/MSB first for CRC. This feature is supported only when the field CFG_LVDS_GEN_0[28] is set to 1 0 -> The calculated value of 32-bit Ethernet polynomial CRC is swapped and sent out clear this bit if data is.."
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line.long 0x1BC "CFG_MASK_REG0,"
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hexmask.long 0x1BC 0.--31. 1. "CFG_MASK_REG0,Mask Register field corresponding to STAT_CBUFF_REG0. Refer STAT_CBUFF_REG0 for bitwise mapping. 0 : Event is unmasked and will cause an interrupt on occuruence 1 : Event is masked. No interrupt will be generated on occurrence"
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line.long 0x1C0 "CFG_MASK_REG1,"
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hexmask.long 0x1C0 0.--31. 1. "CFG_MASK_REG1,Mask Register field corresponding to STAT_CBUFF_REG1. Refer STAT_CBUFF_REG1 for bitwise mapping. 0 : Event is unmasked and will cause an interrupt on occuruence 1 : Event is masked. No interrupt will be generated on occurrence"
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line.long 0x1C4 "CFG_MASK_REG2,"
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hexmask.long 0x1C4 0.--31. 1. "CFG_MASK_REG2,Mask Register field corresponding to STAT_LVDS_REG0. Refer STAT_LVDS_REG0 for bitwise mapping. 0 : Event is unmasked and will cause an interrupt on occuruence 1 : Event is masked. No interrupt will be generated on occurrence"
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line.long 0x1C8 "CFG_MASK_REG3,"
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hexmask.long 0x1C8 0.--31. 1. "CFG_MASK_REG3,RESERVED"
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rgroup.long 0x1EC++0x7
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line.long 0x0 "STAT_CBUFF_REG0,"
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hexmask.long.tbyte 0x0 13.--31. 1. "STAT_CBUFF_REG0_OTHERS,Reseved for future enhancement"
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newline
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bitfld.long 0x0 12. "S_FRAME_DONE,Indicates that CBUFF has completed sending out data for the current Frame" "0,1"
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newline
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bitfld.long 0x0 11. "S_CHIRP_DONE,Indicates that CBUFF has completed sending out data for the current Chirp" "0,1"
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newline
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hexmask.long.byte 0x0 6.--10. 1. "S_LL_INDEX,TI Internal Feature. Debug only. Current Linked list index."
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newline
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bitfld.long 0x0 5. "S_CSI_PKT_LP_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Long Data Packet" "0,1"
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newline
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bitfld.long 0x0 4. "S_CSI_PKT_HE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync End Packet" "0,1"
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newline
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bitfld.long 0x0 3. "S_CSI_PKT_HS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync Start Packet" "0,1"
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newline
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bitfld.long 0x0 2. "S_CSI_PKT_VE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync End Packet" "0,1"
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newline
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bitfld.long 0x0 1. "S_CSI_PKT_VS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync Start Packet" "0,1"
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newline
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bitfld.long 0x0 0. "S_CSI_PKT_RCVD,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine" "0,1"
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line.long 0x4 "STAT_CBUFF_REG1,"
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hexmask.long.word 0x4 21.--31. 1. "S1_UNUSED3,"
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newline
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bitfld.long 0x4 20. "S_CBFIFO_READY_IN_FSM,TI Internal Feature. Debug only. cbuff-fifo_ready - Keep this masked. Not relevant." "0,1"
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newline
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bitfld.long 0x4 19. "S_CBFIFO_EMPTY_IN_FSM,TI Internal Feature. Debug only. cbuff-fifo_empty - Keep this masked. Not relevant." "0,1"
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newline
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bitfld.long 0x4 18. "S_PKTRCV_ERR,TI Internal Feature. Debug only. If the packetReceived arrives at a wrong time. It should NOT be coming while in IDLE state (as no packet was sent before) and in HIBER state (where the next LL group is being evaluated)." "0,1"
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newline
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bitfld.long 0x4 17. "S_FRAME_ERR,Indicates the FrameStart arrived before CBUFF has completed sending out data for all the Chirps programmed" "0,1"
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newline
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bitfld.long 0x4 16. "S_CHIRP_ERR,Indicates tha the chirpAvailable from ADCBuffer arrived before CBUFF has completed sending out the previous Chirp data." "0,1"
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newline
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hexmask.long.byte 0x4 12.--15. 1. "S1_UNUSED2,RESERVED"
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newline
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bitfld.long 0x4 11. "S_CBFIFO_EMPTY,TI Internal Feature. Debug only. CBUFF_FIFO Empty Status - Keep this masked since full and empty will be normal conditions." "0,1"
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newline
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bitfld.long 0x4 10. "S_CBFIFO_FULL,TI Internal Feature. Debug only. CBUFF_FIFO Full Status - Keep this masked since full and empty will be normal conditions." "0,1"
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newline
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bitfld.long 0x4 9. "S_CBPUSH_ERR,TI Internal Feature. Debug only. CBUFF_FIFO_PUSH_ERROR" "0,1"
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newline
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bitfld.long 0x4 8. "S_CBPOP_ERR,TI Internal Feature. Debug only. CBUFF_FIFO_POP_ERROR" "0,1"
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newline
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hexmask.long.byte 0x4 3.--7. 1. "S1_UNUSED1,RESERVED"
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newline
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bitfld.long 0x4 2. "S_LCLPUSH_ERR,TI Internal Feature. Debug only. LCL_FIFO_PUSH_ERROR" "0,1"
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newline
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bitfld.long 0x4 1. "S_LCLPOP_ERR,TI Internal Feature. Debug only. LCL_FIFO_POP_ERROR" "0,1"
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newline
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bitfld.long 0x4 0. "S_LCLFSM_ERR,TI Internal Feature. Debug only. LCL_FIFO_FSM_ERROR" "0,1"
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repeat 2. (list 0x2 0x3)(list 0x0 0x4)
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rgroup.long ($2+0x1F4)++0x3
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line.long 0x0 "STAT_CBUFF_REG$1,"
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hexmask.long 0x0 0.--31. 1. "STAT_CBUFF_REG2,RESERVED. This does not have coresponding clear or mask"
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repeat.end
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rgroup.long 0x1FC++0x3
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line.long 0x0 "STAT_LVDS_REG0,"
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hexmask.long 0x0 0.--31. 1. "STAT_LVDS_REG0,TI Internal Feature. Debug only. Clr is CLR_LVDS_REG0 and MASK is CFG_MASK_REG2 FSM_STAT_CODE: [3:0] is for Ch0 [7:4] is for Ch1 [11:8] is for Ch2 [15:12] is for ch3 ASYNC_FIFO_STATUS: [19:16] is for Ch0 [23:20] is for Ch1 [27:24] is.."
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repeat 3. (list 0x1 0x2 0x3)(list 0x0 0x4 0x8)
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rgroup.long ($2+0x200)++0x3
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line.long 0x0 "STAT_LVDS_REG$1,"
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hexmask.long 0x0 0.--31. 1. "STAT_LVDS_REG1,RESERVED"
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repeat.end
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group.long 0x20C++0xF
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line.long 0x0 "CLR_CBUFF_REG0,"
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hexmask.long.tbyte 0x0 13.--31. 1. "CLR_CBUFF_REG0_OTHERS,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field"
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newline
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bitfld.long 0x0 12. "C_FRAME_DONE,Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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newline
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bitfld.long 0x0 11. "C_CHIRP_DONE,Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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newline
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hexmask.long.byte 0x0 6.--10. 1. "C_LL_INDEX,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field"
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newline
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bitfld.long 0x0 5. "C_CSI_PKT_LP_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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newline
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bitfld.long 0x0 4. "C_CSI_PKT_HE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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newline
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bitfld.long 0x0 3. "C_CSI_PKT_HS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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newline
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bitfld.long 0x0 2. "C_CSI_PKT_VE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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newline
|
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bitfld.long 0x0 1. "C_CSI_PKT_VS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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newline
|
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bitfld.long 0x0 0. "C_CSI_PKT_RCVD,TI Internal Feature. Clear Register field corresponding to STAT_CBUFF_REG0. Write 0x1 to Clear the field" "0,1"
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|
line.long 0x4 "CLR_CBUFF_REG1,"
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hexmask.long 0x4 0.--31. 1. "CLR_CBUFF_REG1,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG1. Write 0x1 to Clear the field"
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line.long 0x8 "CLR_LVDS_REG0,"
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hexmask.long 0x8 0.--31. 1. "CLR_LVDS_REG0,TI Internal Feature.Clear Register field corresponding to STAT_LVDS_REG0. Write 0x1 to Clear the field"
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line.long 0xC "CLR_LVDS_REG1,"
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hexmask.long 0xC 0.--31. 1. "CLR_LVDS_REG1,RESERVED"
|
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rgroup.long 0x21C++0x3
|
|
line.long 0x0 "STAT_CBUFF_ECC_REG,"
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|
hexmask.long.tbyte 0x0 10.--31. 1. "NU2,"
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|
newline
|
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bitfld.long 0x0 9. "seccdbe,0 : No Double bit error 1 : Indicates a double bit error has occurred" "0: No Double bit error,1: Indicates a double bit error has occurred"
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newline
|
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bitfld.long 0x0 8. "seccsbe,0 : No Single bit error 1 : Indicates a single bit error has occurred" "0: No Single bit error,1: Indicates a single bit error has occurred"
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newline
|
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bitfld.long 0x0 6.--7. "NU1," "0,1,2,3"
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|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "seccadd,6-bit address where the ECC error occurred. It is valid when either seccsbe or seccdbe is set. If none of them is set then the addr does not mean anything."
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group.long 0x220++0x7
|
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line.long 0x0 "MASK_CBUFF_ECC_REG,"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU2,"
|
|
newline
|
|
bitfld.long 0x0 9. "meccdbe,0 : Double bit error indications are unmasked 1 : Double bit error indications are Masked" "0: Double bit error indications are unmasked,1: Double bit error indications are Masked"
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newline
|
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bitfld.long 0x0 8. "meccsbe,0 : Single bit error indications are unmasked 1 : Single bit error indications are Masked" "0: Single bit error indications are unmasked,1: Single bit error indications are Masked"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "NU1,"
|
|
line.long 0x4 "CLR_CBUFF_ECC_REG,"
|
|
hexmask.long.tbyte 0x4 10.--31. 1. "NU2,"
|
|
newline
|
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bitfld.long 0x4 9. "ceccdbe,Clear Register field corresponding to STAT_CBUFF_ECC. Write 0x1 to Clear the field" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "ceccsbe,Clear Register field corresponding to STAT_CBUFF_ECC. Write 0x1 to Clear the field" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 1.--7. 1. "NU1,"
|
|
newline
|
|
bitfld.long 0x4 0. "ceccadd,Clear Register field corresponding to STAT_CBUFF_ECC. Write 0x1 to Clear the field" "0,1"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x0 "STAT_SAFETY,"
|
|
hexmask.long.tbyte 0x0 9.--31. 1. "SAF_UNUSED1,RESERVED"
|
|
newline
|
|
bitfld.long 0x0 8. "SAF_CHIRP_ERR,Safety Error. Indicates tha the chirpAvailable from ADCBuffer arrived before CBUFF has completed sending out the previous Chirp data." "0,1"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "SAF_CRC,TRM Desccription : Indicates a CRC error between ADCBuffer and CBUFF. 0 : No Error Non Zero : Error TI Restricted Description : 0 - CRC for col-0 - [15:0] 1 - CRC for col-1 [31:16]; 2 - CRC for col-2 [47:32]; 3 - CRC for col-3 [63:48] 4 - CRC.."
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|
group.long 0x22C++0x7
|
|
line.long 0x0 "MASK_SAFETY,"
|
|
hexmask.long 0x0 0.--31. 1. "MASK_SAFETY,Mask Register field corresponding to STAT_SAFETY. Refer STAT_SAFETY for bitwise mapping. 0 : Event is unmasked and will cause an interrupt on occuruence 1 : Event is masked. No interrupt will be generated on occurrence"
|
|
line.long 0x4 "CLR_SAFETY,"
|
|
hexmask.long 0x4 0.--31. 1. "CLR_SAFETY,Clear Register field corresponding to STAT_SAFETY. Write 0x1 to Clear the field"
|
|
tree.end
|
|
tree "DSS_CTRL"
|
|
base ad:0x6020000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
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|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
repeat 3. (list 0x0 0x1 0x3)(list 0x0 0x4 0xC)
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "HW_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg0,Reserved for R&D"
|
|
repeat.end
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PREVIOUS_NAME,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg2,Reserved for R&D"
|
|
group.long 0x14++0x4F
|
|
line.long 0x0 "DSS_SW_INT,"
|
|
hexmask.long.byte 0x0 0.--3. 1. "dss_swint,Write pulse bit field: DSS SW Interrupt Write 1 : Generate an interrupt on DSS_SW_INT0"
|
|
line.long 0x4 "DSS_TPCC_A_ERRAGG_MASK,"
|
|
bitfld.long 0x4 26. "tptc_a1_read_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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|
newline
|
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bitfld.long 0x4 25. "tptc_a0_read_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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|
newline
|
|
bitfld.long 0x4 24. "tpcc_a_read_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 18. "tptc_a1_write_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPTC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 17. "tptc_a0_write_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPTC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 16. "tpcc_a_write_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 8. "tpcc_a_parity_err,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 3. "tptc_a1_err,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 2. "tptc_a0_err,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 1. "tpcc_a_mpint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 0. "tpcc_a_errint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
line.long 0x8 "DSS_TPCC_A_ERRAGG_STATUS,"
|
|
bitfld.long 0x8 26. "tptc_a1_read_access_error,Status of Interrupt from DSS_TPTC_A1. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "tptc_a0_read_access_error,Status of Interrupt from DSS_TPTC_A0. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "tpcc_a_read_access_error,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "tptc_a1_write_access_error,Status of Interrupt from DSS_TPTC_A1. Set only if Interupt is unmasked in DSS_TPTC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "tptc_a0_write_access_error,Status of Interrupt from DSS_TPTC_A0. Set only if Interupt is unmasked in DSS_TPTC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "tpcc_a_write_access_error,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "tpcc_a_parity_err,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "tptc_a1_err,Status of Interrupt from DSS_TPTC_A1. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "tptc_a0_err,Status of Interrupt from DSS_TPTC_A0. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
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bitfld.long 0x8 1. "tpcc_a_mpint,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 0. "tpcc_a_errint,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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line.long 0xC "DSS_TPCC_A_ERRAGG_STATUS_RAW,"
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bitfld.long 0xC 26. "tptc_a1_read_access_error,Raw Status of Interrupt from DSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 25. "tptc_a0_read_access_error,Raw Status of Interrupt from DSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 24. "tpcc_a_read_access_error,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 18. "tptc_a1_write_access_error,Raw Status of Interrupt from DSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in DSS_TPTC_A_INTAGG_MASK" "0,1"
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bitfld.long 0xC 17. "tptc_a0_write_access_error,Raw Status of Interrupt from DSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in DSS_TPTC_A_INTAGG_MASK" "0,1"
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bitfld.long 0xC 16. "tpcc_a_write_access_error,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 8. "tpcc_a_parity_err,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 3. "tptc_a1_err,Raw Status of Interrupt from DSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 2. "tptc_a0_err,Raw Status of Interrupt from DSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 1. "tpcc_a_mpint,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0xC 0. "tpcc_a_errint,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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line.long 0x10 "DSS_TPCC_A_INTAGG_MASK,"
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bitfld.long 0x10 17. "tptc_a1,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 16. "tptc_a0,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 8. "tpcc_a_int7,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 7. "tpcc_a_int6,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 6. "tpcc_a_int5,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 5. "tpcc_a_int4,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 4. "tpcc_a_int3,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 3. "tpcc_a_int2,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 2. "tpcc_a_int1,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 1. "tpcc_a_int0,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 0. "tpcc_a_intg,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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line.long 0x14 "DSS_TPCC_A_INTAGG_STATUS,"
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bitfld.long 0x14 17. "tptc_a1,Status of Interrupt from DSS_TPTC_A1. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 16. "tptc_a0,Status of Interrupt from DSS_TPTC_A0. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 8. "tpcc_a_int7,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 7. "tpcc_a_int6,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 6. "tpcc_a_int5,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 5. "tpcc_a_int4,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 4. "tpcc_a_int3,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 3. "tpcc_a_int2,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 2. "tpcc_a_int1,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 1. "tpcc_a_int0,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 0. "tpcc_a_intg,Status of Interrupt from DSS_TPCC_A. Set only if Interupt is unmasked in DSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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line.long 0x18 "DSS_TPCC_A_INTAGG_STATUS_RAW,"
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bitfld.long 0x18 17. "tptc_a1,Raw Status of Interrupt from DSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 16. "tptc_a0,Raw Status of Interrupt from DSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 8. "tpcc_a_int7,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 7. "tpcc_a_int6,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 6. "tpcc_a_int5,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 5. "tpcc_a_int4,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 4. "tpcc_a_int3,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 3. "tpcc_a_int2,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 2. "tpcc_a_int1,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 1. "tpcc_a_int0,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x18 0. "tpcc_a_intg,Raw Status of Interrupt from DSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_A_INTAGG_MASK" "0,1"
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line.long 0x1C "DSS_TPCC_B_ERRAGG_MASK,"
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bitfld.long 0x1C 26. "tptc_b1_read_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 25. "tptc_b0_read_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 24. "tpcc_b_read_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 18. "tptc_b1_write_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 17. "tptc_b0_write_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 16. "tpcc_b_write_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 8. "tpcc_b_parity_err,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 3. "tptc_b1_err,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 2. "tptc_b0_err,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 1. "tpcc_b_mpint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x1C 0. "tpcc_b_errint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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line.long 0x20 "DSS_TPCC_B_ERRAGG_STATUS,"
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bitfld.long 0x20 26. "tptc_b1_read_access_error,Status of Error from DSS_TPTC_B1. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 25. "tptc_b0_read_access_error,Status of Error from DSS_TPTC_B0. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 24. "tpcc_b_read_access_error,Status of Error from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 18. "tptc_b1_write_access_error,Status of Error from DSS_TPTC_B1. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 17. "tptc_b0_write_access_error,Status of Error from DSS_TPTC_B0. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 16. "tpcc_b_write_access_error,Status of Error from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 8. "tpcc_b_parity_err,Status of Error from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 3. "tptc_b1_err,Status of Error from DSS_TPCC_B1. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 2. "tptc_b0_err,Status of Error from DSS_TPTC_B0. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 1. "tpcc_b_mpint,Status of Error from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x20 0. "tpcc_b_errint,Status of Error from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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line.long 0x24 "DSS_TPCC_B_ERRAGG_STATUS_RAW,"
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bitfld.long 0x24 26. "tptc_b1_read_access_error,Raw Status of Error from DSS_TPTC_B1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 25. "tptc_b0_read_access_error,Raw Status of Error from DSS_TPTC_B0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 24. "tpcc_b_read_access_error,Raw Status of Error from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 18. "tptc_b1_write_access_error,Raw Status of Error from DSS_TPTC_B1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 17. "tptc_b0_write_access_error,Raw Status of Error from DSS_TPTC_B0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 16. "tpcc_b_write_access_error,Raw Status of Error from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 8. "tpcc_b_parity_err,Raw Status of Error from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 3. "tptc_b1_err,Raw Status of Error from DSS_TPCC_B1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 2. "tptc_b0_err,Raw Status of Error from DSS_TPTC_B0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 1. "tpcc_b_mpint,Raw Status of Error from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x24 0. "tpcc_b_errint,Raw Status of Error from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_ERRAGG_MASK" "0,1"
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line.long 0x28 "DSS_TPCC_B_INTAGG_MASK,"
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bitfld.long 0x28 17. "tptc_b1,Mask Interrupt from DSS_TPTC_B1 to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 16. "tptc_b0,Mask Interrupt from DSS_TPTC_B0 to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 8. "tpcc_b_int7,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 7. "tpcc_b_int6,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 6. "tpcc_b_int5,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 5. "tpcc_b_int4,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 4. "tpcc_b_int3,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 3. "tpcc_b_int2,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 2. "tpcc_b_int1,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 1. "tpcc_b_int0,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x28 0. "tpcc_b_intg,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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line.long 0x2C "DSS_TPCC_B_INTAGG_STATUS,"
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bitfld.long 0x2C 17. "tptc_b1,Status of Interrupt from DSS_TPTC_B1. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 16. "tptc_b0,Status of Interrupt from DSS_TPTC_B0. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 8. "tpcc_b_int7,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 7. "tpcc_b_int6,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 6. "tpcc_b_int5,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 5. "tpcc_b_int4,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 4. "tpcc_b_int3,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 3. "tpcc_b_int2,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 2. "tpcc_b_int1,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 1. "tpcc_b_int0,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x2C 0. "tpcc_b_intg,Status of Interrupt from DSS_TPCC_B. Set only if Interupt is unmasked in DSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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line.long 0x30 "DSS_TPCC_B_INTAGG_STATUS_RAW,"
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bitfld.long 0x30 17. "tptc_b1,Raw Status of Interrupt from DSS_TPTC_B1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 16. "tptc_b0,Raw Status of Interrupt from DSS_TPTC_B0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 8. "tpcc_b_int7,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 7. "tpcc_b_int6,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 6. "tpcc_b_int5,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 5. "tpcc_b_int4,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 4. "tpcc_b_int3,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 3. "tpcc_b_int2,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 2. "tpcc_b_int1,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 1. "tpcc_b_int0,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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bitfld.long 0x30 0. "tpcc_b_intg,Raw Status of Interrupt from DSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_B_INTAGG_MASK" "0,1"
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line.long 0x34 "DSS_TPCC_C_ERRAGG_MASK,"
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bitfld.long 0x34 30. "tptc_c5_read_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 29. "tptc_c4_read_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 28. "tptc_c3_read_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 27. "tptc_c2_read_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 26. "tptc_c1_read_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 25. "tptc_c0_read_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 24. "tpcc_c_read_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 22. "tptc_c5_write_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 21. "tptc_c4_write_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 20. "tptc_c3_write_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 19. "tptc_c2_write_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 18. "tptc_c1_write_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 17. "tptc_c0_write_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 16. "tpcc_c_write_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 8. "tpcc_c_parity_err,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 7. "tptc_c5_err,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 6. "tptc_c4_err,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 5. "tptc_c3_err,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 4. "tptc_c2_err,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 3. "tptc_c1_err,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 2. "tptc_c0_err,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 1. "tpcc_c_mpint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x34 0. "tpcc_c_errint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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line.long 0x38 "DSS_TPCC_C_ERRAGG_STATUS,"
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bitfld.long 0x38 30. "tptc_c5_read_access_error,Status of Error from DSS_TPTC_C5. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 29. "tptc_c4_read_access_error,Status of Error from DSS_TPTC_C4. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 28. "tptc_c3_read_access_error,Status of Error from DSS_TPTC_C3. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 27. "tptc_c2_read_access_error,Status of Error from DSS_TPTC_C2. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 26. "tptc_c1_read_access_error,Status of Error from DSS_TPTC_C1. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 25. "tptc_c0_read_access_error,Status of Error from DSS_TPTC_C0. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 24. "tpcc_c_read_access_error,Status of Error from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 22. "tptc_c5_write_access_error,Status of Error from DSS_TPTC_C5. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 21. "tptc_c4_write_access_error,Status of Error from DSS_TPTC_C4. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 20. "tptc_c3_write_access_error,Status of Error from DSS_TPTC_C3. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 19. "tptc_c2_write_access_error,Status of Error from DSS_TPTC_C2. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 18. "tptc_c1_write_access_error,Status of Error from DSS_TPTC_C1. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 17. "tptc_c0_write_access_error,Status of Error from DSS_TPTC_C0. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 16. "tpcc_c_write_access_error,Status of Error from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 8. "tpcc_c_parity_err,Status of Error from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 7. "tptc_c5_err,Status of Error from DSS_TPTC_C5. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 6. "tptc_c4_err,Status of Error from DSS_TPTC_C4. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 5. "tptc_c3_err,Status of Error from DSS_TPTC_C3. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 4. "tptc_c2_err,Status of Error from DSS_TPTC_C2. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 3. "tptc_c1_err,Status of Error from DSS_TPTC_C1. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 2. "tptc_c0_err,Status of Error from DSS_TPTC_C0. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 1. "tpcc_c_mpint,Status of Error from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x38 0. "tpcc_c_errint,Status of Error from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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line.long 0x3C "DSS_TPCC_C_ERRAGG_STATUS_RAW,"
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bitfld.long 0x3C 30. "tptc_c5_read_access_error,Raw Status of Error from DSS_TPTC_C5. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 29. "tptc_c4_read_access_error,Raw Status of Error from DSS_TPTC_C4. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 28. "tptc_c3_read_access_error,Raw Status of Error from DSS_TPTC_C3. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 27. "tptc_c2_read_access_error,Raw Status of Error from DSS_TPTC_C2. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 26. "tptc_c1_read_access_error,Raw Status of Error from DSS_TPTC_C1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 25. "tptc_c0_read_access_error,Raw Status of Error from DSS_TPTC_C0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 24. "tpcc_c_read_access_error,Raw Status of Error from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 22. "tptc_c5_write_access_error,Raw Status of Error from DSS_TPTC_C5. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 21. "tptc_c4_write_access_error,Raw Status of Error from DSS_TPTC_C4. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 20. "tptc_c3_write_access_error,Raw Status of Error from DSS_TPTC_C3. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 19. "tptc_c2_write_access_error,Raw Status of Error from DSS_TPTC_C2. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 18. "tptc_c1_write_access_error,Raw Status of Error from DSS_TPTC_C1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 17. "tptc_c0_write_access_error,Raw Status of Error from DSS_TPTC_C0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 16. "tpcc_c_write_access_error,Raw Status of Error from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 8. "tpcc_c_parity_err,Raw Status of Error from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 7. "tptc_c5_err,Raw Status of Error from DSS_TPTC_C5. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 6. "tptc_c4_err,Raw Status of Error from DSS_TPTC_C4. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 5. "tptc_c3_err,Raw Status of Error from DSS_TPTC_C3. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 4. "tptc_c2_err,Raw Status of Error from DSS_TPTC_C2. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 3. "tptc_c1_err,Raw Status of Error from DSS_TPTC_C1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 2. "tptc_c0_err,Raw Status of Error from DSS_TPTC_C0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 1. "tpcc_c_mpint,Raw Status of Error from DSS_TPCC_C0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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bitfld.long 0x3C 0. "tpcc_c_errint,Raw Status of Error from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_ERRAGG_MASK" "0,1"
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line.long 0x40 "DSS_TPCC_C_INTAGG_MASK,"
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bitfld.long 0x40 21. "tptc_c5,Mask Interrupt from DSS_TPTC_C5 to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x40 20. "tptc_c4,Mask Interrupt from DSS_TPTC_C4 to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x40 19. "tptc_c3,Mask Interrupt from DSS_TPTC_C3 to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 18. "tptc_c2,Mask Interrupt from DSS_TPTC_C2 to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 17. "tptc_c1,Mask Interrupt from DSS_TPTC_C1 to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 16. "tptc_c0,Mask Interrupt from DSS_TPTC_C0 to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 8. "tpcc_c_int7,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 7. "tpcc_c_int6,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 6. "tpcc_c_int5,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 5. "tpcc_c_int4,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 4. "tpcc_c_int3,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 3. "tpcc_c_int2,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 2. "tpcc_c_int1,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 1. "tpcc_c_int0,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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newline
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bitfld.long 0x40 0. "tpcc_c_intg,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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line.long 0x44 "DSS_TPCC_C_INTAGG_STATUS,"
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bitfld.long 0x44 21. "tptc_c5,Status of Interrupt from DSS_TPTC_C5. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x44 20. "tptc_c4,Status of Interrupt from DSS_TPTC_C4. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x44 19. "tptc_c3,Status of Interrupt from DSS_TPTC_C3. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x44 18. "tptc_c2,Status of Interrupt from DSS_TPTC_C2. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x44 17. "tptc_c1,Status of Interrupt from DSS_TPTC_C1. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x44 16. "tptc_c0,Status of Interrupt from DSS_TPTC_C0. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 8. "tpcc_c_int7,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 7. "tpcc_c_int6,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 6. "tpcc_c_int5,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 5. "tpcc_c_int4,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 4. "tpcc_c_int3,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 3. "tpcc_c_int2,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 2. "tpcc_c_int1,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 1. "tpcc_c_int0,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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newline
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bitfld.long 0x44 0. "tpcc_c_intg,Status of Interrupt from DSS_TPCC_C. Set only if Interupt is unmasked in DSS_TPCC_C_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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line.long 0x48 "DSS_TPCC_C_INTAGG_STATUS_RAW,"
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bitfld.long 0x48 21. "tptc_c5,Raw Status of Interrupt from DSS_TPTC_C5. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 20. "tptc_c4,Raw Status of Interrupt from DSS_TPTC_C4. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 19. "tptc_c3,Raw Status of Interrupt from DSS_TPTC_C3. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 18. "tptc_c2,Raw Status of Interrupt from DSS_TPTC_C2. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 17. "tptc_c1,Raw Status of Interrupt from DSS_TPTC_C1. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 16. "tptc_c0,Raw Status of Interrupt from DSS_TPTC_C0. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 8. "tpcc_c_int7,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 7. "tpcc_c_int6,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 6. "tpcc_c_int5,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 5. "tpcc_c_int4,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 4. "tpcc_c_int3,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 3. "tpcc_c_int2,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 2. "tpcc_c_int1,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 1. "tpcc_c_int0,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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newline
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bitfld.long 0x48 0. "tpcc_c_intg,Raw Status of Interrupt from DSS_TPCC_C. Set irrespective if the Interupt is masked or unmasked in DSS_TPCC_C_INTAGG_MASK" "0,1"
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line.long 0x4C "DSS_TPCC_MEMINIT_START,"
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bitfld.long 0x4C 2. "tpcc_c_meminit_start,Write pulse bit field: Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation.." "0,1"
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newline
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bitfld.long 0x4C 1. "tpcc_b_meminit_start,Write pulse bit field: Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation.." "0,1"
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newline
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bitfld.long 0x4C 0. "tpcc_a_meminit_start,Write pulse bit field: Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation.." "0,1"
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rgroup.long 0x64++0x3
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line.long 0x0 "DSS_TPCC_MEMINIT_STATUS,"
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bitfld.long 0x0 2. "tpcc_c_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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newline
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bitfld.long 0x0 1. "tpcc_b_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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newline
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bitfld.long 0x0 0. "tpcc_a_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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group.long 0x68++0x7
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line.long 0x0 "DSS_TPCC_MEMINIT_DONE,"
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bitfld.long 0x0 2. "tpcc_c_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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newline
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bitfld.long 0x0 1. "tpcc_b_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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newline
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bitfld.long 0x0 0. "tpcc_a_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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line.long 0x4 "DSS_DSP_L2RAM_PARITY_CTRL,"
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hexmask.long.byte 0x4 8.--15. 1. "err_clear,Write to bit N to clear L2 Parity Error line N"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "enable,Write to bit N to enable L2 Parity N"
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repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
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rgroup.long ($2+0x70)++0x3
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line.long 0x0 "DSS_DSP_L2RAM_PARITY_ERR_STATUS_VB$1,"
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hexmask.long.word 0x0 16.--27. 1. "addr1,Error address 1 for Virtual Bank 0"
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newline
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hexmask.long.word 0x0 0.--11. 1. "addr0,Error address 0 for Virtual Bank 0"
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repeat.end
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group.long 0x80++0x3
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line.long 0x0 "DSS_DSP_L2RAM_MEMINIT_START,"
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bitfld.long 0x0 7. "vb31,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x0 6. "vb30,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x0 5. "vb21,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x0 4. "vb20,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x0 3. "vb11,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x0 2. "vb10,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x0 1. "vb01,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x0 0. "vb00,Write pulse bit field: Start Memory intialization of DSP L2 memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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rgroup.long 0x84++0x3
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line.long 0x0 "DSS_DSP_L2RAM_MEMINIT_STATUS,"
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bitfld.long 0x0 7. "vb31,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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newline
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bitfld.long 0x0 6. "vb30,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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newline
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bitfld.long 0x0 5. "vb21,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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newline
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bitfld.long 0x0 4. "vb20,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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newline
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bitfld.long 0x0 3. "vb11,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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newline
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bitfld.long 0x0 2. "vb10,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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newline
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bitfld.long 0x0 1. "vb01,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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newline
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bitfld.long 0x0 0. "vb00,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 memory is in progress." "0,1"
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group.long 0x88++0x7
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line.long 0x0 "DSS_DSP_L2RAM_MEMINIT_DONE,"
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bitfld.long 0x0 7. "vb31,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 6. "vb30,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 5. "vb21,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 4. "vb20,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 3. "vb11,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 2. "vb10,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 1. "vb01,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 0. "vb00,Status field. Read value 0x1 indicates previously triggered Memory intialization of L2 Memory is complete. Write 0x1 to clear status." "0,1"
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line.long 0x4 "DSS_DSP_L2RAM_PARITY_MEMINIT_START,"
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bitfld.long 0x4 7. "vb31,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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newline
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bitfld.long 0x4 6. "vb30,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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newline
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bitfld.long 0x4 5. "vb21,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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newline
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bitfld.long 0x4 4. "vb20,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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newline
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bitfld.long 0x4 3. "vb11,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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newline
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bitfld.long 0x4 2. "vb10,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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newline
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bitfld.long 0x4 1. "vb01,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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newline
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bitfld.long 0x4 0. "vb00,Write pulse bit field: Start Memory intialization of DSP L2 Parity memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that.." "0,1"
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rgroup.long 0x90++0x3
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line.long 0x0 "DSS_DSP_L2RAM_PARITY_MEMINIT_STATUS,"
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bitfld.long 0x0 7. "vb31,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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newline
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bitfld.long 0x0 6. "vb30,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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newline
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bitfld.long 0x0 5. "vb21,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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newline
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bitfld.long 0x0 4. "vb20,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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newline
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bitfld.long 0x0 3. "vb11,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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newline
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bitfld.long 0x0 2. "vb10,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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newline
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bitfld.long 0x0 1. "vb01,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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newline
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bitfld.long 0x0 0. "vb00,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is in progress." "0,1"
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group.long 0x94++0x7
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line.long 0x0 "DSS_DSP_L2RAM_PARITY_MEMINIT_DONE,"
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bitfld.long 0x0 7. "vb31,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 6. "vb30,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 5. "vb21,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 4. "vb20,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 3. "vb11,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 2. "vb10,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 1. "vb01,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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newline
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bitfld.long 0x0 0. "vb00,Status field. Read value 0x1 indicates previously triggered Memory intialization of DSP L2 Parity memory is complete. Write 0x1 to clear status." "0,1"
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line.long 0x4 "DSS_L3RAM_MEMINIT_START,"
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bitfld.long 0x4 3. "l3ram3_meminit_start,Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence ensure that there is.." "0,1"
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newline
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bitfld.long 0x4 2. "l3ram2_meminit_start,Write pulse bit field: Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation.." "0,1"
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newline
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bitfld.long 0x4 1. "l3ram1_meminit_start,Write pulse bit field: Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation.." "0,1"
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newline
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bitfld.long 0x4 0. "l3ram0_meminit_start,Write pulse bit field: Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation.." "0,1"
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rgroup.long 0x9C++0x3
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line.long 0x0 "DSS_L3RAM_MEMINIT_STATUS,"
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bitfld.long 0x0 3. "l3ram3_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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newline
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bitfld.long 0x0 2. "l3ram2_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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newline
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bitfld.long 0x0 1. "l3ram1_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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newline
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bitfld.long 0x0 0. "l3ram0_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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group.long 0xA0++0x3
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line.long 0x0 "DSS_L3RAM_MEMINIT_DONE,"
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bitfld.long 0x0 3. "l3ram3_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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newline
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bitfld.long 0x0 2. "l3ram2_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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newline
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bitfld.long 0x0 1. "l3ram1_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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newline
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bitfld.long 0x0 0. "l3ram0_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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group.long 0xB0++0x3
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line.long 0x0 "DSS_MAILBOX_MEMINIT_START,"
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bitfld.long 0x0 0. "meminit_start,Write pulse bit field: Start Memory intialization of TPCC A Param memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed. Before starting new initilzation sequence.." "0,1"
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rgroup.long 0xB4++0x3
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line.long 0x0 "DSS_MAILBOX_MEMINIT_STATUS,"
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bitfld.long 0x0 0. "meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is in progress." "0,1"
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group.long 0xB8++0xF
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line.long 0x0 "DSS_MAILBOX_MEMINIT_DONE,"
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bitfld.long 0x0 0. "meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of TPCC A Param memory is complte. Write 0x1 to clear status. Refer TPCC Memory initialization sequnce in EDMA section for more details" "0,1"
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line.long 0x4 "DSS_TPCC_A_PARITY_CTRL,"
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bitfld.long 0x4 2. "parity_err_clr,Write pulse bit field: Write 0x1 to clear the Parit Error status for TPCC" "0,1"
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newline
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bitfld.long 0x4 1. "parity_testen,Enable Parity Test for TPCC. Write 0x1 : Parity Test is enabled on PARAM memory" "?,1: Parity Test is enabled on PARAM memory"
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newline
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bitfld.long 0x4 0. "parity_en,Enable Parity for TPCC. Write 0x1 : Parity is enabled on PARAM memory" "?,1: Parity is enabled on PARAM memory"
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line.long 0x8 "DSS_TPCC_B_PARITY_CTRL,"
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bitfld.long 0x8 2. "parity_err_clr,Write pulse bit field: Write 0x1 to clear the Parit Error status for TPCC" "0,1"
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newline
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bitfld.long 0x8 1. "parity_testen,Enable Parity Test for TPCC. Write 0x1 : Parity Test is enabled on PARAM memory" "?,1: Parity Test is enabled on PARAM memory"
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newline
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bitfld.long 0x8 0. "parity_en,Enable Parity for TPCC. Write 0x1 : Parity is enabled on PARAM memory" "?,1: Parity is enabled on PARAM memory"
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line.long 0xC "DSS_TPCC_C_PARITY_CTRL,"
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bitfld.long 0xC 2. "parity_err_clr,Write pulse bit field: Write 0x1 to clear the Parit Error status for TPCC" "0,1"
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newline
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bitfld.long 0xC 1. "parity_testen,Enable Parity Test for TPCC. Write 0x1 : Parity Test is enabled on PARAM memory" "?,1: Parity Test is enabled on PARAM memory"
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newline
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bitfld.long 0xC 0. "parity_en,Enable Parity for TPCC. Write 0x1 : Parity is enabled on PARAM memory" "?,1: Parity is enabled on PARAM memory"
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rgroup.long 0xC8++0xB
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line.long 0x0 "DSS_TPCC_A_PARITY_STATUS,"
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hexmask.long.byte 0x0 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
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line.long 0x4 "DSS_TPCC_B_PARITY_STATUS,"
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hexmask.long.byte 0x4 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
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line.long 0x8 "DSS_TPCC_C_PARITY_STATUS,"
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hexmask.long.word 0x8 0.--8. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
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group.long 0xD4++0xF
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line.long 0x0 "TPTC_DBS_CONFIG,"
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bitfld.long 0x0 18.--19. "tptc_c5,Max Burst size tieoff value for TPTC C5" "0,1,2,3"
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newline
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bitfld.long 0x0 16.--17. "tptc_c4,Max Burst size tieoff value for TPTC C4" "0,1,2,3"
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newline
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bitfld.long 0x0 14.--15. "tptc_c3,Max Burst size tieoff value for TPTC C3" "0,1,2,3"
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newline
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bitfld.long 0x0 12.--13. "tptc_c2,Max Burst size tieoff value for TPTC C2" "0,1,2,3"
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newline
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bitfld.long 0x0 10.--11. "tptc_c1,Max Burst size tieoff value for TPTC C1" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "tptc_c0,Max Burst size tieoff value for TPTC C0" "0,1,2,3"
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newline
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bitfld.long 0x0 6.--7. "tptc_b1,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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newline
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bitfld.long 0x0 4.--5. "tptc_b0,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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newline
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bitfld.long 0x0 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
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newline
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bitfld.long 0x0 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
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line.long 0x4 "DSS_DSP_BOOTCFG,"
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bitfld.long 0x4 25. "L1P_CACHE_MODE,DSP Boot Configuration : L1P Cache Mode" "0,1"
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newline
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bitfld.long 0x4 24. "L1D_CACHE_MODE,DSP Boot Configuration : L1D Cache Mode" "0,1"
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newline
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hexmask.long.tbyte 0x4 0.--21. 1. "ISTP_RST_VAL,DSP Boot Configuration : Reset Vector"
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line.long 0x8 "DSS_DSP_NMI_GATE,"
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bitfld.long 0x8 0.--2. "gate,Write 3'b111 to gate the Non Maskable Interrupt to the DSP. This is not expected to be used" "0,1,2,3,4,5,6,7"
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line.long 0xC "DSS_PBIST_KEY_RESET,"
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bitfld.long 0xC 8. "dss_l2_pbist_st_key,DSS L2 PBIST Selftest Key." "0,1"
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newline
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hexmask.long.byte 0xC 4.--7. 1. "dss_pbist_st_reset,DSS PBIST controller will be brought out of reset when value is 0xA"
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newline
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hexmask.long.byte 0xC 0.--3. 1. "dss_pbist_st_key,DSS PBIST Selftest Key. Valid value is 0x5"
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repeat 2. (list 0x0 0x1)(list 0x0 0x4)
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group.long ($2+0xE4)++0x3
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line.long 0x0 "DSS_PBIST_REG$1,"
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hexmask.long 0x0 0.--31. 1. "dss_pbist_reg0,DSP PBIST registers"
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repeat.end
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group.long 0xEC++0x17
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line.long 0x0 "DSS_TPTC_BOUNDARY_CFG0,"
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hexmask.long.byte 0x0 24.--29. 1. "tptc_b1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "tptc_b0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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newline
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hexmask.long.byte 0x0 8.--13. 1. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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line.long 0x4 "DSS_TPTC_BOUNDARY_CFG1,"
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hexmask.long.byte 0x4 24.--29. 1. "tptc_c3_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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newline
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hexmask.long.byte 0x4 16.--21. 1. "tptc_c2_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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newline
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hexmask.long.byte 0x4 8.--13. 1. "tptc_c1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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newline
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hexmask.long.byte 0x4 0.--5. 1. "tptc_c0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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line.long 0x8 "DSS_TPTC_BOUNDARY_CFG2,"
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hexmask.long.byte 0x8 8.--13. 1. "tptc_c5_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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newline
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hexmask.long.byte 0x8 0.--5. 1. "tptc_c4_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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line.long 0xC "DSS_TPTC_XID_REORDER_CFG0,"
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bitfld.long 0xC 24. "tptc_b1_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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newline
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bitfld.long 0xC 16. "tptc_b0_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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newline
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bitfld.long 0xC 8. "tptc_a1_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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newline
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bitfld.long 0xC 0. "tptc_a0_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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line.long 0x10 "DSS_TPTC_XID_REORDER_CFG1,"
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bitfld.long 0x10 24. "tptc_c3_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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newline
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bitfld.long 0x10 16. "tptc_c2_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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newline
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bitfld.long 0x10 8. "tptc_c1_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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newline
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bitfld.long 0x10 0. "tptc_c0_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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line.long 0x14 "DSS_TPTC_XID_REORDER_CFG2,"
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bitfld.long 0x14 8. "tptc_c5_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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newline
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bitfld.long 0x14 0. "tptc_c4_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
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group.long 0x108++0xF
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line.long 0x0 "ESM_GATING0,"
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hexmask.long 0x0 0.--31. 1. "esm_gating,Bit3:0 : writing '000' will ungate the DSS ESM Group2 Error 0 Bit7:4 : writing '000' will ungate the DSS ESM Group2 Error 1 Bit31:28 : writing '000' will ungate the DSS ESM Group2 Error 7"
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line.long 0x4 "ESM_GATING1,"
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hexmask.long 0x4 0.--31. 1. "esm_gating,Bit3:0 : writing '000' will ungate the DSS ESM Group2 Error 8 Bit7:4 : writing '000' will ungate the DSS ESM Group2 Error 9 Bit31:28 : writing '000' will ungate the DSS ESM Group2 Error 15"
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line.long 0x8 "ESM_GATING2,"
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hexmask.long 0x8 0.--31. 1. "esm_gating,Bit3:0 : writing '000' will ungate the DSS ESM Group2 Error 16 Bit7:4 : writing '000' will ungate the DSS ESM Group2 Error 17 Bit31:28 : writing '000' will ungate the DSS ESM Group2 Error 23"
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line.long 0xC "ESM_GATING3,"
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hexmask.long 0xC 0.--31. 1. "esm_gating,Bit3:0 : writing '000' will ungate the DSS ESM Group2 Error 24 Bit7:4 : writing '000' will ungate the DSS ESM Group2 Error 25 Bit31:28 : writing '000' will ungate the DSS ESM Group2 Error 31"
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group.long 0x560++0x37
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line.long 0x0 "DSS_PERIPH_ERRAGG_MASK0,"
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bitfld.long 0x0 11. "rcss_ctrl_wr,Mask the Write error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 10. "rcss_ctrl_rd,Mask the Read error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 9. "rcss_rcm_wr,Mask the Write error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 8. "rcss_rcm_rd,Mask the Read error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 7. "dss_hwa_cfg_wr,Mask the Write error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 6. "dss_hwa_cfg_rd,Mask the Read error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 5. "dss_cm4_ctrl_wr,Mask the Write error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 4. "dss_cm4_ctrl_rd,Mask the Read error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 3. "dss_ctrl_wr,Mask the Write error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 2. "dss_ctrl_rd,Mask the Read error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 1. "dss_rcm_wr,Mask the Write error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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newline
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bitfld.long 0x0 0. "dss_rcm_rd,Mask the Read error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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line.long 0x4 "DSS_PERIPH_ERRAGG_STATUS0,"
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bitfld.long 0x4 11. "rcss_ctrl_wr,Status of the Write error from RCSS_CTRL space. Read 1 : Read error occurred on access to the RCSS_CTRL space" "?,1: Read error occurred on access to the RCSS_CTRL.."
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newline
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bitfld.long 0x4 10. "rcss_ctrl_rd,Status of the Read error from RCSS_CTRL space. Read 1 : Read error occurred on access to the RCSS_CTRL space" "?,1: Read error occurred on access to the RCSS_CTRL.."
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newline
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bitfld.long 0x4 9. "rcss_rcm_wr,Status of the Write error from RCSS_RCM space. Read 1 : Read error occurred on access to the RCSS_RCM space" "?,1: Read error occurred on access to the RCSS_RCM.."
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newline
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bitfld.long 0x4 8. "rcss_rcm_rd,Status of the Read error from RCSS_RCM space. Read 1 : Read error occurred on access to the RCSS_RCM space" "?,1: Read error occurred on access to the RCSS_RCM.."
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newline
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bitfld.long 0x4 7. "dss_hwa_cfg_wr,Status of the Write error from DSS_HWA_CFG space. Read 1 : Read error occurred on access to the DSS_HWA_CFG space" "?,1: Read error occurred on access to the DSS_HWA_CFG.."
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newline
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bitfld.long 0x4 6. "dss_hwa_cfg_rd,Status of the Read error from DSS_HWA_CFG space. Read 1 : Read error occurred on access to the DSS_HWA_CFG space" "?,1: Read error occurred on access to the DSS_HWA_CFG.."
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newline
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bitfld.long 0x4 5. "dss_cm4_ctrl_wr,Status of the Write error from DSS_CM4_CTRL space. Read 1 : Read error occurred on access to the DSS_CM4_CTRL space" "?,1: Read error occurred on access to the.."
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newline
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bitfld.long 0x4 4. "dss_cm4_ctrl_rd,Status of the Read error from DSS_CM4_CTRL space. Read 1 : Read error occurred on access to the DSS_CM4_CTRL space" "?,1: Read error occurred on access to the.."
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newline
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bitfld.long 0x4 3. "dss_ctrl_wr,Status of the Write error from DSS_CTRL space. Read 1 : Read error occurred on access to the DSS_CTRL space" "?,1: Read error occurred on access to the DSS_CTRL.."
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newline
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bitfld.long 0x4 2. "dss_ctrl_rd,Status of the Read error from DSS_CTRL space. Read 1 : Read error occurred on access to the DSS_CTRL space" "?,1: Read error occurred on access to the DSS_CTRL.."
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newline
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bitfld.long 0x4 1. "dss_rcm_wr,Status of the Write error from DSS_RCM space. Read 1 : Read error occurred on access to the DSS_RCM space" "?,1: Read error occurred on access to the DSS_RCM space"
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newline
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bitfld.long 0x4 0. "dss_rcm_rd,Status of the Read error from DSS_RCM space. Read 1 : Read error occurred on access to the DSS_RCM space" "?,1: Read error occurred on access to the DSS_RCM space"
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|
line.long 0x8 "DSS_PERIPH_ERRAGG_STATUS_RAW0,"
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|
bitfld.long 0x8 11. "rcss_ctrl_wr,Raw Status of the Write error from RCSS_CTRL space irrespective of it being masked. Read 1 : Read error occurred on access to the RCSS_CTRL space" "?,1: Read error occurred on access to the RCSS_CTRL.."
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newline
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bitfld.long 0x8 10. "rcss_ctrl_rd,Raw Status of the Read error from RCSS_CTRL space irrespective of it being masked. Read 1 : Read error occurred on access to the RCSS_CTRL space" "?,1: Read error occurred on access to the RCSS_CTRL.."
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newline
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bitfld.long 0x8 9. "rcss_rcm_wr,Raw Status of the Write error from RCSS_RCM space irrespective of it being masked. Read 1 : Read error occurred on access to the RCSS_RCM space" "?,1: Read error occurred on access to the RCSS_RCM.."
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newline
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bitfld.long 0x8 8. "rcss_rcm_rd,Raw Status of the Read error from RCSS_RCM space irrespective of it being masked. Read 1 : Read error occurred on access to the RCSS_RCM space" "?,1: Read error occurred on access to the RCSS_RCM.."
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newline
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bitfld.long 0x8 7. "dss_hwa_cfg_wr,Raw Status of the Write error from DSS_HWA_CFG space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_HWA_CFG space" "?,1: Read error occurred on access to the DSS_HWA_CFG.."
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newline
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bitfld.long 0x8 6. "dss_hwa_cfg_rd,Raw Status of the Read error from DSS_HWA_CFG space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_HWA_CFG space" "?,1: Read error occurred on access to the DSS_HWA_CFG.."
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newline
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bitfld.long 0x8 5. "dss_cm4_ctrl_wr,Raw Status of the Write error from DSS_CM4_CTRL space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_CM4_CTRL space" "?,1: Read error occurred on access to the.."
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newline
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bitfld.long 0x8 4. "dss_cm4_ctrl_rd,Raw Status of the Read error from DSS_CM4_CTRL space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_CM4_CTRL space" "?,1: Read error occurred on access to the.."
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newline
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bitfld.long 0x8 3. "dss_ctrl_wr,Raw Status of the Write error from DSS_CTRL space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_CTRL space" "?,1: Read error occurred on access to the DSS_CTRL.."
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newline
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bitfld.long 0x8 2. "dss_ctrl_rd,Raw Status of the Read error from DSS_CTRL space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_CTRL space" "?,1: Read error occurred on access to the DSS_CTRL.."
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newline
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bitfld.long 0x8 1. "dss_rcm_wr,Raw Status of the Write error from DSS_RCM space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_RCM space" "?,1: Read error occurred on access to the DSS_RCM space"
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newline
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bitfld.long 0x8 0. "dss_rcm_rd,Raw Status of the Read error from DSS_RCM space irrespective of it being masked. Read 1 : Read error occurred on access to the DSS_RCM space" "?,1: Read error occurred on access to the DSS_RCM space"
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line.long 0xC "DSS_DSP_MBOX_WRITE_DONE,"
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bitfld.long 0xC 28. "proc_7,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
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newline
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bitfld.long 0xC 24. "proc_6,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
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newline
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bitfld.long 0xC 20. "proc_5,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
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newline
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bitfld.long 0xC 16. "proc_4,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
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newline
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bitfld.long 0xC 12. "proc_3,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
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newline
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bitfld.long 0xC 8. "proc_2,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
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newline
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bitfld.long 0xC 4. "proc_1,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
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newline
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bitfld.long 0xC 0. "proc_0,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
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line.long 0x10 "DSS_DSP_MBOX_READ_REQ,"
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bitfld.long 0x10 28. "proc_7,This is request from processor 7 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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newline
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bitfld.long 0x10 24. "proc_6,This is request from processor 6 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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newline
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bitfld.long 0x10 20. "proc_5,This is request from processor 5 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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newline
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bitfld.long 0x10 16. "proc_4,This is request from processor 4 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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newline
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bitfld.long 0x10 12. "proc_3,This is request from processor 3 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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newline
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bitfld.long 0x10 8. "proc_2,This is request from processor 2 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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newline
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bitfld.long 0x10 4. "proc_1,This is request from processor 1 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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newline
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bitfld.long 0x10 0. "proc_0,This is request from processor 0 to DSS_DSP. Requesting it to read from mailbox." "0,1"
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line.long 0x14 "DSS_DSP_MBOX_READ_DONE,"
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bitfld.long 0x14 28. "proc_7,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 7" "0,1"
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newline
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bitfld.long 0x14 24. "proc_6,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 6" "0,1"
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newline
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bitfld.long 0x14 20. "proc_5,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 5" "0,1"
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newline
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bitfld.long 0x14 16. "proc_4,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 4" "0,1"
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newline
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bitfld.long 0x14 12. "proc_3,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 3" "0,1"
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newline
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bitfld.long 0x14 8. "proc_2,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 2" "0,1"
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newline
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bitfld.long 0x14 4. "proc_1,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 1" "0,1"
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newline
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bitfld.long 0x14 0. "proc_0,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 0" "0,1"
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line.long 0x18 "DSS_WDT_EVENT_CAPTURE_SEL,"
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hexmask.long.byte 0x18 8.--14. 1. "cap1,Select the DSS_WDT Capture Event 1 from the DSS DSP Interrupt Map"
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newline
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hexmask.long.byte 0x18 0.--6. 1. "cap0,Select the DSS_WDT Capture Event 0 from the DSS DSP Interrupt Map"
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line.long 0x1C "DSS_RTIA_EVENT_CAPTURE_SEL,"
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hexmask.long.byte 0x1C 8.--14. 1. "cap1,Select the DSS_RTIA Capture Event 1 from the DSS DSP Interrupt Map"
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newline
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hexmask.long.byte 0x1C 0.--6. 1. "cap0,Select the DSS_RTIA Capture Event 0 from the DSS DSP Interrupt Map"
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line.long 0x20 "DSS_RTIB_EVENT_CAPTURE_SEL,"
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hexmask.long.byte 0x20 8.--14. 1. "cap1,Select the DSS_RTIB Capture Event 1 from the DSS DSP Interrupt Map"
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newline
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hexmask.long.byte 0x20 0.--6. 1. "cap0,Select the DSS_RTIB Capture Event 0 from the DSS DSP Interrupt Map"
|
|
line.long 0x24 "DBG_ACK_CPU_CTRL,"
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bitfld.long 0x24 0. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals 0: DSP 1:MSS CR5" "0: DSP 1:MSS CR5,?"
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line.long 0x28 "DBG_ACK_CTL0,"
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bitfld.long 0x28 20.--22. "DSS_WDT,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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newline
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bitfld.long 0x28 16.--18. "DSS_SCIA,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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newline
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bitfld.long 0x28 12.--14. "DSS_RTIB,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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newline
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bitfld.long 0x28 8.--10. "DSS_RTIA,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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newline
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bitfld.long 0x28 4.--6. "DSS_DCCB,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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newline
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bitfld.long 0x28 0.--2. "DSS_DCCA,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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line.long 0x2C "DBG_ACK_CTL1,"
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bitfld.long 0x2C 28.--30. "DSS_HWA,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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newline
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bitfld.long 0x2C 24.--26. "DSS_MCRC,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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line.long 0x30 "DSS_DSP_INT_SEL,"
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bitfld.long 0x30 0.--2. "RCSS_CSI2_ICSSM,DSS DSP Interrupt selcet 0x0: CSI2 Interrupts are propagated to DSP 0x7 : ICSSM Interrupts are propagted to DSP" "0: CSI2 Interrupts are propagated to DSP 0x7 :..,?,?,?,?,?,?,?"
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line.long 0x34 "DSS_CBUFF_TRIGGER_SEL,"
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hexmask.long.byte 0x34 0.--6. 1. "sel,DSS CBUFF HW Trigger select from DSS DSP Interrupt Map. Reset value selects RSS_ADC_CAPTURE_COMPLETE as cbuff trigger"
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|
group.long 0x800++0x3
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|
line.long 0x0 "DSS_BUS_SAFETY_CTRL,"
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|
bitfld.long 0x0 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x804++0x7
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line.long 0x0 "DSS_BUS_SAFETY_SEC_ERR_STAT0,"
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bitfld.long 0x0 28. "DSS_MDO_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 27. "DSS_CBUFF_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 26. "DSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 25. "DSS_TPTC_C5_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 24. "DSS_TPTC_C4_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 23. "DSS_TPTC_C3_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 22. "DSS_TPTC_C2_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 21. "DSS_TPTC_C1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
|
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bitfld.long 0x0 20. "DSS_TPTC_C0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
|
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bitfld.long 0x0 19. "DSS_TPTC_B1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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newline
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bitfld.long 0x0 18. "DSS_TPTC_B0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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|
newline
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bitfld.long 0x0 17. "DSS_TPTC_A1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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|
newline
|
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bitfld.long 0x0 16. "DSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
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|
newline
|
|
bitfld.long 0x0 15. "DSS_TPTC_C5_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
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|
newline
|
|
bitfld.long 0x0 14. "DSS_TPTC_C4_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DSS_TPTC_C3_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
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|
newline
|
|
bitfld.long 0x0 12. "DSS_TPTC_C2_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "DSS_TPTC_C1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "DSS_TPTC_C0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DSS_TPTC_B1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DSS_TPTC_B0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DSS_TPTC_A1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DSS_DSP_SDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "DSS_L3_BANKD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSS_L3_BANKC,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DSS_L3_BANKB,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DSS_L3_BANKA,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DSS_DSP_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
line.long 0x4 "DSS_BUS_SAFETY_SEC_ERR_STAT1,"
|
|
bitfld.long 0x4 22. "RCSS2DSS,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DSS2RCSS,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "DSS_CMC_COMP,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DSS_CMC_UCOMP3,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "DSS_CMC_UCOMP2,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DSS_CMC_UCOMP1,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "DSS_CMC_UCOMP0,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DSS_MBOX,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DSS_CM4_S,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DSS_CM4_M,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DSS_HWA_DMA1,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DSS_HWA_DMA0,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DSS_MCRC,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
group.long 0x80C++0x7
|
|
line.long 0x0 "DSS_DSP_MDMA_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_DSP_MDMA_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "DSS_DSP_MDMA_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
rgroup.long ($2+0x818)++0x3
|
|
line.long 0x0 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_DATA$1,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat.end
|
|
rgroup.long 0x820++0xF
|
|
line.long 0x0 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x0 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0x4 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x830++0x7
|
|
line.long 0x0 "DSS_L3_BANKA_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_L3_BANKA_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x838++0x3
|
|
line.long 0x0 "DSS_L3_BANKA_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
rgroup.long ($2+0x83C)++0x3
|
|
line.long 0x0 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_DATA$1,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat.end
|
|
rgroup.long 0x844++0xF
|
|
line.long 0x0 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x0 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0x4 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x854++0x7
|
|
line.long 0x0 "DSS_L3_BANKB_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_L3_BANKB_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x85C++0x3
|
|
line.long 0x0 "DSS_L3_BANKB_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
rgroup.long ($2+0x860)++0x3
|
|
line.long 0x0 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_DATA$1,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat.end
|
|
rgroup.long 0x868++0xF
|
|
line.long 0x0 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x0 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0x4 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x878++0x7
|
|
line.long 0x0 "DSS_L3_BANKC_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_L3_BANKC_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x880++0x3
|
|
line.long 0x0 "DSS_L3_BANKC_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
rgroup.long ($2+0x884)++0x3
|
|
line.long 0x0 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_DATA$1,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat.end
|
|
rgroup.long 0x88C++0xF
|
|
line.long 0x0 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x0 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0x4 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x89C++0x7
|
|
line.long 0x0 "DSS_L3_BANKD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_L3_BANKD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x8A4++0x3
|
|
line.long 0x0 "DSS_L3_BANKD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
rgroup.long ($2+0x8A8)++0x3
|
|
line.long 0x0 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_DATA$1,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat.end
|
|
rgroup.long 0x8B0++0xF
|
|
line.long 0x0 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x0 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0x4 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x8C0++0x7
|
|
line.long 0x0 "DSS_DSP_SDMA_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_DSP_SDMA_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x8C8++0x17
|
|
line.long 0x0 "DSS_DSP_SDMA_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x8E0++0x7
|
|
line.long 0x0 "DSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_A0_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x8E8++0xF
|
|
line.long 0x0 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x8F8++0x7
|
|
line.long 0x0 "DSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_A1_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x900++0xF
|
|
line.long 0x0 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x910++0x7
|
|
line.long 0x0 "DSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_B0_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x918++0xF
|
|
line.long 0x0 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x928++0x7
|
|
line.long 0x0 "DSS_TPTC_B1_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_B1_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x930++0xF
|
|
line.long 0x0 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x940++0x7
|
|
line.long 0x0 "DSS_TPTC_C0_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C0_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x948++0xF
|
|
line.long 0x0 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x958++0x7
|
|
line.long 0x0 "DSS_TPTC_C1_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C1_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x960++0xF
|
|
line.long 0x0 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x970++0x7
|
|
line.long 0x0 "DSS_TPTC_C2_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C2_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x978++0xF
|
|
line.long 0x0 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x988++0x7
|
|
line.long 0x0 "DSS_TPTC_C3_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C3_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x990++0xF
|
|
line.long 0x0 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x9A0++0x7
|
|
line.long 0x0 "DSS_TPTC_C4_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C4_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x9A8++0xF
|
|
line.long 0x0 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x9B8++0x7
|
|
line.long 0x0 "DSS_TPTC_C5_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C5_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x9C0++0xF
|
|
line.long 0x0 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x9D0++0x7
|
|
line.long 0x0 "DSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_A0_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x9D8++0x13
|
|
line.long 0x0 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x9EC++0x7
|
|
line.long 0x0 "DSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_A1_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x9F4++0x13
|
|
line.long 0x0 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xA08++0x7
|
|
line.long 0x0 "DSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_B0_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xA10++0x13
|
|
line.long 0x0 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xA24++0x7
|
|
line.long 0x0 "DSS_TPTC_B1_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_B1_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xA2C++0x13
|
|
line.long 0x0 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xA40++0x7
|
|
line.long 0x0 "DSS_TPTC_C0_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C0_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xA48++0x13
|
|
line.long 0x0 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xA5C++0x7
|
|
line.long 0x0 "DSS_TPTC_C1_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C1_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xA64++0x13
|
|
line.long 0x0 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xA78++0x7
|
|
line.long 0x0 "DSS_TPTC_C2_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C2_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xA80++0x13
|
|
line.long 0x0 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xA94++0x7
|
|
line.long 0x0 "DSS_TPTC_C3_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C3_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xA9C++0x13
|
|
line.long 0x0 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xAB0++0x7
|
|
line.long 0x0 "DSS_TPTC_C4_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C4_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xAB8++0x13
|
|
line.long 0x0 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xACC++0x7
|
|
line.long 0x0 "DSS_TPTC_C5_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_TPTC_C5_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xAD4++0x13
|
|
line.long 0x0 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xAE8++0x7
|
|
line.long 0x0 "DSS_MDO_FIFO_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_MDO_FIFO_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xAF0++0x17
|
|
line.long 0x0 "DSS_MDO_FIFO_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xB08++0x7
|
|
line.long 0x0 "DSS_CBUFF_FIFO_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CBUFF_FIFO_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xB10++0x17
|
|
line.long 0x0 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xB28++0x7
|
|
line.long 0x0 "DSS_CMC_UCOMP0_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CMC_UCOMP0_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xB30++0x17
|
|
line.long 0x0 "DSS_CMC_UCOMP0_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CMC_UCOMP0_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CMC_UCOMP0_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CMC_UCOMP0_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CMC_UCOMP0_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CMC_UCOMP0_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xB48++0x7
|
|
line.long 0x0 "DSS_CMC_UCOMP1_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CMC_UCOMP1_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xB50++0x17
|
|
line.long 0x0 "DSS_CMC_UCOMP1_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CMC_UCOMP1_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CMC_UCOMP1_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CMC_UCOMP1_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CMC_UCOMP1_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CMC_UCOMP1_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xB68++0x7
|
|
line.long 0x0 "DSS_CMC_UCOMP2_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CMC_UCOMP2_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xB70++0x17
|
|
line.long 0x0 "DSS_CMC_UCOMP2_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CMC_UCOMP2_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CMC_UCOMP2_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CMC_UCOMP2_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CMC_UCOMP2_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CMC_UCOMP2_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xB88++0x7
|
|
line.long 0x0 "DSS_CMC_UCOMP3_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CMC_UCOMP3_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xB90++0x17
|
|
line.long 0x0 "DSS_CMC_UCOMP3_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CMC_UCOMP3_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CMC_UCOMP3_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CMC_UCOMP3_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CMC_UCOMP3_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CMC_UCOMP3_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xBA8++0x7
|
|
line.long 0x0 "DSS_CMC_COMP_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CMC_COMP_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xBB0++0x17
|
|
line.long 0x0 "DSS_CMC_COMP_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CMC_COMP_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CMC_COMP_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CMC_COMP_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CMC_COMP_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CMC_COMP_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xBC8++0x7
|
|
line.long 0x0 "DSS_MCRC_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_MCRC_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xBD0++0x17
|
|
line.long 0x0 "DSS_MCRC_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xBE8++0x7
|
|
line.long 0x0 "DSS_PCR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_PCR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xBF0++0x17
|
|
line.long 0x0 "DSS_PCR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xC08++0x7
|
|
line.long 0x0 "DSS_HWA_DMA0_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_HWA_DMA0_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xC10++0x17
|
|
line.long 0x0 "DSS_HWA_DMA0_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xC28++0x7
|
|
line.long 0x0 "DSS_HWA_DMA1_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_HWA_DMA1_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xC30++0x17
|
|
line.long 0x0 "DSS_HWA_DMA1_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xC48++0x7
|
|
line.long 0x0 "DSS_CM4_M_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CM4_M_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xC50++0x17
|
|
line.long 0x0 "DSS_CM4_M_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xC68++0x7
|
|
line.long 0x0 "DSS_CM4_S_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_CM4_S_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xC70++0x17
|
|
line.long 0x0 "DSS_CM4_S_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xC88++0x7
|
|
line.long 0x0 "DSS_MBOX_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_MBOX_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xC90++0x17
|
|
line.long 0x0 "DSS_MBOX_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "proc,Write pulse bit field: For bits 0 to 7: Wrting 1'b1 : Generates pulse interrupt to corresponding proc from DSP."
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "DSS_DCCA"
|
|
base ad:0x6F79C00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters clears the error signal"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DCCREV,Module version"
|
|
bitfld.long 0x0 30.--31. "SCHEME,SCHEME. - (RO )" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "NU1,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional release number - (RO )"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number - (RO )"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number. - (RO )"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU3,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU4,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU5,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"
|
|
line.long 0xC "DCCSTAT,Contains the error & done flag bit"
|
|
hexmask.long 0xC 2.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU7,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU8,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU9,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSSRC1,Clock source1 selection control"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x0 4.--11. 1. "NU10,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Refer to Design document section: 11.4.2 DCC"
|
|
line.long 0x4 "DCCCLKSSRC0,Clock source0 selection control"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU13,Reserved"
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x4 4.--11. 1. "NU12,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Refer to Design document section: 11.4.2 DCC"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DCCGCTRL2,Global control register 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "NU13,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FIFO_NONERR,FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_READ,FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CONT_ON_ERR,Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue.."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "DCCSTATUS2,FIFO status register"
|
|
hexmask.long 0x0 6.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full." "0: Count1 FIFO is not Full,1: Count1 FIFO is Full"
|
|
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full." "0: Valid0 FIFO is not Full,1: Valid0 FIFO is Full"
|
|
newline
|
|
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full." "0: Count0 FIFO is not Full,1: Count0 FIFO is Full"
|
|
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
|
|
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DCCERRCNT,Error count register"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU15,Reserved"
|
|
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
|
|
tree.end
|
|
tree "DSS_DCCB"
|
|
base ad:0x6F79D00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters clears the error signal"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DCCREV,Module version"
|
|
bitfld.long 0x0 30.--31. "SCHEME,SCHEME. - (RO )" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "NU1,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional release number - (RO )"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number - (RO )"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number. - (RO )"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU3,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU4,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU5,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"
|
|
line.long 0xC "DCCSTAT,Contains the error & done flag bit"
|
|
hexmask.long 0xC 2.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU7,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU8,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU9,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSSRC1,Clock source1 selection control"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x0 4.--11. 1. "NU10,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Refer to Design document section: 11.4.2 DCC"
|
|
line.long 0x4 "DCCCLKSSRC0,Clock source0 selection control"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU13,Reserved"
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x4 4.--11. 1. "NU12,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Refer to Design document section: 11.4.2 DCC"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DCCGCTRL2,Global control register 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "NU13,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FIFO_NONERR,FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_READ,FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CONT_ON_ERR,Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue.."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "DCCSTATUS2,FIFO status register"
|
|
hexmask.long 0x0 6.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full." "0: Count1 FIFO is not Full,1: Count1 FIFO is Full"
|
|
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full." "0: Valid0 FIFO is not Full,1: Valid0 FIFO is Full"
|
|
newline
|
|
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full." "0: Count0 FIFO is not Full,1: Count0 FIFO is Full"
|
|
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
|
|
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DCCERRCNT,Error count register"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU15,Reserved"
|
|
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
|
|
tree.end
|
|
tree "DSS_DSP_PBIST"
|
|
base ad:0x6F79000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "PBIST_A$1,Variable Address Register0"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "PBIST_L$1,Variable Loop Count Register L0"
|
|
repeat.end
|
|
group.long 0x120++0x7
|
|
line.long 0x0 "PBIST_DD10,DD0 Data Register 16 (D0)"
|
|
line.long 0x4 "PBIST_DE10,DE0 Data Register 16 (D0)"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x130)++0x3
|
|
line.long 0x0 "PBIST_CA$1,Constant Address Register0"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "PBIST_CL$1,Constant Loop Count Register0"
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
group.long ($2+0x150)++0x3
|
|
line.long 0x0 "PBIST_CI$1,Constant Increment Register0"
|
|
repeat.end
|
|
repeat 2. (list 0x2 0x3)(list 0x0 0x4)
|
|
group.word ($2+0x158)++0x1
|
|
line.word 0x0 "PBIST_CI$1,Constant Increment Register2"
|
|
hexmask.word 0x0 0.--15. 1. "PBIST_CI2,TI Internal Register.Reserved for HW RnD"
|
|
repeat.end
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
hexmask.long.byte 0x0 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
hexmask.long.byte 0x0 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
group.word 0x164++0x1
|
|
line.word 0x0 "PBIST_DLR,Datalogger 0"
|
|
hexmask.word.byte 0x0 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode. When in this mode ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config write to both this bit and bit [2] of the Datalogger Register.."
|
|
hexmask.word.byte 0x0 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM [3] : Do not change this bit from its default value of 1 [4] : Config.."
|
|
group.byte 0x168++0x0
|
|
line.byte 0x0 "PBIST_CMS,Clock mux select"
|
|
hexmask.byte 0x0 0.--3. 1. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
group.byte 0x16C++0x0
|
|
line.byte 0x0 "PBIST_PC,Program Control"
|
|
hexmask.byte 0x0 0.--4. 1. "PBIST_PC,TI Internal Register.Reserved for HW RnD"
|
|
repeat 2. (list 0x1 0x4)(list 0x0 0x4)
|
|
group.long ($2+0x170)++0x3
|
|
line.long 0x0 "PBIST_SCR$1,Address Scramble 0 -3"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
|
|
repeat.end
|
|
group.long 0x178++0x3
|
|
line.long 0x0 "PBIST_CS,Chip Select 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
|
|
group.byte 0x17C++0x0
|
|
line.byte 0x0 "PBIST_FDLY,Fail Delay"
|
|
hexmask.byte 0x0 0.--7. 1. "PBIST_FDLY,TI Internal Register.Reserved for HW RnD"
|
|
group.byte 0x180++0x0
|
|
line.byte 0x0 "PBIST_PACT,Pbist Active"
|
|
bitfld.byte 0x0 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used as the clock gate enable. As long as this bit is 0 any access to PBIST will not go.." "0: Disable internal PBIST clocks Value,1: Enable internal PBIST clocks"
|
|
group.byte 0x184++0x0
|
|
line.byte 0x0 "PBIST_ID,PBIST ID"
|
|
hexmask.byte 0x0 0.--4. 1. "PBIST_ID,PBIST ID. This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. The value of this register does not affect the functionality of the CPU interface."
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "PBIST_OVR,PBIST Overrides"
|
|
rgroup.byte 0x190++0x0
|
|
line.byte 0x0 "PBIST_FSFR0,Fail status fail - port 0"
|
|
bitfld.byte 0x0 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure" "0: No failure occurred Value,1: Indicates a failure"
|
|
rgroup.byte 0x194++0x0
|
|
line.byte 0x0 "PBIST_FSFR1,Fail status fail - port 1"
|
|
bitfld.byte 0x0 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure" "0: No failure occurred Value,1: Indicates a failure"
|
|
rgroup.byte 0x198++0x0
|
|
line.byte 0x0 "PBIST_FSRCR0,Fail Count fail - port 0"
|
|
hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test. The PBIST controller stops executing the memory self-test whenever a failure occurs in any memory instance for any of the.."
|
|
rgroup.byte 0x19C++0x0
|
|
line.byte 0x0 "PBIST_FSRCR1,Fail Count fail - port 1"
|
|
hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test. The PBIST controller stops executing the memory self-test whenever a failure occurs in any memory instance for any of the.."
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "PBIST_FSRA0,Fail status address - port 0"
|
|
rgroup.word 0x1A4++0x1
|
|
line.word 0x0 "PBIST_FSRA1,Fail status address - port 1"
|
|
hexmask.word 0x0 0.--15. 1. "PBIST_FSRA1,TI Internal Register.Reserved for HW RnD"
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x8)
|
|
rgroup.long ($2+0x1A8)++0x3
|
|
line.long 0x0 "PBIST_FSRDL$1,Fail status Data - port 0"
|
|
hexmask.long 0x0 0.--31. 1. "PBIST_FSRDL0,TI Internal Register.Reserved for HW RnD"
|
|
repeat.end
|
|
group.long 0x1B4++0xB
|
|
line.long 0x0 "PBIST_MARGIN,Margin Mode"
|
|
line.long 0x4 "PBIST_WRENZ,WRENZ"
|
|
line.long 0x8 "PBIST_PGS,PAGE/PGS"
|
|
group.byte 0x1C0++0x0
|
|
line.byte 0x0 "PBIST_ROM,Rom Mask"
|
|
bitfld.byte 0x0 0.--1. "PBIST_ROM,Rom Mask . This two-bit register sets appropriate ROM access modes for the PBIST controller. Value 0h = No information is used from ROM Value 1h = Only RAM Group information from ROM Vaule 2h = Only Algorithm information from ROM Value 3h =.." "0,1,2,3"
|
|
group.long 0x1C4++0xB
|
|
line.long 0x0 "PBIST_ALGO,ROM Algorithm Mask 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
hexmask.long.byte 0x0 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
hexmask.long.byte 0x0 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
line.long 0x4 "PBIST_RINFOL,RAM Info Mask Lower 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x4 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
line.long 0x8 "PBIST_RINFOU,RAM Info Mask Upper 0"
|
|
hexmask.long.byte 0x8 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x8 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x8 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x8 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
tree.end
|
|
tree "DSS_DSP_STC"
|
|
base ad:0x6F79200
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "STCGCR0,Self test Global control Reg0. *NOT BYTE ACCESSIBLE"
|
|
hexmask.long.word 0x0 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run. The selftest controller sends out 'complete' indication once it runs all of the.."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "NU0,Reserved bits"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock. This value is used to insert that many idle cycles in the Capture phase. Programmable idle cycles allow.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only). *NOT BYTE ACCESSIBLE Idle Cycles between scan_en going high to func_clk_en generation and scan_en going high to misr_log_en generation. This.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval. This bit.." "0: Continue NSTC run from previous interval,1: Restart NSTC run from ROM address 0 1X = Start..,?,?"
|
|
line.long 0x4 "STCGCR1,Self test Global control Reg1"
|
|
hexmask.long.tbyte 0x4 12.--31. 1. "NU2,Reserved bits"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test 0001 = Select CORE for selftest Other = CORE not selected."
|
|
newline
|
|
rbitfld.long 0x4 7. "NU3,Reserved bits" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode. 1 = Spread mode 0 = XOR mode" "0: XOR mode,1: Spread mode"
|
|
newline
|
|
bitfld.long 0x4 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration: 1 = Operates in Low Power Scan Mode. 0 = Operates in Normal Scan Mode." "0: Operates in Normal Scan Mode,1: Operates in Low Power Scan Mode"
|
|
newline
|
|
bitfld.long 0x4 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only) 1010 = Self test run enabled All values other than 1010 = Self test run disabled"
|
|
line.long 0x8 "STCTPR,Time out counter preload register"
|
|
hexmask.long 0x8 0.--31. 1. "TO_PRELOAD,Self test time out preload (RWP - Read Priviledge Mode Write only) This register contains the total number of STC clock cycles it will take before a self-test timeout error will be triggered after the initiation of the self-test run. This is.."
|
|
rgroup.long 0xC++0xF
|
|
line.long 0x0 "STC_CADDR,Current Address register for CORE1"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE1 This register reflects the current ROM address (for micro code load) accessed during selftest for CORE1 in of case segment0 and all the remaining segmentsn where n = 1 to 3)."
|
|
line.long 0x4 "STCCICR,Current Interval count register"
|
|
hexmask.long.word 0x4 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well. This field is applicable only for Segment 0."
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run."
|
|
line.long 0x8 "STCGSTAT,Global Status Register"
|
|
hexmask.long.tbyte 0x8 12.--31. 1. "NU4,Reserved bits"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "ST_ACTIVE,Tells whether self test is currently active or not. 1010 = Self test is active Others = SelfTest is not active Once the self-test completes and ST_ENA_B4 key is cleared this field will reflect the inactive value."
|
|
newline
|
|
hexmask.long.byte 0x8 2.--7. 1. "NU5,Reserved bits"
|
|
newline
|
|
bitfld.long 0x8 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode) 0 = Self test run has not failed 1 = SelfTest run has failed. Write Clear." "0: Self test run has not failed,1: SelfTest run has failed"
|
|
newline
|
|
bitfld.long 0x8 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode) 0 = Not completed 1 = SelfTest run Completed" "0: Not completed,1: SelfTest run Completed"
|
|
line.long 0xC "STCFSTAT,Fail Status Register"
|
|
hexmask.long 0xC 5.--31. 1. "NU6,Reserved bits"
|
|
newline
|
|
bitfld.long 0xC 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur. 00 = Failure on Segment 0 01 = Failure on Segment 1.." "0: Failure on Segment 0,1: Failure on Segment 1,?,?"
|
|
newline
|
|
bitfld.long 0xC 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode) 0 = No time out error occurred 1 = SelfTest run failed due to a timeout error" "0: No time out error occurred,1: SelfTest run failed due to a timeout error"
|
|
newline
|
|
bitfld.long 0xC 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode) 0 = No MISR mismatch for CORE2 1 = Self test run failed due to MISR mismatch for CORE2" "0: No MISR mismatch for CORE2,1: Self test run failed due to MISR mismatch for.."
|
|
newline
|
|
bitfld.long 0xC 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments. 0 = No MISR mismatch for CORE1 1 = Self test run failed due to MISR mismatch for CORE1" "0: No MISR mismatch for CORE1,1: Self test run failed due to MISR mismatch for.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "STCSCSCR,Signature compare Self Check Register"
|
|
hexmask.long 0x0 5.--31. 1. "NU7,Reserved bits"
|
|
newline
|
|
bitfld.long 0x0 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only) 0 = No fault insertion. 1 = Inserts fault in the logic unedr test which will make signature compare fail. This feature is used as diagnostic check of the STC IP." "0: No fault insertion,1: Inserts fault in the logic unedr test which will.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only) 1010 = Signature compare logic Self Check is enabled All values other than 1010 = Signature compare logic Self Check is disabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "STC_CADDR2,Current Address register for CORE2"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE2 This register reflects the current ROM address(for micro code load) accessed during selftest for CORE2 in of case segment0."
|
|
group.long 0x24++0x17
|
|
line.long 0x0 "STC_CLKDIV,Clock Divider Register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "NU8,Reserved bits"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
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|
newline
|
|
hexmask.long.byte 0x0 19.--23. 1. "NU9,Reserved bits"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
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|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "NU10,Reserved bits"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
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|
newline
|
|
hexmask.long.byte 0x0 3.--7. 1. "NU11,Reserved bits"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "STC_SEGPLR,Segment 1st interval Preload Register"
|
|
hexmask.long 0x4 2.--31. 1. "NU12,Reserved bits"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter. The 1st address of each.." "0: Preload the address of the 1st interval of..,1: Preload the address of the 1st interval of..,?,?"
|
|
line.long 0x8 "SEG0_START_ADDR,ROM Start address for Segment0"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU13,Reserved bits"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
|
|
line.long 0xC "SEG1_START_ADDR,ROM Start address for Segment1"
|
|
hexmask.long.word 0xC 20.--31. 1. "NU14,Reserved bits"
|
|
newline
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
|
|
line.long 0x10 "SEG2_START_ADDR,ROM Start address for Segment2"
|
|
hexmask.long.word 0x10 20.--31. 1. "NU15,Reserved bits"
|
|
newline
|
|
hexmask.long.tbyte 0x10 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
|
|
line.long 0x14 "SEG3_START_ADDR,ROM Start address for Segment3"
|
|
hexmask.long.word 0x14 20.--31. 1. "NU16,Reserved bits"
|
|
newline
|
|
hexmask.long.tbyte 0x14 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
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|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
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|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "CORE1_CURMISR_$1,Holds the MISR signature for CORE1"
|
|
hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1 This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.."
|
|
repeat.end
|
|
repeat 12. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C)
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "CORE1_CURMISR_$1,Holds the MISR signature for CORE1"
|
|
hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1 This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.."
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0xAC)++0x3
|
|
line.long 0x0 "CORE2_CURMISR_$1,Holds the MISR signature for CORE2"
|
|
hexmask.long 0x0 0.--31. 1. "C2MISR0,MISR Signature for CORE2 This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.."
|
|
repeat.end
|
|
repeat 12. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C)
|
|
rgroup.long ($2+0xAC)++0x3
|
|
line.long 0x0 "CORE2_CURMISR_$1,Holds the MISR signature for CORE2"
|
|
hexmask.long 0x0 0.--31. 1. "C2MISR0,MISR Signature for CORE2 This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.."
|
|
repeat.end
|
|
tree.end
|
|
tree "DSS_ECC_AGG"
|
|
base ad:0x60A0000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "rev,Revision parameters"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "module_id,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL version"
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|
bitfld.long 0x0 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "custom,Custom version" "0,1,2,3"
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|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor version"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "vector,ECC Vector Register"
|
|
rbitfld.long 0x0 24. "rd_svbus_done,Status to indicate if read on serial VBUS is complete" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "rd_svbus_address,Read address"
|
|
bitfld.long 0x0 15. "rd_svbus,Write 1 to trigger a read on the serial VBUS" "0,1"
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|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ecc_vector,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "stat,Misc Status"
|
|
hexmask.long.word 0x0 0.--10. 1. "num_rams,Indicates the number of RAMS serviced by the ECC aggregator"
|
|
line.long 0x4 "wrap_rev,Revision parameters"
|
|
bitfld.long 0x4 30.--31. "scheme,Scheme" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x4 16.--27. 1. "module_id,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x4 11.--15. 1. "revrtl,RTL version"
|
|
bitfld.long 0x4 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "custom,Custom version" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "revmin,Minor version"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "ctrl,ECC Control Register"
|
|
bitfld.long 0x0 8. "check_svbus_timeout,check for svbus timeout errors" "0,1"
|
|
bitfld.long 0x0 7. "check_parity,check for parity errors" "0,1"
|
|
bitfld.long 0x0 6. "error_once,Force Error only once" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "force_n_row,Force Error on any RAM read" "0,1"
|
|
bitfld.long 0x0 4. "force_ded,Force Double Bit Error" "0,1"
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|
bitfld.long 0x0 3. "force_sec,Force Single Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "enable_rmw,Enable rmw" "0,1"
|
|
bitfld.long 0x0 1. "ecc_check,Enable ECC check" "0,1"
|
|
bitfld.long 0x0 0. "ecc_enable,Enable ECC" "0,1"
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|
line.long 0x4 "err_ctrl1,ECC Error Control1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "ecc_row,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
|
|
line.long 0x8 "err_ctrl2,ECC Error Control2 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ecc_bit2,Data bit that needs to be flipped if double bit error needs to be forced"
|
|
hexmask.long.word 0x8 0.--15. 1. "ecc_bit1,Data bit that needs to be flipped when force_sec is set"
|
|
line.long 0xC "err_stat1,ECC Error Status1 Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ecc_bit1,Data bit that corresponds to the single-bit error"
|
|
bitfld.long 0xC 15. "clr_ctrl_reg_err,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
|
|
bitfld.long 0xC 13.--14. "clr_ctrl_reg_err,Clear parity Error Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 12. "clr_ecc_other,Clear other Error Status" "0,1"
|
|
bitfld.long 0xC 10.--11. "clr_ecc_ded,Clear Double Bit Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "clr_ecc_sec,Clear Single Bit Error Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 7. "ctr_reg_err,control register error pending Level interrupt" "0,1"
|
|
bitfld.long 0xC 5.--6. "parity_err,Level parity error Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 4. "ecc_other,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "ecc_ded,Level Double Bit Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "ecc_sec,Level Single Bit Error Status" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "err_stat2,ECC Error Status2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ecc_row,Row address where the single or double-bit error has occurred"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "err_stat3,ECC Error Status3 Register"
|
|
bitfld.long 0x0 9. "clr_svbus_timeout_err,Clear svbus timeout Error Status" "0,1"
|
|
bitfld.long 0x0 1. "svbus_timeout_err,Level svbus timeout error Error Status" "0,1"
|
|
rbitfld.long 0x0 0. "wb_pend,delayed write back pending Status" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "sec_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
|
|
line.long 0x4 "sec_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 22. "rcss_tptc_b1_pend,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x4 21. "rcss_tptc_b0_pend,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
|
|
bitfld.long 0x4 20. "rcss_tptc_a1_pend,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "rcss_tptc_a0_pend,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x4 18. "dss_tptc_c5_pend,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
|
|
bitfld.long 0x4 17. "dss_tptc_c4_pend,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "dss_tptc_c3_pend,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
|
|
bitfld.long 0x4 15. "dss_tptc_c2_pend,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
|
|
bitfld.long 0x4 14. "dss_tptc_c1_pend,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "dss_tptc_c0_pend,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
|
|
bitfld.long 0x4 12. "dss_tptc_b1_pend,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x4 11. "dss_tptc_b0_pend,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "dss_tptc_a1_pend,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
|
|
bitfld.long 0x4 9. "dss_tptc_a0_pend,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x4 8. "hwacm4_mailbox_pend,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hwacm4_ram_b2_pend,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
|
|
bitfld.long 0x4 6. "hwacm4_ram_b1_pend,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
|
|
bitfld.long 0x4 5. "hwacm4_ram_b0_pend,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "dss_mailbox_pend,Interrupt Pending Status for dss_mailbox_pend" "0,1"
|
|
bitfld.long 0x4 3. "dss_l3ram3_pend,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
|
|
bitfld.long 0x4 2. "dss_l3ram2_pend,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "dss_l3ram1_pend,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
|
|
bitfld.long 0x4 0. "dss_l3ram0_pend,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 22. "rcss_tptc_b1_enable_set,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 21. "rcss_tptc_b0_enable_set,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 20. "rcss_tptc_a1_enable_set,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "rcss_tptc_a0_enable_set,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 18. "dss_tptc_c5_enable_set,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
|
|
bitfld.long 0x0 17. "dss_tptc_c4_enable_set,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "dss_tptc_c3_enable_set,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
|
|
bitfld.long 0x0 15. "dss_tptc_c2_enable_set,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
|
|
bitfld.long 0x0 14. "dss_tptc_c1_enable_set,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "dss_tptc_c0_enable_set,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
|
|
bitfld.long 0x0 12. "dss_tptc_b1_enable_set,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 11. "dss_tptc_b0_enable_set,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "dss_tptc_a1_enable_set,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 9. "dss_tptc_a0_enable_set,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 8. "hwacm4_mailbox_enable_set,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "hwacm4_ram_b2_enable_set,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
|
|
bitfld.long 0x0 6. "hwacm4_ram_b1_enable_set,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
|
|
bitfld.long 0x0 5. "hwacm4_ram_b0_enable_set,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dss_mailbox_enable_set,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
|
|
bitfld.long 0x0 3. "dss_l3ram3_enable_set,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "dss_l3ram2_enable_set,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "dss_l3ram1_enable_set,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
|
|
bitfld.long 0x0 0. "dss_l3ram0_enable_set,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 22. "rcss_tptc_b1_enable_clr,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 21. "rcss_tptc_b0_enable_crl,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 20. "rcss_tptc_a1_enable_crl,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "rcss_tptc_a0_enable_crl,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 18. "dss_tptc_c5_enable_crl,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
|
|
bitfld.long 0x0 17. "dss_tptc_c4_enable_crl,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "dss_tptc_c3_enable_crl,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
|
|
bitfld.long 0x0 15. "dss_tptc_c2_enable_crl,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
|
|
bitfld.long 0x0 14. "dss_tptc_c1_enable_crl,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "dss_tptc_c0_enable_crl,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
|
|
bitfld.long 0x0 12. "dss_tptc_b1_enable_crl,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 11. "dss_tptc_b0_enable_crl,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "dss_tptc_a1_enable_crl,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 9. "dss_tptc_a0_enable_crl,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 8. "hwacm4_mailbox_enable_crl,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "hwacm4_ram_b2_enable_crl,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
|
|
bitfld.long 0x0 6. "hwacm4_ram_b1_enable_crl,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
|
|
bitfld.long 0x0 5. "hwacm4_ram_b0_enable_crl,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dss_mailbox_enable_crl,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
|
|
bitfld.long 0x0 3. "dss_l3ram3_enable_crl,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "dss_l3ram2_enable_crl,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "dss_l3ram1_enable_crl,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
|
|
bitfld.long 0x0 0. "dss_l3ram0_enable_crl,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
|
|
group.long 0x13C++0x7
|
|
line.long 0x0 "ded_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
|
|
line.long 0x4 "ded_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 22. "rcss_tptc_b1_pend,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x4 21. "rcss_tptc_b0_pend,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
|
|
bitfld.long 0x4 20. "rcss_tptc_a1_pend,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "rcss_tptc_a0_pend,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x4 18. "dss_tptc_c5_pend,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
|
|
bitfld.long 0x4 17. "dss_tptc_c4_pend,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "dss_tptc_c3_pend,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
|
|
bitfld.long 0x4 15. "dss_tptc_c2_pend,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
|
|
bitfld.long 0x4 14. "dss_tptc_c1_pend,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "dss_tptc_c0_pend,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
|
|
bitfld.long 0x4 12. "dss_tptc_b1_pend,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x4 11. "dss_tptc_b0_pend,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "dss_tptc_a1_pend,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
|
|
bitfld.long 0x4 9. "dss_tptc_a0_pend,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x4 8. "hwacm4_mailbox_pend,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hwacm4_ram_b2_pend,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
|
|
bitfld.long 0x4 6. "hwacm4_ram_b1_pend,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
|
|
bitfld.long 0x4 5. "hwacm4_ram_b0_pend,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "dss_mailbox_pend,Interrupt Pending Status for dss_mailbox_pend" "0,1"
|
|
bitfld.long 0x4 3. "dss_l3ram3_pend,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
|
|
bitfld.long 0x4 2. "dss_l3ram2_pend,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "dss_l3ram1_pend,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
|
|
bitfld.long 0x4 0. "dss_l3ram0_pend,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 22. "rcss_tptc_b1_enable_set,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 21. "rcss_tptc_b0_enable_set,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 20. "rcss_tptc_a1_enable_set,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "rcss_tptc_a0_enable_set,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 18. "dss_tptc_c5_enable_set,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
|
|
bitfld.long 0x0 17. "dss_tptc_c4_enable_set,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "dss_tptc_c3_enable_set,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
|
|
bitfld.long 0x0 15. "dss_tptc_c2_enable_set,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
|
|
bitfld.long 0x0 14. "dss_tptc_c1_enable_set,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "dss_tptc_c0_enable_set,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
|
|
bitfld.long 0x0 12. "dss_tptc_b1_enable_set,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 11. "dss_tptc_b0_enable_set,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "dss_tptc_a1_enable_set,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 9. "dss_tptc_a0_enable_set,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 8. "hwacm4_mailbox_enable_set,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "hwacm4_ram_b2_enable_set,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
|
|
bitfld.long 0x0 6. "hwacm4_ram_b1_enable_set,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
|
|
bitfld.long 0x0 5. "hwacm4_ram_b0_enable_set,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dss_mailbox_enable_set,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
|
|
bitfld.long 0x0 3. "dss_l3ram3_enable_set,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "dss_l3ram2_enable_set,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "dss_l3ram1_enable_set,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
|
|
bitfld.long 0x0 0. "dss_l3ram0_enable_set,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 22. "rcss_tptc_b1_enable_clr,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 21. "rcss_tptc_b0_enable_crl,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 20. "rcss_tptc_a1_enable_crl,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "rcss_tptc_a0_enable_crl,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 18. "dss_tptc_c5_enable_crl,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
|
|
bitfld.long 0x0 17. "dss_tptc_c4_enable_crl,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "dss_tptc_c3_enable_crl,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
|
|
bitfld.long 0x0 15. "dss_tptc_c2_enable_crl,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
|
|
bitfld.long 0x0 14. "dss_tptc_c1_enable_crl,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "dss_tptc_c0_enable_crl,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
|
|
bitfld.long 0x0 12. "dss_tptc_b1_enable_crl,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
|
|
bitfld.long 0x0 11. "dss_tptc_b0_enable_crl,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "dss_tptc_a1_enable_crl,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 9. "dss_tptc_a0_enable_crl,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 8. "hwacm4_mailbox_enable_crl,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "hwacm4_ram_b2_enable_crl,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
|
|
bitfld.long 0x0 6. "hwacm4_ram_b1_enable_crl,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
|
|
bitfld.long 0x0 5. "hwacm4_ram_b0_enable_crl,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dss_mailbox_enable_crl,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
|
|
bitfld.long 0x0 3. "dss_l3ram3_enable_crl,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "dss_l3ram2_enable_crl,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "dss_l3ram1_enable_crl,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
|
|
bitfld.long 0x0 0. "dss_l3ram0_enable_crl,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "aggr_enable_set,AGGR interrupt enable set Register"
|
|
bitfld.long 0x0 1. "timeout,interrupt enable set for svbus timeout errors" "0,1"
|
|
bitfld.long 0x0 0. "parity,interrupt enable set for parity errors" "0,1"
|
|
line.long 0x4 "aggr_enable_clr,AGGR interrupt enable clear Register"
|
|
bitfld.long 0x4 1. "timeout,interrupt enable clear for svbus timeout errors" "0,1"
|
|
bitfld.long 0x4 0. "parity,interrupt enable clear for parity errors" "0,1"
|
|
line.long 0x8 "aggr_status_set,AGGR interrupt status set Register"
|
|
bitfld.long 0x8 2.--3. "timeout,interrupt status set for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "parity,interrupt status set for parity errors" "0,1,2,3"
|
|
line.long 0xC "aggr_status_clr,AGGR interrupt status clear Register"
|
|
bitfld.long 0xC 2.--3. "timeout,interrupt status clear for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "parity,interrupt status clear for parity errors" "0,1,2,3"
|
|
tree.end
|
|
tree "DSS_ESM"
|
|
base ad:0x6F7D000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
|
|
hexmask.long 0x0 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1.."
|
|
line.long 0x4 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
|
|
hexmask.long 0x4 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1.."
|
|
line.long 0x8 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
|
|
hexmask.long 0x8 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0xC "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
|
|
hexmask.long 0xC 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
|
|
hexmask.long 0x10 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register.."
|
|
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
|
|
hexmask.long 0x14 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register.."
|
|
repeat 4. (list 0x1 0x4 0x7 0xA)(list 0x0 0x40 0x80 0xC0)
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "ESMSR$1,ESM Status Register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ESF,Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt.."
|
|
repeat.end
|
|
group.long 0x1C++0x3B
|
|
line.long 0x0 "ESMSR2,ESM Status Register 2"
|
|
hexmask.long 0x0 0.--31. 1. "ESF,Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt.."
|
|
line.long 0x4 "ESMSR3,ESM Status Register 3"
|
|
hexmask.long 0x4 0.--31. 1. "ESF,Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."
|
|
line.long 0x8 "ESMEPSR,ESM ERROR Pin Status Register"
|
|
hexmask.long 0x8 1.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
bitfld.long 0x8 0. "EPSF,ERROR Pin Status Flag. Provides status information for the ERROR Pin. Read/Write in User and Privileged mode. 0 Read: ERROR Pin is low (active) if any error has occurred. Write: Writes have no effect. 1 Read: ERROR Pin is high if no error has.." "0,1"
|
|
line.long 0xC "ESMIOFFHR,ESM Interrupt Offset High Register"
|
|
hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.word 0xC 0.--8. 1. "INTOFFH,Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts of error Group1. Inside a group channel.."
|
|
line.long 0x10 "ESMIOFFLR,ESM Interrupt Offset Low Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.byte 0x10 0.--7. 1. "INTOFFL,Offset Low Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the low level interrupt line. Inside a group channel 0 has highest priority and channel 31 has lowest priority. User and privileged.."
|
|
line.long 0x14 "ESMLTCR,ESM Low-Time Counter Register"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.word 0x14 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin. The low-time counter is triggered by the peripheral clock (VCLK). Note: Low time counter is set to the default preload value of the ESMLTCPR in the.."
|
|
line.long 0x18 "ESMLTCPR,ESM Low-Time Counter Preload Register"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.word 0x18 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write)."
|
|
line.long 0x1C "ESMEKR,ESM Error Key Register"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.byte 0x1C 0.--3. 1. "EKEY,Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. User and privileged mode (read): Returns current value of the EKEY. Privileged mode (write): 0 Activates normal mode (recommended default mode). Ah Forces error on.."
|
|
line.long 0x20 "ESMSSR2,ESM Status Shadow Register 2"
|
|
hexmask.long 0x20 0.--31. 1. "ESF,Error Status Flag. Shadow register for status information on pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."
|
|
line.long 0x24 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
|
|
hexmask.long 0x24 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4.."
|
|
line.long 0x28 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
|
|
hexmask.long 0x28 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4.."
|
|
line.long 0x2C "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
|
|
hexmask.long 0x2C 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x30 "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
|
|
hexmask.long 0x30 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x34 "ESMILSR4,Interrupt Level Set/Status Register 4"
|
|
hexmask.long 0x34 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register.."
|
|
line.long 0x38 "ESMILCR4,Interrupt Level Clear/Status Register 4"
|
|
hexmask.long 0x38 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register.."
|
|
group.long 0x80++0x17
|
|
line.long 0x0 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
|
|
hexmask.long 0x0 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7.."
|
|
line.long 0x4 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
|
|
hexmask.long 0x4 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR7.."
|
|
line.long 0x8 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
|
|
hexmask.long 0x8 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0xC "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
|
|
hexmask.long 0xC 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR7 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
|
|
hexmask.long 0x10 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register.."
|
|
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
|
|
hexmask.long 0x14 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register.."
|
|
group.long 0xC0++0x17
|
|
line.long 0x0 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
|
|
hexmask.long 0x0 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR10.."
|
|
line.long 0x4 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
|
|
hexmask.long 0x4 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR10.."
|
|
line.long 0x8 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
|
|
hexmask.long 0x8 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR10 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0xC "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
|
|
hexmask.long 0xC 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR10 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
|
|
hexmask.long 0x10 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR10 register.."
|
|
line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
|
|
hexmask.long 0x14 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR10 register.."
|
|
tree.end
|
|
tree "DSS_HWA_CFG"
|
|
base ad:0x6062000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
group.long 0x4++0x1F
|
|
line.long 0x0 "PARAM_RAM_IDX,"
|
|
hexmask.long.word 0x0 16.--25. 1. "PARAM_END_IDX,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "PARAM_START_IDX,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by.."
|
|
line.long 0x4 "PARAM_RAM_LOOP,"
|
|
hexmask.long.word 0x4 0.--11. 1. "NUMLOOPS,Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them. The maximum number of times the loop can be made is run.."
|
|
line.long 0x8 "PARAM_RAM_IDX_ALT,"
|
|
hexmask.long.word 0x8 16.--25. 1. "PARAM_END_IDX,PARAM_END_IDX for alternate thread"
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "PARAM_START_IDX,PARAM_START_IDX for alternate thread"
|
|
line.long 0xC "PARAM_RAM_LOOP_ALT,"
|
|
hexmask.long.word 0xC 0.--11. 1. "NUMLOOPS,NUMLOOPS for alternate thread"
|
|
line.long 0x10 "PREVIOUS_NAME,"
|
|
bitfld.long 0x10 24. "hwa_dyn_clk_en,Dynamic Clock-gating Control: Setting this register bit to '1' enables the capability to clock gate the 4 Radar Accelerator core IPs (FFT datapath CFAR Memory compression Local Maxima) based on the ParamSet being executed." "0,1"
|
|
newline
|
|
bitfld.long 0x10 16.--18. "hwa_reset,Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator. The assertion of these register bits by the main processor will bring the Accelerator Engine to a known reset state. This is mostly.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 8.--10. "hwa_clk_en,Clock-gating Control: This register controls the enable/disable for the clock of the Radar Accelerator. This register bit can be set to 0 to clock-gate the accelerator when not using the accelerator. Before enabling the accelerator or before.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 0.--2. "hwa_en,Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state. A 000b to 111b transition is expected to trigger a new Paramset execution" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CS_CONFIG,"
|
|
hexmask.long.byte 0x14 16.--20. 1. "CS_TRGSRC,In case of DMA trigger this specifies which DMA channel (which bit in DMA2HWA_TRIG register) to wait for In case of HW-based trigger this specifies which CSI2 trigger signal (out of the 20 possible trigger signals) to wait for"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "CS_TRIGMODE,Trigger mode for context switching 0011b: DMA-based trigger (used in conjunction with DMA2HWA_TRIGGER and CS_TRIGSRC registers described below) 0100b: Hardware based trigger (used in conjunction with CS_TRIGSRC) Valid programmation 0-19 .."
|
|
newline
|
|
bitfld.long 0x14 0. "CS_ENABLE,Master enable for the Conxtext switching feature.Setting this bit will allow context switching to ALT thread if it is enabled in the Param set" "0,1"
|
|
line.long 0x18 "FW2DMA_TRIG,"
|
|
hexmask.long 0x18 0.--31. 1. "FW2DMA_TRIGGER,SW Override for HWA Trigger to DMA by the CPU It s a Self clearing bit"
|
|
line.long 0x1C "DMA2HWA_TRIG,"
|
|
hexmask.long 0x1C 0.--31. 1. "DMA2HWA_TRIGGER,DMA trigger register: This register is relevant whenever DMA triggered mode is used (i.e. TRIGMODE = 011b). Whenever a DMA channel has finished copying input samples into the local memory of the accelerator and wants to trigger the.."
|
|
rgroup.long 0x24++0x7F
|
|
line.long 0x0 "SIGDMACH0DONE,"
|
|
hexmask.long 0x0 0.--31. 1. "SIGDMACH0DONE,Signature for DMA channel 0 completion : 0x0000_0001 Linked DMA can copy from one of these SIG_DMACHx_DONE registers into DMA2HWA_TRIGGER register to set the appropriate register bit to signal the completion of DMA and trigger the.."
|
|
line.long 0x4 "SIGDMACH1DONE,"
|
|
hexmask.long 0x4 0.--31. 1. "SIGDMACH1DONE,Signature for DMA channel 1 completion : 0x0000_0002"
|
|
line.long 0x8 "SIGDMACH2DONE,"
|
|
hexmask.long 0x8 0.--31. 1. "SIGDMACH2DONE,Signature for DMA channel 2 completion : 0x0000_0004"
|
|
line.long 0xC "SIGDMACH3DONE,"
|
|
hexmask.long 0xC 0.--31. 1. "SIGDMACH3DONE,Signature for DMA channel 3 completion : 0x0000_0008"
|
|
line.long 0x10 "SIGDMACH4DONE,"
|
|
hexmask.long 0x10 0.--31. 1. "SIGDMACH4DONE,Signature for DMA channel 4 completion : 0x0000_0010"
|
|
line.long 0x14 "SIGDMACH5DONE,"
|
|
hexmask.long 0x14 0.--31. 1. "SIGDMACH5DONE,Signature for DMA channel 5 completion : 0x0000_0020"
|
|
line.long 0x18 "SIGDMACH6DONE,"
|
|
hexmask.long 0x18 0.--31. 1. "SIGDMACH6DONE,Signature for DMA channel 6 completion : 0x0000_0040"
|
|
line.long 0x1C "SIGDMACH7DONE,"
|
|
hexmask.long 0x1C 0.--31. 1. "SIGDMACH7DONE,Signature for DMA channel 7 completion : 0x0000_0080"
|
|
line.long 0x20 "SIGDMACH8DONE,"
|
|
hexmask.long 0x20 0.--31. 1. "SIGDMACH8DONE,Signature for DMA channel 8 completion : 0x0000_0100"
|
|
line.long 0x24 "SIGDMACH9DONE,"
|
|
hexmask.long 0x24 0.--31. 1. "SIGDMACH9DONE,Signature for DMA channel 9 completion : 0x0000_0200"
|
|
line.long 0x28 "SIGDMACH10DONE,"
|
|
hexmask.long 0x28 0.--31. 1. "SIGDMACH10DONE,Signature for DMA channel 10 completion : 0x0000_0400"
|
|
line.long 0x2C "SIGDMACH11DONE,"
|
|
hexmask.long 0x2C 0.--31. 1. "SIGDMACH11DONE,Signature for DMA channel 11 completion : 0x0000_0800"
|
|
line.long 0x30 "SIGDMACH12DONE,"
|
|
hexmask.long 0x30 0.--31. 1. "SIGDMACH12DONE,Signature for DMA channel 12 completion : 0x0000_1000"
|
|
line.long 0x34 "SIGDMACH13DONE,"
|
|
hexmask.long 0x34 0.--31. 1. "SIGDMACH13DONE,Signature for DMA channel 13 completion : 0x0000_2000"
|
|
line.long 0x38 "SIGDMACH14DONE,"
|
|
hexmask.long 0x38 0.--31. 1. "SIGDMACH14DONE,Signature for DMA channel 14 completion : 0x0000_4000"
|
|
line.long 0x3C "SIGDMACH15DONE,"
|
|
hexmask.long 0x3C 0.--31. 1. "SIGDMACH15DONE,Signature for DMA channel 15 completion : 0x0000_8000"
|
|
line.long 0x40 "SIGDMACH16DONE,"
|
|
hexmask.long 0x40 0.--31. 1. "SIGDMACH16DONE,Signature for DMA channel 16 completion : 0x0001_0000"
|
|
line.long 0x44 "SIGDMACH17DONE,"
|
|
hexmask.long 0x44 0.--31. 1. "SIGDMACH17DONE,Signature for DMA channel 17 completion : 0x0002_0000"
|
|
line.long 0x48 "SIGDMACH18DONE,"
|
|
hexmask.long 0x48 0.--31. 1. "SIGDMACH18DONE,Signature for DMA channel 18 completion : 0x0004_0000"
|
|
line.long 0x4C "SIGDMACH19DONE,"
|
|
hexmask.long 0x4C 0.--31. 1. "SIGDMACH19DONE,Signature for DMA channel 19 completion : 0x0008_0000"
|
|
line.long 0x50 "SIGDMACH20DONE,"
|
|
hexmask.long 0x50 0.--31. 1. "SIGDMACH20DONE,Signature for DMA channel 20 completion : 0x0010_0000"
|
|
line.long 0x54 "SIGDMACH21DONE,"
|
|
hexmask.long 0x54 0.--31. 1. "SIGDMACH21DONE,Signature for DMA channel 21 completion : 0x0020_0000"
|
|
line.long 0x58 "SIGDMACH22DONE,"
|
|
hexmask.long 0x58 0.--31. 1. "SIGDMACH22DONE,Signature for DMA channel 22 completion : 0x0040_0000"
|
|
line.long 0x5C "SIGDMACH23DONE,"
|
|
hexmask.long 0x5C 0.--31. 1. "SIGDMACH23DONE,Signature for DMA channel 23 completion : 0x0080_0000"
|
|
line.long 0x60 "SIGDMACH24DONE,"
|
|
hexmask.long 0x60 0.--31. 1. "SIGDMACH24DONE,Signature for DMA channel 24 completion : 0x0100_0000"
|
|
line.long 0x64 "SIGDMACH25DONE,"
|
|
hexmask.long 0x64 0.--31. 1. "SIGDMACH25DONE,Signature for DMA channel 25 completion : 0x0200_0000"
|
|
line.long 0x68 "SIGDMACH26DONE,"
|
|
hexmask.long 0x68 0.--31. 1. "SIGDMACH26DONE,Signature for DMA channel 26 completion : 0x0400_0000"
|
|
line.long 0x6C "SIGDMACH27DONE,"
|
|
hexmask.long 0x6C 0.--31. 1. "SIGDMACH27DONE,Signature for DMA channel 27 completion : 0x0800_0000"
|
|
line.long 0x70 "SIGDMACH28DONE,"
|
|
hexmask.long 0x70 0.--31. 1. "SIGDMACH28DONE,Signature for DMA channel 28 completion : 0x1000_0000"
|
|
line.long 0x74 "SIGDMACH29DONE,"
|
|
hexmask.long 0x74 0.--31. 1. "SIGDMACH29DONE,Signature for DMA channel 29 completion : 0x2000_0000"
|
|
line.long 0x78 "SIGDMACH30DONE,"
|
|
hexmask.long 0x78 0.--31. 1. "SIGDMACH30DONE,Signature for DMA channel 30 completion : 0x4000_0000"
|
|
line.long 0x7C "SIGDMACH31DONE,"
|
|
hexmask.long 0x7C 0.--31. 1. "SIGDMACH31DONE,Signature for DMA channel 31 completion : 0x8000_0000"
|
|
group.long 0xA4++0x2F
|
|
line.long 0x0 "FW2HWA_TRIG_0,"
|
|
bitfld.long 0x0 0. "FW2HWA_TRIGGER_0,Software trigger bit 0: This register bit is relevant whenever software triggered mode is used (i.e. TRIGMODE = 001b). The main processor software can set this register bit so that the State Machine gets triggered and starts the.." "0: This register bit is relevant whenever software..,?"
|
|
line.long 0x4 "FW2HWA_TRIG_1,"
|
|
bitfld.long 0x4 0. "FW2HWA_TRIGGER_1,Software trigger bit 1: This register bit is relevant whenever software triggered mode is used (i.e. TRIGMODE = 111b). The main processor software can set this register bit so that the State Machine gets triggered and starts the.." "?,1: This register bit is relevant whenever software.."
|
|
line.long 0x8 "CS_FW2ACC_TRIG,"
|
|
bitfld.long 0x8 0. "FW2HWA_TRIGGER_CS,CPU can set this register bit to trigger a context switch when CS_TRIGMODE = 101b It s a Self clearing bit" "0,1"
|
|
line.long 0xC "BPM_PATTERN_0,"
|
|
hexmask.long 0xC 0.--31. 1. "BPM_PATTERN_0,BPM pattern [31:0]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x10 "BPM_PATTERN_1,"
|
|
hexmask.long 0x10 0.--31. 1. "BPM_PATTERN_1,BPM pattern [63:32]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x14 "BPM_PATTERN_2,"
|
|
hexmask.long 0x14 0.--31. 1. "BPM_PATTERN_2,BPM pattern [95:64]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x18 "BPM_PATTERN_3,"
|
|
hexmask.long 0x18 0.--31. 1. "BPM_PATTERN_3,BPM pattern [127:96]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x1C "BPM_PATTERN_4,"
|
|
hexmask.long 0x1C 0.--31. 1. "BPM_PATTERN_4,BPM pattern [159:128]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x20 "BPM_PATTERN_5,"
|
|
hexmask.long 0x20 0.--31. 1. "BPM_PATTERN_5,BPM pattern [191:160]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x24 "BPM_PATTERN_6,"
|
|
hexmask.long 0x24 0.--31. 1. "BPM_PATTERN_6,BPM pattern [223:192]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x28 "BPM_PATTERN_7,"
|
|
hexmask.long 0x28 0.--31. 1. "BPM_PATTERN_7,BPM pattern[255:224]: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled"
|
|
line.long 0x2C "BPM_RATE,"
|
|
hexmask.long.word 0x2C 0.--9. 1. "BPM_RATE,BPM rate: Specifies the number of input samples corresponding to each BPM bit. Minimum valid value for this register is 1."
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "PARAM_DONE_SET_STATUS_0,"
|
|
hexmask.long 0x0 0.--31. 1. "PARAM_DONE_SET_STATUS_0 R,Parameter-set done status[31:0]: This read-only status register can be used by the main processor to see which parameter-sets are complete that led to the interrupt to the main processor. The individual bits in this 64-bit.."
|
|
line.long 0x4 "PARAM_DONE_SET_STATUS_1,"
|
|
hexmask.long 0x4 0.--31. 1. "PARAM_DONE_SET_STATUS_1 R,Parameter-set done status[63:32]: This read-only status register can be used by the main processor to see which parameter-sets are complete that led to the interrupt to the main processor. The individual bits in this 64-bit.."
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
group.long ($2+0xDC)++0x3
|
|
line.long 0x0 "PARAM_DONE_CLR_$1,"
|
|
hexmask.long 0x0 0.--31. 1. "param_done_status_clr_0,Status bits in PARAM_DONE_SET_STATUS are not automatically cleared but they can be individually cleared by writing to 64-bit register PARAM_DONE_CLR. It s a Self clearing bit"
|
|
repeat.end
|
|
rgroup.long 0xE4++0x7
|
|
line.long 0x0 "TRIGGER_SET_STATUS_0,"
|
|
hexmask.long 0x0 0.--31. 1. "TRIGGER_SET_STATUS_0,Debug register for trigger status[31:0]: This is a read-only status register which indicates the trigger status of the accelerator i.e. whether a specific DMA trigger or a CSI or a SW trigger was ever received (refer TRIGMODE in.."
|
|
line.long 0x4 "TRIGGER_SET_STATUS_1,"
|
|
hexmask.long 0x4 0.--31. 1. "TRIGGER_SET_STATUS_1,Debug register for trigger status[63:32]: This is a read-only status register which indicates the trigger status of the accelerator i.e. whether a specific DMA trigger or a CSI or a SW trigger was ever received (refer TRIGMODE in.."
|
|
group.long 0xEC++0xF
|
|
line.long 0x0 "TRIGGER_SET_IN_CLR_0,"
|
|
bitfld.long 0x0 0. "TRIGGER_SET_IN_CLR_0,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_0 described above It s a Self clearing bit" "0,1"
|
|
line.long 0x4 "TRIGGER_SET_IN_CLR_1,"
|
|
bitfld.long 0x4 0. "TRIGGER_SET_IN_CLR_1,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_1 described above It s a Self clearing bit" "0,1"
|
|
line.long 0x8 "DC_EST_RESET_SW,"
|
|
bitfld.long 0x8 0. "DC_EST_RESET_SW,Reset for all 12 DC estimation accumulators It s a Self clearing bit" "0,1"
|
|
line.long 0xC "DC_EST_CTRL,"
|
|
hexmask.long.byte 0xC 16.--19. 1. "DC_EST_SHIFT,Programmable shift applied to all 12 accumulator outputs. Cannot be bypassed. Output shifted by 2^(8 + 6+DCEST_SHIFT). For DCEST_SHIFT = 15 also gives 2^(28) and not 29 (saturate at 28)"
|
|
newline
|
|
hexmask.long.word 0xC 0.--8. 1. "15-9,9-bit scale applied to all 12 accumulators. Multiplies the accumulator output by DCEST_SCALE/256.This is followed by right shift and truncation. Default value is 256 giving a scale of 1.0. Setting it to 128 gives a scale of 0.5"
|
|
rgroup.long 0xFC++0x127
|
|
line.long 0x0 "DC_EST_I_0_VAL,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DC_EST_I_0_VAL,This read only register provide the DC estimates I for bcnt= 0"
|
|
line.long 0x4 "DC_EST_I_1_VAL,"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "DC_EST_I_1_VAL,This read only register provide the DC estimates I for bcnt= 1"
|
|
line.long 0x8 "DC_EST_I_2_VAL,"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "DC_EST_I_2_VAL,This read only register provide the DC estimates I for bcnt= 2"
|
|
line.long 0xC "DC_EST_I_3_VAL,"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "DC_EST_I_3_VAL,This read only register provide the DC estimates I for bcnt= 3"
|
|
line.long 0x10 "DC_EST_I_4_VAL,"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "DC_EST_I_4_VAL,This read only register provide the DC estimates I for bcnt= 4"
|
|
line.long 0x14 "DC_EST_I_5_VAL,"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "DC_EST_I_5_VAL,This read only register provide the DC estimates I for bcnt= 5"
|
|
line.long 0x18 "DC_EST_I_6_VAL,"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "DC_EST_I_6_VAL,This read only register provide the DC estimates I for bcnt= 6"
|
|
line.long 0x1C "DC_EST_I_7_VAL,"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "DC_EST_I_7_VAL,This read only register provide the DC estimates I for bcnt= 7"
|
|
line.long 0x20 "DC_EST_I_8_VAL,"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "DC_EST_I_8_VAL,This read only register provide the DC estimates I for bcnt= 8"
|
|
line.long 0x24 "DC_EST_I_9_VAL,"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "DC_EST_I_9_VAL,This read only register provide the DC estimates I for bcnt= 9"
|
|
line.long 0x28 "DC_EST_I_10_VAL,"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "DC_EST_I_10_VAL,This read only register provide the DC estimates I for bcnt= 10"
|
|
line.long 0x2C "DC_EST_I_11_VAL,"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "DC_EST_I_11_VAL,This read only register provide the DC estimates I for bcnt= 11"
|
|
line.long 0x30 "DC_EST_Q_0_VAL,"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. "DC_EST_Q_0_VAL,This read only register provide the DC estimates Q for bcnt= 0"
|
|
line.long 0x34 "DC_EST_Q_1_VAL,"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. "DC_EST_Q_1_VAL,This read only register provide the DC estimates Q for bcnt= 1"
|
|
line.long 0x38 "DC_EST_Q_2_VAL,"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. "DC_EST_Q_2_VAL,This read only register provide the DC estimates Q for bcnt= 2"
|
|
line.long 0x3C "DC_EST_Q_3_VAL,"
|
|
hexmask.long.tbyte 0x3C 0.--23. 1. "DC_EST_Q_3_VAL,This read only register provide the DC estimates Q for bcnt= 3"
|
|
line.long 0x40 "DC_EST_Q_4_VAL,"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. "DC_EST_Q_4_VAL,This read only register provide the DC estimates Q for bcnt= 4"
|
|
line.long 0x44 "DC_EST_Q_5_VAL,"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. "DC_EST_Q_5_VAL,This read only register provide the DC estimates Q for bcnt= 5"
|
|
line.long 0x48 "DC_EST_Q_6_VAL,"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. "DC_EST_Q_6_VAL,This read only register provide the DC estimates Q for bcnt= 6"
|
|
line.long 0x4C "DC_EST_Q_7_VAL,"
|
|
hexmask.long.tbyte 0x4C 0.--23. 1. "DC_EST_Q_7_VAL,This read only register provide the DC estimates Q for bcnt= 7"
|
|
line.long 0x50 "DC_EST_Q_8_VAL,"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. "DC_EST_Q_8_VAL,This read only register provide the DC estimates Q for bcnt= 8"
|
|
line.long 0x54 "DC_EST_Q_9_VAL,"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. "DC_EST_Q_9_VAL,This read only register provide the DC estimates Q for bcnt= 9"
|
|
line.long 0x58 "DC_EST_Q_10_VAL,"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. "DC_EST_Q_10_VAL,This read only register provide the DC estimates Q for bcnt= 10"
|
|
line.long 0x5C "DC_EST_Q_11_VAL,"
|
|
hexmask.long.tbyte 0x5C 0.--23. 1. "DC_EST_Q_11_VAL,This read only register provide the DC estimates Q for bcnt= 11"
|
|
line.long 0x60 "DC_ACC_I_0_VAL_LSB,"
|
|
hexmask.long 0x60 0.--31. 1. "DC_ACC_I_0_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=0"
|
|
line.long 0x64 "DC_ACC_I_0_VAL_MSB,"
|
|
hexmask.long.byte 0x64 0.--3. 1. "DC_ACC_I_0_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=0"
|
|
line.long 0x68 "DC_ACC_I_1_VAL_LSB,"
|
|
hexmask.long 0x68 0.--31. 1. "DC_ACC_I_1_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=1"
|
|
line.long 0x6C "DC_ACC_I_1_VAL_MSB,"
|
|
hexmask.long.byte 0x6C 0.--3. 1. "DC_ACC_I_1_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=1"
|
|
line.long 0x70 "DC_ACC_I_2_VAL_LSB,"
|
|
hexmask.long 0x70 0.--31. 1. "DC_ACC_I_2_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=2"
|
|
line.long 0x74 "DC_ACC_I_2_VAL_MSB,"
|
|
hexmask.long.byte 0x74 0.--3. 1. "DC_ACC_I_2_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=2"
|
|
line.long 0x78 "DC_ACC_I_3_VAL_LSB,"
|
|
hexmask.long 0x78 0.--31. 1. "DC_ACC_I_3_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=3"
|
|
line.long 0x7C "DC_ACC_I_3_VAL_MSB,"
|
|
hexmask.long.byte 0x7C 0.--3. 1. "DC_ACC_I_3_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=3"
|
|
line.long 0x80 "DC_ACC_I_4_VAL_LSB,"
|
|
hexmask.long 0x80 0.--31. 1. "DC_ACC_I_4_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=4"
|
|
line.long 0x84 "DC_ACC_I_4_VAL_MSB,"
|
|
hexmask.long.byte 0x84 0.--3. 1. "DC_ACC_I_4_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=4"
|
|
line.long 0x88 "DC_ACC_I_5_VAL_LSB,"
|
|
hexmask.long 0x88 0.--31. 1. "DC_ACC_I_5_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=5"
|
|
line.long 0x8C "DC_ACC_I_5_VAL_MSB,"
|
|
hexmask.long.byte 0x8C 0.--3. 1. "DC_ACC_I_5_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=5"
|
|
line.long 0x90 "DC_ACC_I_6_VAL_LSB,"
|
|
hexmask.long 0x90 0.--31. 1. "DC_ACC_I_6_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=6"
|
|
line.long 0x94 "DC_ACC_I_6_VAL_MSB,"
|
|
hexmask.long.byte 0x94 0.--3. 1. "DC_ACC_I_6_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=6"
|
|
line.long 0x98 "DC_ACC_I_7_VAL_LSB,"
|
|
hexmask.long 0x98 0.--31. 1. "DC_ACC_I_7_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=7"
|
|
line.long 0x9C "DC_ACC_I_7_VAL_MSB,"
|
|
hexmask.long.byte 0x9C 0.--3. 1. "DC_ACC_I_7_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=7"
|
|
line.long 0xA0 "DC_ACC_I_8_VAL_LSB,"
|
|
hexmask.long 0xA0 0.--31. 1. "DC_ACC_I_8_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=8"
|
|
line.long 0xA4 "DC_ACC_I_8_VAL_MSB,"
|
|
hexmask.long.byte 0xA4 0.--3. 1. "DC_ACC_I_8_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=8"
|
|
line.long 0xA8 "DC_ACC_I_9_VAL_LSB,"
|
|
hexmask.long 0xA8 0.--31. 1. "DC_ACC_I_9_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=9"
|
|
line.long 0xAC "DC_ACC_I_9_VAL_MSB,"
|
|
hexmask.long.byte 0xAC 0.--3. 1. "DC_ACC_I_9_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=9"
|
|
line.long 0xB0 "DC_ACC_I_10_VAL_LSB,"
|
|
hexmask.long 0xB0 0.--31. 1. "DC_ACC_I_10_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=10"
|
|
line.long 0xB4 "DC_ACC_I_10_VAL_MSB,"
|
|
hexmask.long.byte 0xB4 0.--3. 1. "DC_ACC_I_10_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=10"
|
|
line.long 0xB8 "DC_ACC_I_11_VAL_LSB,"
|
|
hexmask.long 0xB8 0.--31. 1. "DC_ACC_I_11_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator I channel value for bcnt=11"
|
|
line.long 0xBC "DC_ACC_I_11_VAL_MSB,"
|
|
hexmask.long.byte 0xBC 0.--3. 1. "DC_ACC_I_11_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=11"
|
|
line.long 0xC0 "DC_ACC_Q_0_VAL_LSB,"
|
|
hexmask.long 0xC0 0.--31. 1. "DC_ACC_Q_0_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=0"
|
|
line.long 0xC4 "DC_ACC_Q_0_VAL_MSB,"
|
|
hexmask.long.byte 0xC4 0.--3. 1. "DC_ACC_Q_0_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=0"
|
|
line.long 0xC8 "DC_ACC_Q_1_VAL_LSB,"
|
|
hexmask.long 0xC8 0.--31. 1. "DC_ACC_Q_1_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=1"
|
|
line.long 0xCC "DC_ACC_Q_1_VAL_MSB,"
|
|
hexmask.long.byte 0xCC 0.--3. 1. "DC_ACC_Q_1_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=1"
|
|
line.long 0xD0 "DC_ACC_Q_2_VAL_LSB,"
|
|
hexmask.long 0xD0 0.--31. 1. "DC_ACC_Q_2_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=2"
|
|
line.long 0xD4 "DC_ACC_Q_2_VAL_MSB,"
|
|
hexmask.long.byte 0xD4 0.--3. 1. "DC_ACC_Q_2_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=2"
|
|
line.long 0xD8 "DC_ACC_Q_3_VAL_LSB,"
|
|
hexmask.long 0xD8 0.--31. 1. "DC_ACC_Q_3_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=3"
|
|
line.long 0xDC "DC_ACC_Q_3_VAL_MSB,"
|
|
hexmask.long.byte 0xDC 0.--3. 1. "DC_ACC_Q_3_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=3"
|
|
line.long 0xE0 "DC_ACC_Q_4_VAL_LSB,"
|
|
hexmask.long 0xE0 0.--31. 1. "DC_ACC_Q_4_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=4"
|
|
line.long 0xE4 "DC_ACC_Q_4_VAL_MSB,"
|
|
hexmask.long.byte 0xE4 0.--3. 1. "DC_ACC_Q_4_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=4"
|
|
line.long 0xE8 "DC_ACC_Q_5_VAL_LSB,"
|
|
hexmask.long 0xE8 0.--31. 1. "DC_ACC_Q_5_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=5"
|
|
line.long 0xEC "DC_ACC_Q_5_VAL_MSB,"
|
|
hexmask.long.byte 0xEC 0.--3. 1. "DC_ACC_Q_5_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=5"
|
|
line.long 0xF0 "DC_ACC_Q_6_VAL_LSB,"
|
|
hexmask.long 0xF0 0.--31. 1. "DC_ACC_Q_6_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=6"
|
|
line.long 0xF4 "DC_ACC_Q_6_VAL_MSB,"
|
|
hexmask.long.byte 0xF4 0.--3. 1. "DC_ACC_Q_6_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=6"
|
|
line.long 0xF8 "DC_ACC_Q_7_VAL_LSB,"
|
|
hexmask.long 0xF8 0.--31. 1. "DC_ACC_Q_7_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=7"
|
|
line.long 0xFC "DC_ACC_Q_7_VAL_MSB,"
|
|
hexmask.long.byte 0xFC 0.--3. 1. "DC_ACC_Q_7_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=7"
|
|
line.long 0x100 "DC_ACC_Q_8_VAL_LSB,"
|
|
hexmask.long 0x100 0.--31. 1. "DC_ACC_Q_8_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=8"
|
|
line.long 0x104 "DC_ACC_Q_8_VAL_MSB,"
|
|
hexmask.long.byte 0x104 0.--3. 1. "DC_ACC_Q_8_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=8"
|
|
line.long 0x108 "DC_ACC_Q_9_VAL_LSB,"
|
|
hexmask.long 0x108 0.--31. 1. "DC_ACC_Q_9_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=9"
|
|
line.long 0x10C "DC_ACC_Q_9_VAL_MSB,"
|
|
hexmask.long.byte 0x10C 0.--3. 1. "DC_ACC_Q_9_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=9"
|
|
line.long 0x110 "DC_ACC_Q_10_VAL_LSB,"
|
|
hexmask.long 0x110 0.--31. 1. "DC_ACC_Q_10_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=10"
|
|
line.long 0x114 "DC_ACC_Q_10_VAL_MSB,"
|
|
hexmask.long.byte 0x114 0.--3. 1. "DC_ACC_Q_10_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=10"
|
|
line.long 0x118 "DC_ACC_Q_11_VAL_LSB,"
|
|
hexmask.long 0x118 0.--31. 1. "DC_ACC_Q_11_VAL_LSB,This read only register provide the LSB 32 bits value of DC accumulator Q channel value for bcnt=11"
|
|
line.long 0x11C "DC_ACC_Q_11_VAL_MSB,"
|
|
hexmask.long.byte 0x11C 0.--3. 1. "DC_ACC_Q_11_VAL_MSB,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=11"
|
|
line.long 0x120 "DC_ACC_CLIP_STATUS,"
|
|
hexmask.long.word 0x120 0.--11. 1. "DC_ACC_CLIP_STATUS,This register contains the clip status of both I/Q of DC accumulators 0 to 11"
|
|
line.long 0x124 "DC_EST_CLIP_STATUS,"
|
|
hexmask.long.word 0x124 0.--11. 1. "DC_EST_CLIP_STATUS,This register contains the clip status of DC estimates (both I & Q combined)"
|
|
group.long 0x224++0x5F
|
|
line.long 0x0 "DC_I0_SW,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DC_I0_SW,SW programmed DC I value(for bcnt =0 ) used in DC subtraction"
|
|
line.long 0x4 "DC_I1_SW,"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "DC_I1_SW,SW programmed DC I value(for bcnt =1) used in DC subtraction"
|
|
line.long 0x8 "DC_I2_SW,"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "DC_I2_SW,SW programmed DC I value(for bcnt =2 ) used in DC subtraction"
|
|
line.long 0xC "DC_I3_SW,"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "DC_I3_SW,SW programmed DC I value(for bcnt =3) used in DC subtraction"
|
|
line.long 0x10 "DC_I4_SW,"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "DC_I4_SW,SW programmed DC I value(for bcnt =4 ) used in DC subtraction"
|
|
line.long 0x14 "DC_I5_SW,"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "DC_I5_SW,SW programmed DC I value(for bcnt =5 ) used in DC subtraction"
|
|
line.long 0x18 "DC_I6_SW,"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "DC_I6_SW,SW programmed DC I value(for bcnt =6 ) used in DC subtraction"
|
|
line.long 0x1C "DC_I7_SW,"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "DC_I7_SW,SW programmed DC I value(for bcnt =7 ) used in DC subtraction"
|
|
line.long 0x20 "DC_I8_SW,"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "DC_I8_SW,SW programmed DC I value(for bcnt =8) used in DC subtraction"
|
|
line.long 0x24 "DC_I9_SW,"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "DC_I9_SW,SW programmed DC I value(for bcnt =9 ) used in DC subtraction"
|
|
line.long 0x28 "DC_I10_SW,"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "DC_I10_SW,SW programmed DC I value(for bcnt =10 ) used in DC subtraction"
|
|
line.long 0x2C "DC_I11_SW,"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "DC_I11_SW,SW programmed DC I value(for bcnt =11) used in DC subtraction"
|
|
line.long 0x30 "DC_Q0_SW,"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. "DC_Q0_SW,SW programmed DC Q value(for bcnt =0 ) used in DC subtraction"
|
|
line.long 0x34 "DC_Q1_SW,"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. "DC_Q1_SW,SW programmed DC Q value(for bcnt =1) used in DC subtraction"
|
|
line.long 0x38 "DC_Q2_SW,"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. "DC_Q2_SW,SW programmed DC Q value(for bcnt =2 ) used in DC subtraction"
|
|
line.long 0x3C "DC_Q3_SW,"
|
|
hexmask.long.tbyte 0x3C 0.--23. 1. "DC_Q3_SW,SW programmed DC Q value(for bcnt =3) used in DC subtraction"
|
|
line.long 0x40 "DC_Q4_SW,"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. "DC_Q4_SW,SW programmed DC Q value(for bcnt =4 ) used in DC subtraction"
|
|
line.long 0x44 "DC_Q5_SW,"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. "DC_Q5_SW,SW programmed DC Q value(for bcnt =5 ) used in DC subtraction"
|
|
line.long 0x48 "DC_Q6_SW,"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. "DC_Q6_SW,SW programmed DC Q value(for bcnt =6 ) used in DC subtraction"
|
|
line.long 0x4C "DC_Q7_SW,"
|
|
hexmask.long.tbyte 0x4C 0.--23. 1. "DC_Q7_SW,SW programmed DC Q value(for bcnt =7 ) used in DC subtraction"
|
|
line.long 0x50 "DC_Q8_SW,"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. "DC_Q8_SW,SW programmed DC Q value(for bcnt =8) used in DC subtraction"
|
|
line.long 0x54 "DC_Q9_SW,"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. "DC_Q9_SW,SW programmed DC Q value(for bcnt =9 ) used in DC subtraction"
|
|
line.long 0x58 "DC_Q10_SW,"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. "DC_Q10_SW,SW programmed DC Q value(for bcnt =10 ) used in DC subtraction"
|
|
line.long 0x5C "DC_Q11_SW,"
|
|
hexmask.long.tbyte 0x5C 0.--23. 1. "DC_Q11_SW,SW programmed DC Q value(for bcnt =11) used in DC subtraction"
|
|
rgroup.long 0x284++0x3
|
|
line.long 0x0 "DC_SUB_CLIP,"
|
|
bitfld.long 0x0 0. "DC_SUB_CLIP,Indicates the DC subtraction clip status" "0,1"
|
|
repeat 4. (list 0x2 0x3 0x4 0x5)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x288)++0x3
|
|
line.long 0x0 "DC_RESERVED_$1,"
|
|
hexmask.long 0x0 0.--31. 1. "dc_sub_reserved_2,Reserved for future addition"
|
|
repeat.end
|
|
group.long 0x298++0x7
|
|
line.long 0x0 "INTF_STATS_RESET_SW,"
|
|
bitfld.long 0x0 0. "INTF_STATS_RESET_SW,SW reset for Interference stats module. It s a self clearing bit." "0,1"
|
|
line.long 0x4 "INTF_STATS_CTRL,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "INTF_STATS_MAGDIFF_SCALE,Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block. Default 8= scale of 1.0"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "INTF_STATS_MAG_SCALE,Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block. Default 8= scale of 1.0"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "INTF_STATS_MAGDIFF_SHIFT,Right shift applied after scaling - 2^(6+INTERFSUM_MAGDIFF_SHIFT). Can t be more than 2^(12)." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "INTF_STATS_MAG_SHIFT,Right shift applied after scaling - 2^(6+INTERSUM_MAGS_SHIFT). Can t be more than 2^(12)." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2A0++0x127
|
|
line.long 0x0 "INTF_LOC_THRESH_MAG0_VAL,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "INTF_LOC_THRESH_MAG0_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =0"
|
|
line.long 0x4 "INTF_LOC_THRESH_MAG1_VAL,"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "INTF_LOC_THRESH_MAG1_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =1"
|
|
line.long 0x8 "INTF_LOC_THRESH_MAG2_VAL,"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "INTF_LOC_THRESH_MAG2_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =2"
|
|
line.long 0xC "INTF_LOC_THRESH_MAG3_VAL,"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "INTF_LOC_THRESH_MAG3_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =3"
|
|
line.long 0x10 "INTF_LOC_THRESH_MAG4_VAL,"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "INTF_LOC_THRESH_MAG4_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =4"
|
|
line.long 0x14 "INTF_LOC_THRESH_MAG5_VAL,"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "INTF_LOC_THRESH_MAG5_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =5"
|
|
line.long 0x18 "INTF_LOC_THRESH_MAG6_VAL,"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "INTF_LOC_THRESH_MAG6_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =6"
|
|
line.long 0x1C "INTF_LOC_THRESH_MAG7_VAL,"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "INTF_LOC_THRESH_MAG7_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =7"
|
|
line.long 0x20 "INTF_LOC_THRESH_MAG8_VAL,"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "INTF_LOC_THRESH_MAG8_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =8"
|
|
line.long 0x24 "INTF_LOC_THRESH_MAG9_VAL,"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "INTF_LOC_THRESH_MAG9_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =9"
|
|
line.long 0x28 "INTF_LOC_THRESH_MAG10_VAL,"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "INTF_LOC_THRESH_MAG10_VA,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =10"
|
|
line.long 0x2C "INTF_LOC_THRESH_MAG11_VAL,"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "INTF_LOC_THRESH_MAG11_VAL R,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =11"
|
|
line.long 0x30 "INTF_LOC_THRESH_MAGDIFF0_VAL,"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF0_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =0"
|
|
line.long 0x34 "INTF_LOC_THRESH_MAGDIFF1_VAL,"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF1_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =1"
|
|
line.long 0x38 "INTF_LOC_THRESH_MAGDIFF2_VAL,"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF2_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =2"
|
|
line.long 0x3C "INTF_LOC_THRESH_MAGDIFF3_VAL,"
|
|
hexmask.long.tbyte 0x3C 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF3_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =3"
|
|
line.long 0x40 "INTF_LOC_THRESH_MAGDIFF4_VAL,"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF4_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =4"
|
|
line.long 0x44 "INTF_LOC_THRESH_MAGDIFF5_VAL,"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF5_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =5"
|
|
line.long 0x48 "INTF_LOC_THRESH_MAGDIFF6_VAL,"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF6_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =6"
|
|
line.long 0x4C "INTF_LOC_THRESH_MAGDIFF7_VAL,"
|
|
hexmask.long.tbyte 0x4C 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF7_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =7"
|
|
line.long 0x50 "INTF_LOC_THRESH_MAGDIFF8_VAL,"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF8_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =8"
|
|
line.long 0x54 "INTF_LOC_THRESH_MAGDIFF9_VAL,"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF9_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =9"
|
|
line.long 0x58 "INTF_LOC_THRESH_MAGDIFF10_VAL,"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF10,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =10"
|
|
line.long 0x5C "INTF_LOC_THRESH_MAGDIFF11_VAL,"
|
|
hexmask.long.tbyte 0x5C 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF11_,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =11"
|
|
line.long 0x60 "INTF_LOC_COUNT_ALL_CHIRP,"
|
|
hexmask.long.word 0x60 0.--11. 1. "INTF_LOC_COUNT_ALL_CHIRP,Number of samples that exceeded the threshold in a chirp"
|
|
line.long 0x64 "INTF_LOC_COUNT_ALL_FRAME,"
|
|
hexmask.long.tbyte 0x64 0.--19. 1. "INTF_LOC_COUNT_ALL_FRAME,Number of samples that exceeded the threshold in a frame"
|
|
line.long 0x68 "INTF_STATS_MAG_ACC_0_LSB,"
|
|
hexmask.long 0x68 0.--31. 1. "INTF_STATS_MAG_ACC_0_LSB R,This read only register contains the accumulator value of interference magnitude(LSB 32 bits) for bcnt = 0"
|
|
line.long 0x6C "INTF_STATS_MAG_ACC_0_MSB,"
|
|
hexmask.long.byte 0x6C 0.--3. 1. "INTF_STATS_MAG_ACC_0_MS,This read only register contains the accumulator value of interference magnitude(MSB 4 bits) for bcnt = 0"
|
|
line.long 0x70 "INTF_STATS_MAG_ACC_1_LSB,"
|
|
hexmask.long 0x70 0.--31. 1. "INTF_STATS_MAG_ACC_1_LSB R,This read only contains the accumulator value of interference magnitude (LSB 32 bits) for bcnt = 1"
|
|
line.long 0x74 "INTF_STATS_MAG_ACC_1_MSB,"
|
|
hexmask.long.byte 0x74 0.--3. 1. "INTF_STATS_MAG_ACC_1_MS,This read only contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 1"
|
|
line.long 0x78 "INTF_STATS_MAG_ACC_2_LSB,"
|
|
hexmask.long 0x78 0.--31. 1. "INTF_STATS_MAG_ACC_2_LSB R,This read only contains the accumulator value of interference magnitude (LSB 32 bits) for bcnt = 2"
|
|
line.long 0x7C "INTF_STATS_MAG_ACC_2_MSB,"
|
|
hexmask.long.byte 0x7C 0.--3. 1. "INTF_STATS_MAG_ACC_2_MS,This read only register contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 2"
|
|
line.long 0x80 "INTF_STATS_MAG_ACC_3_LSB,"
|
|
hexmask.long 0x80 0.--31. 1. "INTF_STATS_MAG_ACC_3_LSB R,This read only register contains the accumulator value of the interference magnitude( for LSB 32 bits) for bcnt = 3"
|
|
line.long 0x84 "INTF_STATS_MAG_ACC_3_MSB,"
|
|
hexmask.long.byte 0x84 0.--3. 1. "INTF_STATS_MAG_ACC_3_MS,This read only register contains the accumulator value of the interference magnitude(for MSB 4 bits) for bcnt = 3"
|
|
line.long 0x88 "INTF_STATS_MAG_ACC_4_LSB,"
|
|
hexmask.long 0x88 0.--31. 1. "INTF_STATS_MAG_ACC_4_LSB R,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 4"
|
|
line.long 0x8C "INTF_STATS_MAG_ACC_4_MSB,"
|
|
hexmask.long.byte 0x8C 0.--3. 1. "INTF_STATS_MAG_ACC_4_MS,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 4"
|
|
line.long 0x90 "INTF_STATS_MAG_ACC_5_LSB,"
|
|
hexmask.long 0x90 0.--31. 1. "INTF_STATS_MAG_ACC_5_LSB R,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 5"
|
|
line.long 0x94 "INTF_STATS_MAG_ACC_5_MSB,"
|
|
hexmask.long.byte 0x94 0.--3. 1. "INTF_STATS_MAG_ACC_5_MS,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 5"
|
|
line.long 0x98 "INTF_STATS_MAG_ACC_6_LSB,"
|
|
hexmask.long 0x98 0.--31. 1. "INTF_STATS_MAG_ACC_6_LSB R,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 6"
|
|
line.long 0x9C "INTF_STATS_MAG_ACC_6_MSB,"
|
|
hexmask.long.byte 0x9C 0.--3. 1. "INTF_STATS_MAG_ACC_6_MS,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 6"
|
|
line.long 0xA0 "INTF_STATS_MAG_ACC_7_LSB,"
|
|
hexmask.long 0xA0 0.--31. 1. "INTF_STATS_MAG_ACC_7_LSB R,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 7"
|
|
line.long 0xA4 "INTF_STATS_MAG_ACC_7_MSB,"
|
|
hexmask.long.byte 0xA4 0.--3. 1. "INTF_STATS_MAG_ACC_7_MS,This read only register contains the accumulator value of the interference magnitude (MSB4 bits)for bcnt = 7"
|
|
line.long 0xA8 "INTF_STATS_MAG_ACC_8_LSB,"
|
|
hexmask.long 0xA8 0.--31. 1. "INTF_STATS_MAG_ACC_8_LSB R,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 8"
|
|
line.long 0xAC "INTF_STATS_MAG_ACC_8_MSB,"
|
|
hexmask.long.byte 0xAC 0.--3. 1. "INTF_STATS_MAG_ACC_8_MS,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 8"
|
|
line.long 0xB0 "INTF_STATS_MAG_ACC_9_LSB,"
|
|
hexmask.long 0xB0 0.--31. 1. "INTF_STATS_MAG_ACC_9_LSB R,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 9"
|
|
line.long 0xB4 "INTF_STATS_MAG_ACC_9_MSB,"
|
|
hexmask.long.byte 0xB4 0.--3. 1. "INTF_STATS_MAG_ACC_9_MS,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 9"
|
|
line.long 0xB8 "INTF_STATS_MAG_ACC_10_LSB,"
|
|
hexmask.long 0xB8 0.--31. 1. "INTF_STATS_MAG_ACC_10_LS,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits)for bcnt = 10"
|
|
line.long 0xBC "INTF_STATS_MAG_ACC_10_MSB,"
|
|
hexmask.long.byte 0xBC 0.--3. 1. "INTF_STATS_MAG_ACC_10_M,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 10"
|
|
line.long 0xC0 "INTF_STATS_MAG_ACC_11_LSB,"
|
|
hexmask.long 0xC0 0.--31. 1. "INTF_STATS_MAG_ACC_11_LS,This read only register contains the accumulator value of the interference magnitude (LSB 32 bits)for bcnt = 11"
|
|
line.long 0xC4 "INTF_STATS_MAG_ACC_11_MSB,"
|
|
hexmask.long.byte 0xC4 0.--3. 1. "INTF_STATS_MAG_ACC_11_M,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 11"
|
|
line.long 0xC8 "INTF_STATS_MAGDIFF_ACC_0_LSB,"
|
|
hexmask.long 0xC8 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_0_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 0"
|
|
line.long 0xCC "INTF_STATS_MAGDIFF_ACC_0_MSB,"
|
|
hexmask.long.byte 0xCC 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_0_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0"
|
|
line.long 0xD0 "INTF_STATS_MAGDIFF_ACC_1_LSB,"
|
|
hexmask.long 0xD0 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_1_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 1"
|
|
line.long 0xD4 "INTF_STATS_MAGDIFF_ACC_1_MSB,"
|
|
hexmask.long.byte 0xD4 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_1_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1"
|
|
line.long 0xD8 "INTF_STATS_MAGDIFF_ACC_2_LSB,"
|
|
hexmask.long 0xD8 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_2_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 2"
|
|
line.long 0xDC "INTF_STATS_MAGDIFF_ACC_2_MSB,"
|
|
hexmask.long.byte 0xDC 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_2_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2"
|
|
line.long 0xE0 "INTF_STATS_MAGDIFF_ACC_3_LSB,"
|
|
hexmask.long 0xE0 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_3_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 3"
|
|
line.long 0xE4 "INTF_STATS_MAGDIFF_ACC_3_MSB,"
|
|
hexmask.long.byte 0xE4 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_3_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3"
|
|
line.long 0xE8 "INTF_STATS_MAGDIFF_ACC_4_LSB,"
|
|
hexmask.long 0xE8 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_4_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) accumulator for bcnt = 4"
|
|
line.long 0xEC "INTF_STATS_MAGDIFF_ACC_4_MSB,"
|
|
hexmask.long.byte 0xEC 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_4_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4"
|
|
line.long 0xF0 "INTF_STATS_MAGDIFF_ACC_5_LSB,"
|
|
hexmask.long 0xF0 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_5_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 5"
|
|
line.long 0xF4 "INTF_STATS_MAGDIFF_ACC_5_MSB,"
|
|
hexmask.long.byte 0xF4 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_5_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5"
|
|
line.long 0xF8 "INTF_STATS_MAGDIFF_ACC_6_LSB,"
|
|
hexmask.long 0xF8 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_6_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 6"
|
|
line.long 0xFC "INTF_STATS_MAGDIFF_ACC_6_MSB,"
|
|
hexmask.long.byte 0xFC 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_6_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 6"
|
|
line.long 0x100 "INTF_STATS_MAGDIFF_ACC_7_LSB,"
|
|
hexmask.long 0x100 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_7_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 7"
|
|
line.long 0x104 "INTF_STATS_MAGDIFF_ACC_7_MSB,"
|
|
hexmask.long.byte 0x104 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_7_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 7"
|
|
line.long 0x108 "INTF_STATS_MAGDIFF_ACC_8_LSB,"
|
|
hexmask.long 0x108 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_8_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 8"
|
|
line.long 0x10C "INTF_STATS_MAGDIFF_ACC_8_MSB,"
|
|
hexmask.long.byte 0x10C 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_8_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 8"
|
|
line.long 0x110 "INTF_STATS_MAGDIFF_ACC_9_LSB,"
|
|
hexmask.long 0x110 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_9_L,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 9"
|
|
line.long 0x114 "INTF_STATS_MAGDIFF_ACC_9_MSB,"
|
|
hexmask.long.byte 0x114 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_9_,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 9"
|
|
line.long 0x118 "INTF_STATS_MAGDIFF_ACC_10_LSB,"
|
|
hexmask.long 0x118 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_10,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 10"
|
|
line.long 0x11C "INTF_STATS_MAGDIFF_ACC_10_MSB,"
|
|
hexmask.long.byte 0x11C 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_10,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 10"
|
|
line.long 0x120 "INTF_STATS_MAGDIFF_ACC_11_LSB,"
|
|
hexmask.long 0x120 0.--31. 1. "INTF_STATS_MAGDIFF_ACC_11,This read only register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 11"
|
|
line.long 0x124 "INTF_STATS_MAGDIFF_ACC_11_MSB,"
|
|
hexmask.long.byte 0x124 0.--3. 1. "INTF_STATS_MAGDIFF_ACC_11,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 11"
|
|
group.long 0x3C8++0x5F
|
|
line.long 0x0 "INTF_LOC_THRESH_MAG0_SW,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "INTF_LOC_THRESH_MAG0_SW,SW programmed interface threshold magnitude for bcnt=0"
|
|
line.long 0x4 "INTF_LOC_THRESH_MAG1_SW,"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "INTF_LOC_THRESH_MAG1_SW,SW programmed interface threshold magnitude for bcnt=1"
|
|
line.long 0x8 "INTF_LOC_THRESH_MAG2_SW,"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "INTF_LOC_THRESH_MAG2_SW,SW programmed interface threshold magnitude for bcnt=2"
|
|
line.long 0xC "INTF_LOC_THRESH_MAG3_SW,"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "INTF_LOC_THRESH_MAG3_SW,SW programmed interface threshold magnitude for bcnt=3"
|
|
line.long 0x10 "INTF_LOC_THRESH_MAG4_SW,"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "INTF_LOC_THRESH_MAG4_SW,SW programmed interface threshold magnitude for bcnt=4"
|
|
line.long 0x14 "INTF_LOC_THRESH_MAG5_SW,"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "INTF_LOC_THRESH_MAG5_SW,SW programmed interface threshold magnitude for bcnt=5"
|
|
line.long 0x18 "INTF_LOC_THRESH_MAG6_SW,"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "INTF_LOC_THRESH_MAG6_SW,SW programmed interface threshold magnitude for bcnt=6"
|
|
line.long 0x1C "INTF_LOC_THRESH_MAG7_SW,"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "INTF_LOC_THRESH_MAG7_SW,SW programmed interface threshold magnitude for bcnt=7"
|
|
line.long 0x20 "INTF_LOC_THRESH_MAG8_SW,"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "INTF_LOC_THRESH_MAG8_SW,SW programmed interface threshold magnitude for bcnt=8"
|
|
line.long 0x24 "INTF_LOC_THRESH_MAG9_SW,"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "INTF_LOC_THRESH_MAG9_SW,SW programmed interface threshold magnitude for bcnt=9"
|
|
line.long 0x28 "INTF_LOC_THRESH_MAG10_SW,"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. "INTF_LOC_THRESH_MAG10_SW,SW programmed interface threshold magnitude for bcnt=10"
|
|
line.long 0x2C "INTF_LOC_THRESH_MAG11_SW,"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "INTF_LOC_THRESH_MAG11_SW,SW programmed interface threshold magnitude for bcnt=11"
|
|
line.long 0x30 "INTF_LOC_THRESH_MAGDIFF0_SW,"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF0_,SW programmed interface threshold magnitude difference for bcnt=0"
|
|
line.long 0x34 "INTF_LOC_THRESH_MAGDIFF1_SW,"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF1_,SW programmed interface threshold magnitude difference for bcnt=1"
|
|
line.long 0x38 "INTF_LOC_THRESH_MAGDIFF2_SW,"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF2_,SW programmed interface threshold magnitude difference for bcnt=2"
|
|
line.long 0x3C "INTF_LOC_THRESH_MAGDIFF3_SW,"
|
|
hexmask.long.tbyte 0x3C 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF3_,SW programmed interface threshold magnitude difference for bcnt=3"
|
|
line.long 0x40 "INTF_LOC_THRESH_MAGDIFF4_SW,"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF4_,SW programmed interface threshold magnitude difference for bcnt=4"
|
|
line.long 0x44 "INTF_LOC_THRESH_MAGDIFF5_SW,"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF5_,SW programmed interface threshold magnitude difference for bcnt=5"
|
|
line.long 0x48 "INTF_LOC_THRESH_MAGDIFF6_SW,"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF6_,SW programmed interface threshold magnitude difference for bcnt=6"
|
|
line.long 0x4C "INTF_LOC_THRESH_MAGDIFF7_SW,"
|
|
hexmask.long.tbyte 0x4C 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF7_,SW programmed interface threshold magnitude difference for bcnt=7"
|
|
line.long 0x50 "INTF_LOC_THRESH_MAGDIFF8_SW,"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF8_,SW programmed interface threshold magnitude difference for bcnt=8"
|
|
line.long 0x54 "INTF_LOC_THRESH_MAGDIFF9_SW,"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF9_,SW programmed interface threshold magnitude difference for bcnt=9"
|
|
line.long 0x58 "INTF_LOC_THRESH_MAGDIFF10_SW,"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF10,SW programmed interface threshold magnitude difference for bcnt=10"
|
|
line.long 0x5C "INTF_LOC_THRESH_MAGDIFF11_SW,"
|
|
hexmask.long.tbyte 0x5C 0.--23. 1. "INTF_LOC_THRESH_MAGDIFF11_,SW programmed interface threshold magnitude difference for bcnt=11"
|
|
rgroup.long 0x428++0x7
|
|
line.long 0x0 "INTF_STATS_ACC_CLIP_STATUS,"
|
|
hexmask.long.word 0x0 16.--27. 1. "INTF_STATS_MAGDIFF_ACCUMU,Interference magnitue difference accumulator Clip status"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "LATOR_CLIP_STATUS,Interference magnitue accumulator Clip status"
|
|
line.long 0x4 "INTF_STATS_THRESH_CLIP_STATUS,"
|
|
hexmask.long.word 0x4 16.--27. 1. "INTF_STATS_THRESH_MAGDIFF_,Interference magnitude difference threshold Clip status"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "CLIP_STATUS,Interference magnitude threshold Clip status"
|
|
group.long 0x430++0x3
|
|
line.long 0x0 "INTF_MITG_WINDOW_PARAM_0,"
|
|
hexmask.long.byte 0x0 0.--4. 1. "INTF_MITG_WINDOW_PARAM_,This is a programmable array of window parameters. Each window parameter is an unsigned 5 bit integer. The total length of the array is 5. The BFR of the array is given by the matlab code : val = round(hanning(12)*32).."
|
|
repeat 4. (list 0x1 0x2 0x3 0x4)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x434)++0x3
|
|
line.long 0x0 "INTF_MITG_WINDOW_PARAM_$1,"
|
|
hexmask.long.byte 0x0 0.--4. 1. "INTF_MITG_WINDOW_PARAM_,Refer description of INTF_MITG_WINDOW_PARAM_0"
|
|
repeat.end
|
|
rgroup.long 0x444++0xF
|
|
line.long 0x0 "INTF_STATS_SUM_MAG_VAL,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "INTF_STATS_SUM_MAG_VAL,Indicates the sum of mag values ; Only Configured BCNT mag values are added"
|
|
line.long 0x4 "INTF_STATS_SUM_MAG_VAL_CLIP_STATUS,"
|
|
bitfld.long 0x4 0. "INTF_STATS_SUM_MAG_VAL_C,Indicates the clip status of sum of mag values" "0,1"
|
|
line.long 0x8 "INTF_STATS_SUM_MAGDIFF_VAL,"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "INTF_STATS_SUM_MAGDIFF_VA,Indicates the sum of magdiff values ; Only Configured BCNT magdiff values are added"
|
|
line.long 0xC "INTF_STATS_SUM_MAGDIFF_VAL_CLIP_STATUS,"
|
|
bitfld.long 0xC 0. "INTF_STATS_SUM_MAGDIFF_VA,indicates the clip status of sum of magdiff values" "0,1"
|
|
group.long 0x454++0x7
|
|
line.long 0x0 "INTERF_RESERVED_5,"
|
|
hexmask.long 0x0 0.--31. 1. "interf_reserved_5,Reserved for future addition"
|
|
line.long 0x4 "ICMULT_SCALE0,"
|
|
hexmask.long.tbyte 0x4 0.--20. 1. "ICMULT_SCALE0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration.."
|
|
repeat 11. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28)
|
|
group.long ($2+0x45C)++0x3
|
|
line.long 0x0 "ICMULT_SCALE$1,"
|
|
hexmask.long.tbyte 0x0 0.--20. 1. "icmult_scale1,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration.."
|
|
repeat.end
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24)
|
|
group.long ($2+0x488)++0x3
|
|
line.long 0x0 "QCMULT_SCALE$1,"
|
|
hexmask.long.tbyte 0x0 0.--20. 1. "qcmult_scale0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration.."
|
|
repeat.end
|
|
group.long 0x4B0++0x13
|
|
line.long 0x0 "QCMULT_SCALE10,"
|
|
hexmask.long.tbyte 0x0 0.--20. 1. "qcmult_scale10,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11.."
|
|
line.long 0x4 "QCMULT_SCALE11,"
|
|
hexmask.long.tbyte 0x4 0.--20. 1. "qcmult_scale11,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11.."
|
|
line.long 0x8 "TWID_INCR_DELTA_FRAC,"
|
|
hexmask.long.word 0x8 0.--9. 1. "twid_incr_delta_frac,Used in complex multiplier mode 10 Delta Fractional frequency increment per param-set looping Instantaneous frequency is (TWIDINCR << 10) +TWID_INCR_DELTA_ FRAC*c c is current execution count of the parameter set."
|
|
line.long 0xC "RECWIN_RESET_SW,"
|
|
bitfld.long 0xC 0. "recwin_reset_sw,This resets the param set counter / execution counter used in Complex multiplier mode 8 . It s a self clearing bit." "0,1"
|
|
line.long 0x10 "TWID_INCR_DELTA_FRAC_RESET_SW,"
|
|
bitfld.long 0x10 0. "twid_incr_delta_frac_reset_sw,This resets the param set counter used in Complex multiplier mode 10 . It s a Self clearing bit" "0,1"
|
|
rgroup.long 0x4C4++0x3
|
|
line.long 0x0 "TWID_INCR_DELTA_FRAC_CLIP_STATUS,"
|
|
bitfld.long 0x0 0. "twid_incr_delta_frac_clip_status,Indicates the clip status for TWID_INCR_DELTA_FRAC accumulator" "0,1"
|
|
group.long 0x4C8++0x2B
|
|
line.long 0x0 "RECWIN_INIT_KVAL,"
|
|
hexmask.long.word 0x0 0.--11. 1. "recwin_init_kval,Indicates the initialization value of execution counter in recursive window mode . Execution counter value is initialized when recwin_reset_sw is 1'b1"
|
|
line.long 0x4 "CMULT_RESERVED_2,"
|
|
hexmask.long 0x4 0.--31. 1. "cmult_reserved_2,Reserved for future addition"
|
|
line.long 0x8 "CHAN_COMB_SIZE,"
|
|
hexmask.long.byte 0x8 0.--7. 1. "chan_comb_size,Number of samples after combination"
|
|
line.long 0xC "CHAN_COMB_VEC_0,"
|
|
hexmask.long 0xC 0.--31. 1. "chan_comb_vec_0,Channel combination MASK for 0 to 31 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
line.long 0x10 "CHAN_COMB_VEC_1,"
|
|
hexmask.long 0x10 0.--31. 1. "chan_comb_vec_1,Channel combination MASK for 32 to 63 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
line.long 0x14 "CHAN_COMB_VEC_2,"
|
|
hexmask.long 0x14 0.--31. 1. "chan_comb_vec_2,Channel combination MASK for 64 to 95 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
line.long 0x18 "CHAN_COMB_VEC_3,"
|
|
hexmask.long 0x18 0.--31. 1. "chan_comb_vec_3,Channel combination MASK for 96 to 127 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
line.long 0x1C "CHAN_COMB_VEC_4,"
|
|
hexmask.long 0x1C 0.--31. 1. "chan_comb_vec_4,Channel combination MASK for 128 to 159 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
line.long 0x20 "CHAN_COMB_VEC_5,"
|
|
hexmask.long 0x20 0.--31. 1. "chan_comb_vec_5,Channel combination MASK for 160 to 191 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
line.long 0x24 "CHAN_COMB_VEC_6,"
|
|
hexmask.long 0x24 0.--31. 1. "chan_comb_vec_6,Channel combination MASK for 192 to 223 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
line.long 0x28 "CHAN_COMB_VEC_7,"
|
|
hexmask.long 0x28 0.--31. 1. "chan_comb_vec_7,Channel combination MASK for 224 to 255 samples Vector indicating the samples indices that need to be combined. A 01 or 10 transition demarcates the groups. if CHAN_COMB_VEC = 0xF030000000000000 sums the first 4 samples and.."
|
|
rgroup.long 0x4F4++0x3
|
|
line.long 0x0 "CHANNEL_COMB_CLIP_STATUS,"
|
|
bitfld.long 0x0 0. "channel_comb_clip_status,Indicates the clip status of the channel combination" "0,1"
|
|
group.long 0x4F8++0x23
|
|
line.long 0x0 "ZERO_INSERT_NUM,"
|
|
hexmask.long.byte 0x0 0.--7. 1. "zero_insert_num,Number of zeros to be inserted in an iteration"
|
|
line.long 0x4 "ZERO_INSERT_MASK_0,"
|
|
hexmask.long 0x4 0.--31. 1. "zero_insert_mask_0,Zero insert mask for samples 0 to 31 A bit-field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
line.long 0x8 "ZERO_INSERT_MASK_1,"
|
|
hexmask.long 0x8 0.--31. 1. "zero_insert_mask_1,Zero insert mask for samples 32 to 63 A bit-field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
line.long 0xC "ZERO_INSERT_MASK_2,"
|
|
hexmask.long 0xC 0.--31. 1. "zero_insert_mask_2,Zero insert mask for samples 64 to 95 A bit-field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
line.long 0x10 "ZERO_INSERT_MASK_3,"
|
|
hexmask.long 0x10 0.--31. 1. "zero_insert_mask_3,Zero insert mask for samples 96 to 127 A bit-field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
line.long 0x14 "ZERO_INSERT_MASK_4,"
|
|
hexmask.long 0x14 0.--31. 1. "zero_insert_mask_4,Zero insert mask for samples 128 to 159 A bit-field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
line.long 0x18 "ZERO_INSERT_MASK_5,"
|
|
hexmask.long 0x18 0.--31. 1. "zero_insert_mask_5,Zero insert mask for samples 160 to 191 A bit-field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
line.long 0x1C "ZERO_INSERT_MASK_6,"
|
|
hexmask.long 0x1C 0.--31. 1. "zero_insert_mask_6,Zero insert mask for samples 192 to 223 A bit field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
line.long 0x20 "ZERO_INSERT_MASK_7,"
|
|
hexmask.long 0x20 0.--31. 1. "zero_insert_mask_7,Zero insert mask for samples 224 to 255 A bit-field of 0 inserts a zero at location based on bit-field index. 1 means the input is passed through. Up-stream and down-stream processing is stalled during the zero insertion"
|
|
repeat 4. (list 0x1 0x2 0x3 0x4)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x51C)++0x3
|
|
line.long 0x0 "ZERO_INSERT_RESERVED_$1,"
|
|
hexmask.long 0x0 0.--31. 1. "zero_insert_reserved_1,Reserved for future addition"
|
|
repeat.end
|
|
group.long 0x52C++0xB
|
|
line.long 0x0 "LFSR_SEED,"
|
|
hexmask.long 0x0 0.--28. 1. "lfsr_seed,Seed for LFSR (random pattern): For twiddle factor dithering there is an LFSR that is used whose seed value is loaded by writing to this 29-bit LFSRSEED register. The LFSRSEED register should be set to any non-zero value say 0x1234567"
|
|
line.long 0x4 "LFSR_LOAD,"
|
|
bitfld.long 0x4 0. "lfsr_load,Its self clearing bit . It should be set for loading the LFSR_SEED. It s a self clearing bit" "0,1"
|
|
line.long 0x8 "DITHER_TWID_EN,"
|
|
bitfld.long 0x8 0. "dither_twid_en,Twiddle factor dithering enable: This register-bit is used to enable and disable dithering of twiddle factors in the FFT. The twiddle factors are 24-bits wide (24-bits for each I and Q) but they are quantized to 21-bits before twiddle.." "0,1"
|
|
rgroup.long 0x538++0x3
|
|
line.long 0x0 "FFT_CLIP,"
|
|
hexmask.long.word 0x0 0.--12. 1. "fft_clip,FFT Clip Status (read-only): This is a read-only status register which indicates any saturation/clipping events that have happened in the FFT butterfly stages. Note that each of the individual butterfly stages in the FFT can be programmed to.."
|
|
group.long 0x53C++0x7
|
|
line.long 0x0 "CLR_FFTCLIP,"
|
|
bitfld.long 0x0 0. "clr_fftclip,Clear FFT Clip Status register: This register bit when set clears the FFTCLIP register. It s a self clearing bit" "0,1"
|
|
line.long 0x4 "CLR_CLIP_MISC,"
|
|
bitfld.long 0x4 0. "clr_clip_status,This clears the following clip register channel_comb_clip_status dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status.." "0,1"
|
|
rgroup.long 0x544++0x3
|
|
line.long 0x0 "IP_OP_FORMATTER_CLIP_STATUS,"
|
|
bitfld.long 0x0 16. "op_formatter_clip_status,Indicates the output formatter clip status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ip_formatter_clip_status,Indicates the input formatter clip status" "0,1"
|
|
repeat 3. (list 0x1 0x2 0x3)(list 0x0 0x4 0x8)
|
|
group.long ($2+0x548)++0x3
|
|
line.long 0x0 "FFT_RESERVED_$1,"
|
|
hexmask.long 0x0 0.--31. 1. "fft_reserved_1,Reserved for future addition"
|
|
repeat.end
|
|
rgroup.long 0x554++0x5F
|
|
line.long 0x0 "MAX1_VALUE,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "max1_value,These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of.."
|
|
line.long 0x4 "MAX2_VALUE,"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "max2_value,These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of.."
|
|
line.long 0x8 "MAX3_VALUE,"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "max3_value,These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of.."
|
|
line.long 0xC "MAX4_VALUE,"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "max4_value,These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of.."
|
|
line.long 0x10 "MAX1_INDEX,"
|
|
hexmask.long.word 0x10 0.--11. 1. "max1_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers."
|
|
line.long 0x14 "MAX2_INDEX,"
|
|
hexmask.long.word 0x14 0.--11. 1. "max2_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers."
|
|
line.long 0x18 "MAX3_INDEX,"
|
|
hexmask.long.word 0x18 0.--11. 1. "max3_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers."
|
|
line.long 0x1C "MAX4_INDEX,"
|
|
hexmask.long.word 0x1C 0.--11. 1. "max4_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers."
|
|
line.long 0x20 "I_SUM1_LSB,"
|
|
hexmask.long 0x20 0.--31. 1. "i_sum1_lsb,I Sum value 1 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x24 "I_SUM1_MSB,"
|
|
hexmask.long.byte 0x24 0.--3. 1. "i_sum1_msb,I Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x28 "I_SUM2_LSB,"
|
|
hexmask.long 0x28 0.--31. 1. "i_sum2_lsb,I Sum value 2 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x2C "I_SUM2_MSB,"
|
|
hexmask.long.byte 0x2C 0.--3. 1. "i_sum2_msb,I Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x30 "I_SUM3_LSB,"
|
|
hexmask.long 0x30 0.--31. 1. "i_sum3_lsb,I Sum value 3 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x34 "I_SUM3_MSB,"
|
|
hexmask.long.byte 0x34 0.--3. 1. "i_sum3_msb,I Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x38 "I_SUM4_LSB,"
|
|
hexmask.long 0x38 0.--31. 1. "i_sum4_lsb,I Sum value 4 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x3C "I_SUM4_MSB,"
|
|
hexmask.long.byte 0x3C 0.--3. 1. "i_sum4_msb,I Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x40 "Q_SUM1_LSB,"
|
|
hexmask.long 0x40 0.--31. 1. "q_sum1_lsb,Q Sum value 1 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x44 "Q_SUM1_MSB,"
|
|
hexmask.long.byte 0x44 0.--3. 1. "q_sum1_msb,Q Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x48 "Q_SUM2_LSB,"
|
|
hexmask.long 0x48 0.--31. 1. "q_sum2_lsb,Q Sum value 2 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x4C "Q_SUM2_MSB,"
|
|
hexmask.long.byte 0x4C 0.--3. 1. "q_sum2_msb,Q Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x50 "Q_SUM3_LSB,"
|
|
hexmask.long 0x50 0.--31. 1. "q_sum3_lsb,Q Sum value 3 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x54 "Q_SUM3_MSB,"
|
|
hexmask.long.byte 0x54 0.--3. 1. "q_sum3_msb,Q Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x58 "Q_SUM4_LSB,"
|
|
hexmask.long 0x58 0.--31. 1. "q_sum4_lsb,Q Sum value 4 LSB 32 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
line.long 0x5C "Q_SUM4_MSB,"
|
|
hexmask.long.byte 0x5C 0.--3. 1. "q_sum4_msb,Q Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations use statistics.."
|
|
group.long 0x5B4++0xF
|
|
line.long 0x0 "FFTSUMDIV,"
|
|
hexmask.long.byte 0x0 0.--4. 1. "fftsumdiv,Right-shifting for Sum statistic: This register specifies the number of bits to right-shift the sum statistic before it is written to destination memory. The internal sum statistic register is 36-bits wide (allowing 12 bits of MSB growth of the.."
|
|
line.long 0x4 "MAX2D_OFFSET_DIM1,"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "max2d_offset_dim1,Offset to be added to dimension 1 Maxima results. This offset will be applied to all the maxima results in the iteration dimension. Needs to be configured to 0 in case no offset is required."
|
|
line.long 0x8 "MAX2D_OFFSET_DIM2,"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "max2d_offset_dim2,Offset to be added to dimension 2 Maxima results. This offset will be applied to all the maxima results in the sample dimension. Needs to be configured to 0 in case no offset is required."
|
|
line.long 0xC "CDF_CNT_THRESH,"
|
|
hexmask.long.word 0xC 0.--11. 1. "cdf_cnt_thresh,This register is applicable in CDF_CNT_THRESH mode of operation. CDF is computed over the histogram till the value of the CDF just exceeds the CDF_CNT_THRESH specified by the user. This register can take values from 0 to 1023."
|
|
repeat 5. (list 0x1 0x2 0x3 0x4 0x5)(list 0x0 0x4 0x8 0xC 0x10)
|
|
group.long ($2+0x5C4)++0x3
|
|
line.long 0x0 "STATS_RESERVED_$1,"
|
|
hexmask.long 0x0 0.--31. 1. "stats_reserved_1,Future use"
|
|
repeat.end
|
|
rgroup.long 0x5D8++0x3
|
|
line.long 0x0 "CFAR_PEAKCNT,"
|
|
hexmask.long.word 0x0 0.--11. 1. "cfar_peakcnt,CFAR detected peak count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory when CFAR Engine is configured in Detected Peaks List mode. In the Detected Peaks List mode .."
|
|
group.long 0x5DC++0xB
|
|
line.long 0x0 "CFAR_DET_THR,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "cfar_det_thr,To be added"
|
|
line.long 0x4 "CFAR_TEST_REG,"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "cfar_test_reg,To be added"
|
|
line.long 0x8 "CFAR_THRESH,"
|
|
hexmask.long.tbyte 0x8 0.--17. 1. "cfar_thresh,Threshold scale factor: This register is used to specify the threshold scale factor. This value is used to either multiply or add to the surrounding noise average to determine the threshold used for detection of the present cell under.."
|
|
repeat 4. (list 0x1 0x2 0x3 0x4)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x5E8)++0x3
|
|
line.long 0x0 "CFAR_RESERVED_$1,"
|
|
hexmask.long 0x0 0.--31. 1. "cfar_reserved_1,Future use"
|
|
repeat.end
|
|
group.long 0x5F8++0xF
|
|
line.long 0x0 "CMP_EGE_K0123,"
|
|
hexmask.long.byte 0x0 24.--28. 1. "cmp_ege_k3,3th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "cmp_ege_k2,2th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "cmp_ege_k1,1th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "cmp_ege_k0,0th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
line.long 0x4 "CMP_EGE_K4567,"
|
|
hexmask.long.byte 0x4 24.--28. 1. "cmp_ege_k7,7th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "cmp_ege_k6,6th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "cmp_ege_k5,5th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "cmp_ege_k4,4th K-param value should be loaded here which would be used in the First-pass of EGE Compression"
|
|
line.long 0x8 "MEM_INIT_START,"
|
|
bitfld.long 0x8 14. "hist_odd_ram,writing 1'b1 would start the memory initialization for the Histogram memory 2 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "hist_even_ram,writing 1'b1 would start the memory initialization for the Histogram memory 1 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "per_iter_max_val_ram,writing 1'b1 would start the memory initialization for the 2D MAX per iteration RAM It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "per_sample_max_val_odd_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 2 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "per_sample_max_val_even_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 1 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "window_ram,writing 1'b1 would start the memory initialization for the window memory It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "param_ram,writing 1'b1 would start the memory initialization for the Param memory It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "dmem7,writing 1'b1 would start the memory initialization for the DMEM7 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "dmem6,writing 1'b1 would start the memory initialization for the DMEM6 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "dmem5,writing 1'b1 would start the memory initialization for the DMEM5 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "dmem4,writing 1'b1 would start the memory initialization for the DMEM4 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "dmem3,writing 1'b1 would start the memory initialization for the DMEM3 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "dmem2,writing 1'b1 would start the memory initialization for the DMEM2 It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "dmem1,writing 1'b1 would start the memory initialization for the DMEM1. It s a self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "dmem0,writing 1'b1 would start the memory initialization for the DMEM0 It s a self clearing bit" "0,1"
|
|
line.long 0xC "MEM_INIT_DONE,"
|
|
bitfld.long 0xC 14. "hist_odd_ram,Will be 1'b1 after cmpletion of memory initialization for hist_odd_ram" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "hist_even_ram,Will be 1'b1 after cmpletion of memory initialization for hist_even_ram" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "per_iteration_max_val_ram,Will be 1'b1 after cmpletion of memory initialization for per_iteration_max_val_ram" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "per_sample_max_val_odd_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_odd_ram" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "per_sample_max_val_even_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_even_ram" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "window_ram,Will be 1'b1 after cmpletion of memory initialization for window_ram" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "param_ram,Will be 1'b1 after cmpletion of memory initialization for param_ram" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "dmem7,Will be 1'b1 after cmpletion of memory initialization for dmem7" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "dmem6,Will be 1'b1 after cmpletion of memory initialization for dmem6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "dmem5,Will be 1'b1 after cmpletion of memory initialization for dmem5" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "dmem4,Will be 1'b1 after cmpletion of memory initialization for dmem4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "dmem3,Will be 1'b1 after cmpletion of memory initialization for dmem3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "dmem2,Will be 1'b1 after cmpletion of memory initialization for dmem2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "dmem1,Will be 1'b1 after cmpletion of memory initialization for dmem1" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "dmem0,Will be 1'b1 after cmpletion of memory initialization for dmem0" "0,1"
|
|
rgroup.long 0x608++0x3
|
|
line.long 0x0 "MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 14. "hist_odd_ram,Will be 1'b1 during memory initialization for hist_odd_ram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "hist_even_ram,Will be 1'b1 during memory initialization for hist_even_ram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "per_iteration_max_val_ram,Will be 1'b1 during memory initialization for per_iteration_max_val_ram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "per_sample_max_val_odd_ram,Will be 1'b1 during memory initialization for per_sample_max_val_odd_ram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "per_sample_max_val_even_ram,Will be 1'b1 during memory initialization for per_sample_max_val_even_ram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "window_ram,Will be 1'b1 during memory initialization for window_ram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "param_ram,Will be 1'b1 during memory initialization for param_ram" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "dmem7,Will be 1'b1 during memory initialization for dmem7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "dmem6,Will be 1'b1 during memory initialization for dmem6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "dmem5,Will be 1'b1 during memory initialization for dmem5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dmem4,Will be 1'b1 during memory initialization for dmem4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "dmem3,Will be 1'b1 during memory initialization for dmem3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "dmem2,Will be 1'b1 during memory initialization for dmem2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "dmem1,Will be 1'b1 during memory initialization for dmem1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "dmem0,Will be 1'b1 during memory initialization for dmem0" "0,1"
|
|
group.long 0x60C++0x17
|
|
line.long 0x0 "LM_THRESH_VAL,"
|
|
hexmask.long.word 0x0 16.--31. 1. "dimc_thresh_val,Threshold value configured for Dimension C"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "dimb_thresh_val,Threshold value configured for Dimension B"
|
|
line.long 0x4 "LM_2DSTATS_BASE_ADDR,"
|
|
hexmask.long.word 0x4 16.--27. 1. "base_addr_dimc,Base Address in Stats RAM for the Threshold values corresponding to dimension C"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "base_addr_dimb,Base Address in Stats RAM for the Threshold values corresponding to dimension B"
|
|
line.long 0x8 "HWA_SAFETY_EN,"
|
|
bitfld.long 0x8 3. "cfg_dmem_parity_en,Writing 1'b1 would enable the parity chekcer for the 8 DMEM memories" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "cfg_window_ram_parity_en,Writing 1'b1 enables parity for windowing RAM" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "cfg_fsm_lockstep_inv_en,Writing 1'b1 will invert the redundant FSM outputs. This can be used for selftest of FSM lockstep error interrupt. This bit is self clearing bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "cfg_fsm_lockstep_en,Writing 1'b1 would enable the lockstep logic for FSM" "0,1"
|
|
line.long 0xC "HWA_SAFETY_ERR_MASK,"
|
|
bitfld.long 0xC 9. "fsm_lockstep,When 1'b1 : FSM lockstep error is masked 1'b0 : FSM lockstep error is not masked" "?,1: FSM lockstep error is masked 1'b0 : FSM lockstep.."
|
|
newline
|
|
bitfld.long 0xC 8. "window_ram,When 1'b1 : window RAM parity error is masked 1'b0 : window RAM parity error is not masked" "?,1: window RAM parity error is masked 1'b0 : window.."
|
|
newline
|
|
bitfld.long 0xC 7. "dmem7,When 1'b1 : DMEM7 parity error is masked 1'b0 : DMEM7 parity error is not masked" "?,1: DMEM7 parity error is masked 1'b0 : DMEM7 parity.."
|
|
newline
|
|
bitfld.long 0xC 6. "dmem6,When 1'b1 : DMEM6 parity error is masked 1'b0 : DMEM6 parity error is not masked" "?,1: DMEM6 parity error is masked 1'b0 : DMEM6 parity.."
|
|
newline
|
|
bitfld.long 0xC 5. "dmem5,When 1'b1 : DMEM5 parity error is masked 1'b0 : DMEM5 parity error is not masked" "?,1: DMEM5 parity error is masked 1'b0 : DMEM5 parity.."
|
|
newline
|
|
bitfld.long 0xC 4. "dmem4,When 1'b1 : DMEM4 parity error is masked 1'b0 : DMEM4 parity error is not masked" "?,1: DMEM4 parity error is masked 1'b0 : DMEM4 parity.."
|
|
newline
|
|
bitfld.long 0xC 3. "dmem3,When 1'b1 : DMEM3 parity error is masked 1'b0 : DMEM3 parity error is not masked" "?,1: DMEM3 parity error is masked 1'b0 : DMEM3 parity.."
|
|
newline
|
|
bitfld.long 0xC 2. "dmem2,When 1'b1 : DMEM2 parity error is masked 1'b0 : DMEM2 parity error is not masked" "?,1: DMEM2 parity error is masked 1'b0 : DMEM2 parity.."
|
|
newline
|
|
bitfld.long 0xC 1. "dmem1,When 1'b1 : DMEM1 parity error is masked 1'b0 : DMEM1 parity error is not masked" "?,1: DMEM1 parity error is masked 1'b0 : DMEM1 parity.."
|
|
newline
|
|
bitfld.long 0xC 0. "dmem0,When 1'b1 : DMEM0 parity error is masked 1'b0 : DMEM0 parity error is not masked" "?,1: DMEM0 parity error is masked 1'b0 : DMEM0 parity.."
|
|
line.long 0x10 "HWA_SAFETY_ERR_STATUS,"
|
|
bitfld.long 0x10 9. "fsm_lockstep,Indicates the FSM lockstep error (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "window_ram,Indicates the parity error in window RAM (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "dmem7,Indicates the parity error in dmem7 (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "dmem6,Indicates the parity error in dmem6 (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "dmem5,Indicates the parity error in dmem5 (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "dmem4,Indicates the parity error in dmem4 (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "dmem3,Indicates the parity error in dmem3 (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "dmem2,Indicates the parity error in dmem2 (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "dmem1,Indicates the parity error in dmem1 (Masked status)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "dmem0,Indicates the parity error in dmem0 (Masked status)" "0,1"
|
|
line.long 0x14 "HWA_SAFETY_ERR_STATUS_RAW,"
|
|
bitfld.long 0x14 9. "fsm_lockstep,Indicates the FSM lockstep error (raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 9" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "window_ram,Indicates the parity error in window RAM(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "dmem7,Indicates the parity error in dmem7(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 7" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "dmem6,Indicates the parity error in dmem6(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 6" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "dmem5,Indicates the parity error in dmem5(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "dmem4,Indicates the parity error in dmem4(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 4" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "dmem3,Indicates the parity error in dmem3(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "dmem2,Indicates the parity error in dmem2(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "dmem1,Indicates the parity error in dmem1(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 1" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "dmem0,Indicates the parity error in dmem0(raw status). Set irrespective of HWA_SAFETY_ERR_MASK bit 0" "0,1"
|
|
rgroup.long 0x624++0x23
|
|
line.long 0x0 "HWA_SAFETY_DMEM0_ERR_ADDR,"
|
|
hexmask.long.word 0x0 0.--9. 1. "dmem0_err_addr,Captures the address where parity error occured for dmem0"
|
|
line.long 0x4 "HWA_SAFETY_DMEM1_ERR_ADDR,"
|
|
hexmask.long.word 0x4 0.--9. 1. "dmem1_err_addr,Captures the address where parity error occured for dmem1"
|
|
line.long 0x8 "HWA_SAFETY_DMEM2_ERR_ADDR,"
|
|
hexmask.long.word 0x8 0.--9. 1. "dmem2_err_addr,Captures the address where parity error occured for dmem2"
|
|
line.long 0xC "HWA_SAFETY_DMEM3_ERR_ADDR,"
|
|
hexmask.long.word 0xC 0.--9. 1. "dmem3_err_addr,Captures the address where parity error occured for dmem3"
|
|
line.long 0x10 "HWA_SAFETY_DMEM4_ERR_ADDR,"
|
|
hexmask.long.word 0x10 0.--9. 1. "dmem4_err_addr,Captures the address where parity error occured for dmem4"
|
|
line.long 0x14 "HWA_SAFETY_DMEM5_ERR_ADDR,"
|
|
hexmask.long.word 0x14 0.--9. 1. "dmem5_err_addr,Captures the address where parity error occured for dmem5"
|
|
line.long 0x18 "HWA_SAFETY_DMEM6_ERR_ADDR,"
|
|
hexmask.long.word 0x18 0.--9. 1. "dmem6_err_addr,Captures the address where parity error occured for dmem6"
|
|
line.long 0x1C "HWA_SAFETY_DMEM7_ERR_ADDR,"
|
|
hexmask.long.word 0x1C 0.--9. 1. "dmem7_err_addr,Captures the address where parity error occured for dmem7"
|
|
line.long 0x20 "HWA_SAFETY_WINDOW_RAM_ERR_ADDR,"
|
|
hexmask.long.word 0x20 0.--10. 1. "window_ram_err_addr,Captures the address where parity error occured for window RAM"
|
|
group.long 0x648++0x3
|
|
line.long 0x0 "MEM_ACCESS_ERR_STATUS,"
|
|
bitfld.long 0x0 7. "dmem7,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem7 at the same time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "dmem6,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem6 at the same time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "dmem5,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem5 at the same time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dmem4,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem4 at the same time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "dmem3,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem3 at the same time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "dmem2,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem2 at the same time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "dmem1,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem1 at the same time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "dmem0,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem0 at the same time" "0,1"
|
|
rgroup.long 0x64C++0x13
|
|
line.long 0x0 "LOOP_CNT,"
|
|
hexmask.long.word 0x0 16.--27. 1. "loop_cnt_alt,Loop count for alternate thread"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "loop_cnt,Loop count"
|
|
line.long 0x4 "PARAMADDR,"
|
|
hexmask.long.byte 0x4 0.--5. 1. "paramaddr,Index of the current parameter set being executed from PARAM RAM ."
|
|
line.long 0x8 "PARAMADDR_CPUINTR0,"
|
|
hexmask.long.byte 0x8 0.--5. 1. "paramaddr,Index of the parameter set when PARAM_DONE_INTR0 is generated"
|
|
line.long 0xC "PARAMADDR_CPUINTR1,"
|
|
hexmask.long.byte 0xC 0.--5. 1. "paramaddr,Index of the parameter set when PARAM_DONE_INTR1 is generated"
|
|
line.long 0x10 "FSM_STATE,"
|
|
bitfld.long 0x10 0.--2. "fsm_state,Current state of the state machine" "0,1,2,3,4,5,6,7"
|
|
group.long 0x660++0xF
|
|
line.long 0x0 "SINGLE_STEP_EN,"
|
|
bitfld.long 0x0 0. "single_step_en,Single step enable 1'b1 : the state machine executes one parameter-set at a time and wait for the single step trigger every time" "?,1: the state machine executes one parameter-set at.."
|
|
line.long 0x4 "SINGLE_STEP_TRIG,"
|
|
bitfld.long 0x4 0. "single_step_trig,This is a self clearing sofware trigger bit . When single_step_en is 1 the state machine executes one parameter-set at a time and wait for the single step trigger every time" "0,1"
|
|
line.long 0x8 "HWA_DMEM_A_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "HWA_DMEM_A_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0xC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0xC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x670++0x3
|
|
line.long 0x0 "HWA_DMEM_A_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
rgroup.long 0x678++0x3
|
|
line.long 0x0 "HWA_DMEM_A_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x67C++0x7
|
|
line.long 0x0 "HWA_DMEM_B_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HWA_DMEM_B_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x684++0x3
|
|
line.long 0x0 "HWA_DMEM_B_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
rgroup.long 0x68C++0x3
|
|
line.long 0x0 "HWA_DMEM_B_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_wph,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "DSS_MCRC"
|
|
base ad:0x83300000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
|
|
rbitfld.long 0x0 31. "NU12,Reserved" "0,1"
|
|
rbitfld.long 0x0 30. "NU11,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 29. "NU10,Reserved" "0,1"
|
|
rbitfld.long 0x0 27.--28. "NU9,Reserved" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x0 25.--26. "NU8,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x0 24. "NU7,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 23. "NU6,Reserved" "0,1"
|
|
rbitfld.long 0x0 22. "NU5,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 21. "NU4,Reserved" "0,1"
|
|
rbitfld.long 0x0 19.--20. "NU3,Reserved" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x0 17.--18. "NU2,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x0 16. "NU1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
|
|
bitfld.long 0x0 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
|
|
bitfld.long 0x0 11.--12. "CH2_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]} 000 - CRC-64 001 - CRC-16 010 - CRC-32 100 - VDA CAN SAE-J1850 CRC-8 101 - H2F Autosar 4.0 110 - CASTAGNOLI iSCSI 111 / 011 - E2E Profile 4" "?,1: CRC-16 010 - CRC-32 100,?,?"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "CH2_DW_SEL,CRC Data Size select. 000 - 64 bit Data Size 001 - 16 bit Data Size 010 - 32 Bit Data Size" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a '0'. 0 = PSA Signature Register.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
|
|
newline
|
|
bitfld.long 0x0 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
|
|
bitfld.long 0x0 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
|
|
bitfld.long 0x0 3.--4. "CH1_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]} 000 - CRC-64 001 - CRC-16 010 - CRC-32 100 - VDA CAN SAE-J1850 CRC-8 101 - H2F Autosar 4.0 110 - CASTAGNOLI iSCSI 111 / 011 - E2E Profile 4" "?,1: CRC-16 010 - CRC-32 100,?,?"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "CH1_DW_SEL,CRC Data Size select. 000 - 64 bit Data Size 001 - 16 bit Data Size 010 - 32 Bit Data Size" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a '0'. 0 = PSA Signature Register.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CRC_CTRL1,Contains power down control bit"
|
|
hexmask.long 0x0 1.--31. 1. "Reserved1,Reserved"
|
|
bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode 1 = MCRC is in power down mode" "0: MCRC is not in power down mode,1: MCRC is in power down mode"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
|
|
hexmask.long.byte 0x0 26.--31. 1. "Reserved5,Reserved"
|
|
rbitfld.long 0x0 24.--25. "NU14,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 18.--23. 1. "Reserved4,Reserved"
|
|
rbitfld.long 0x0 16.--17. "NU13,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--15. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode: 0 0 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: reserved 1,1: Full-CPU mode,?,?"
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|
newline
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rbitfld.long 0x0 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable. When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable"
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|
newline
|
|
rbitfld.long 0x0 2.--3. "Reserved1,Reserved" "0,1,2,3"
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|
bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode: 0 0 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: reserved 1,1: Full-CPU mode,?,?"
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|
group.long 0x18++0x3
|
|
line.long 0x0 "CRC_INTS,Write one to a bit to enable a interrupt"
|
|
rbitfld.long 0x0 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
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|
rbitfld.long 0x0 28. "NU22,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 27. "NU21,Reserved" "0,1"
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|
rbitfld.long 0x0 26. "NU20,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 25. "NU19,Reserved" "0,1"
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|
hexmask.long.byte 0x0 21.--24. 1. "Reserved4,Reserved"
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|
newline
|
|
rbitfld.long 0x0 20. "NU18,Reserved" "0,1"
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|
rbitfld.long 0x0 19. "NU17,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 18. "NU16,Reserved" "0,1"
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|
rbitfld.long 0x0 17. "NU15,Reserved" "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 13.--16. 1. "Reserved3,Reserved"
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|
bitfld.long 0x0 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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|
newline
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bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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|
bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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|
newline
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bitfld.long 0x0 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
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|
hexmask.long.byte 0x0 5.--8. 1. "Reserved2,Reserved"
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|
newline
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bitfld.long 0x0 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
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|
bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
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newline
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bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
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|
bitfld.long 0x0 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
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|
newline
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rbitfld.long 0x0 0. "Reserved1,Reserved" "0,1"
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|
group.long 0x20++0x3
|
|
line.long 0x0 "CRC_INTR,Write one to a bit to disable a interrupt"
|
|
rbitfld.long 0x0 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
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|
rbitfld.long 0x0 28. "NU30,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 27. "NU29,Reserved" "0,1"
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|
rbitfld.long 0x0 26. "NU28,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 25. "NU27,Reserved" "0,1"
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|
hexmask.long.byte 0x0 21.--24. 1. "Reserved4,Reserved"
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|
newline
|
|
rbitfld.long 0x0 20. "NU26,Reserved" "0,1"
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|
rbitfld.long 0x0 19. "NU25,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 18. "NU24,Reserved" "0,1"
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|
rbitfld.long 0x0 17. "NU23,Reserved" "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 13.--16. 1. "Reserved3,Reserved"
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|
bitfld.long 0x0 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt disable"
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|
newline
|
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bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 =.." "0: Has no effect,1: Underrun Interrupt disable"
|
|
bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt disable"
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|
newline
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bitfld.long 0x0 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt disable"
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|
hexmask.long.byte 0x0 5.--8. 1. "Reserved2,Reserved"
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|
newline
|
|
bitfld.long 0x0 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt disable"
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|
bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 =.." "0: Has no effect,1: Underrun Interrupt disable"
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newline
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bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt disable"
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bitfld.long 0x0 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt disable"
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newline
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rbitfld.long 0x0 0. "Reserved1,Reserved" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
|
|
rbitfld.long 0x0 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
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|
rbitfld.long 0x0 28. "NU38,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 27. "NU37,Reserved" "0,1"
|
|
rbitfld.long 0x0 26. "NU36,Reserved" "0,1"
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|
newline
|
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rbitfld.long 0x0 25. "NU35,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 21.--24. 1. "Reserved4,Reserved"
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|
newline
|
|
rbitfld.long 0x0 20. "NU34,Reserved" "0,1"
|
|
rbitfld.long 0x0 19. "NU33,Reserved" "0,1"
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|
newline
|
|
rbitfld.long 0x0 18. "NU32,Reserved" "0,1"
|
|
rbitfld.long 0x0 17. "NU31,Reserved" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 13.--16. 1. "Reserved3,Reserved"
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|
bitfld.long 0x0 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
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newline
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bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
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bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
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newline
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bitfld.long 0x0 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
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hexmask.long.byte 0x0 5.--8. 1. "Reserved2,Reserved"
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newline
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bitfld.long 0x0 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
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bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
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newline
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bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
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bitfld.long 0x0 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
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newline
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rbitfld.long 0x0 0. "Reserved1,Reserved" "0,1"
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|
group.long 0x30++0x3
|
|
line.long 0x0 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
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hexmask.long.tbyte 0x0 8.--31. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x0 0.--7. 1. "OFSTREG,CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register auto- matically clear the respective interrupt flag. Please reference Table 1-3. for details."
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|
rgroup.long 0x38++0x3
|
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line.long 0x0 "CRC_BUSY,Contains the busy flag for each channel"
|
|
hexmask.long.byte 0x0 25.--31. 1. "Reserved4,Reserved"
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|
bitfld.long 0x0 24. "NU40,Reserved" "0,1"
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|
newline
|
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hexmask.long.byte 0x0 17.--23. 1. "Reserved3,Reserved"
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|
bitfld.long 0x0 16. "NU39,Reserved" "0,1"
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|
newline
|
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hexmask.long.byte 0x0 9.--15. 1. "Reserved2,Reserved"
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|
bitfld.long 0x0 8. "Ch2_BUSY,Ch2_BUSY. During AUTO mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 1.--7. 1. "Reserved1,Reserved"
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|
bitfld.long 0x0 0. "CH1_BUSY,CH1_BUSY. During AUTO mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
|
|
hexmask.long.word 0x0 20.--31. 1. "Reserved1,Reserved"
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|
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."
|
|
line.long 0x4 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
|
|
hexmask.long.word 0x4 16.--31. 1. "Reserved1,Reserved"
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|
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."
|
|
line.long 0x8 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
|
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hexmask.long.word 0x8 16.--31. 1. "Reserved1,Reserved"
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|
hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.."
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|
line.long 0xC "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Reserved1,Reserved"
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hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
|
|
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "PSA_SIGREGL1,Channel 1 PSA signature low register"
|
|
hexmask.long 0x0 0.--31. 1. "PSASIG1_31_0,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register."
|
|
line.long 0x4 "PSA_SIGREGH1,Channel 1 PSA signature high register"
|
|
hexmask.long 0x4 0.--31. 1. "PSA_SIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register."
|
|
line.long 0x8 "CRC_REGL1,Channel 1 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "CRC1_31_0,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] regis- ter."
|
|
line.long 0xC "CRC_REGH1,Channel 1 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "CRC1_63_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] regis- ter."
|
|
rgroup.long 0x70++0xF
|
|
line.long 0x0 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
|
|
hexmask.long 0x0 0.--31. 1. "PSASECSIG1_31_0,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register."
|
|
line.long 0x4 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
|
|
hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register."
|
|
line.long 0x8 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
|
|
hexmask.long 0x8 0.--31. 1. "RAW_DATA1_31_0,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."
|
|
line.long 0xC "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
|
|
hexmask.long 0xC 0.--31. 1. "RAW_DATA1_63_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
|
|
hexmask.long.word 0x0 20.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."
|
|
line.long 0x4 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
|
|
hexmask.long.word 0x4 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."
|
|
line.long 0x8 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
|
|
hexmask.long.word 0x8 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.."
|
|
line.long 0xC "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
|
|
line.long 0x10 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."
|
|
group.long 0xA0++0xF
|
|
line.long 0x0 "PSA_SIGREGL2,Channel 2 PSA signature low register"
|
|
hexmask.long 0x0 0.--31. 1. "PSASIG2_31_0,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register."
|
|
line.long 0x4 "PSA_SIGREGH2,Channel 2 PSA signature high register"
|
|
hexmask.long 0x4 0.--31. 1. "PSA_SIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register."
|
|
line.long 0x8 "CRC_REGL2,Channel 2 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "CRC2_31_0,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] regis- ter."
|
|
line.long 0xC "CRC_REGH2,Channel 2 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] regis- ter."
|
|
rgroup.long 0xB0++0x23
|
|
line.long 0x0 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
|
|
hexmask.long 0x0 0.--31. 1. "PSASECSIG2_31_0,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register."
|
|
line.long 0x4 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
|
|
hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register."
|
|
line.long 0x8 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
|
|
hexmask.long 0x8 0.--31. 1. "RAW_DATA2_31_0,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."
|
|
line.long 0xC "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
|
|
hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."
|
|
line.long 0x10 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
|
|
hexmask.long.word 0x10 20.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x10 0.--19. 1. "NU41,Reserved"
|
|
line.long 0x14 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
|
|
hexmask.long.word 0x14 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "NU42,Reserved"
|
|
line.long 0x18 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
|
|
hexmask.long.word 0x18 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "NU43,Reserved"
|
|
line.long 0x1C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "NU44,Reserved"
|
|
line.long 0x20 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x20 24.--31. 1. "Reserved1,Reserved"
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|
hexmask.long.tbyte 0x20 0.--23. 1. "NU45,Reserved"
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|
rgroup.long 0xE0++0x33
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|
line.long 0x0 "PSA_SIGREGL3,Channel 3 PSA signature low register"
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|
hexmask.long 0x0 0.--31. 1. "NU46,Reserved"
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|
line.long 0x4 "PSA_SIGREGH3,Channel 3 PSA signature high register"
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|
hexmask.long 0x4 0.--31. 1. "NU47,Reserved"
|
|
line.long 0x8 "CRC_REGL3,Channel 3 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "NU48,Reserved"
|
|
line.long 0xC "CRC_REGH3,Channel 3 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "NU49,Reserved"
|
|
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
|
|
hexmask.long 0x10 0.--31. 1. "NU50,Reserved"
|
|
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
|
|
hexmask.long 0x14 0.--31. 1. "NU51,Reserved"
|
|
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
|
|
hexmask.long 0x18 0.--31. 1. "NU52,Reserved"
|
|
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NU53,Reserved"
|
|
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
|
|
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
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hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
|
|
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
|
|
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
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|
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
|
|
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
|
|
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
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hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
|
|
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
|
|
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
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|
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
|
|
rgroup.long 0x120++0x1F
|
|
line.long 0x0 "PSA_SIGREGL4,Channel 4 PSA signature low register"
|
|
hexmask.long 0x0 0.--31. 1. "NU59,Reserved"
|
|
line.long 0x4 "PSA_SIGREGH4,Channel 4 PSA signature high register"
|
|
hexmask.long 0x4 0.--31. 1. "NU60,Reserved"
|
|
line.long 0x8 "CRC_REGL4,Channel 4 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "NU61,Reserved"
|
|
line.long 0xC "CRC_REGH4,Channel 4 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "NU62,Reserved"
|
|
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
|
|
hexmask.long 0x10 0.--31. 1. "NU63,Reserved"
|
|
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
|
|
hexmask.long 0x14 0.--31. 1. "NU64,Reserved"
|
|
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
|
|
hexmask.long 0x18 0.--31. 1. "NU65,Reserved"
|
|
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NU66,Reserved"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
|
|
hexmask.long 0x0 3.--31. 1. "NU67,Reserved"
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|
bitfld.long 0x0 2. "MEn,MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled"
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newline
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bitfld.long 0x0 1. "DTCMEn,DTCMEn. Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.."
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bitfld.long 0x0 0. "ITCMEn,ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled" "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled"
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x0 "MCRC_RESERVED,0x144 to 0x1FF is reserved area."
|
|
hexmask.long 0x0 0.--31. 1. "NU68,0x144 to 0x1FF is reserved area."
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|
tree.end
|
|
tree "DSS_PCR"
|
|
base ad:0x6F78000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
|
|
bitfld.long 0x0 31. "PCS31_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 30. "PCS30_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 29. "PCS29_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
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bitfld.long 0x0 28. "PCS28_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
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bitfld.long 0x0 27. "PCS27_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 26. "PCS26_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
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bitfld.long 0x0 25. "PCS25_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
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|
bitfld.long 0x0 24. "PCS24_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 23. "PCS23_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 22. "PCS22_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
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bitfld.long 0x0 21. "PCS21_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 20. "PCS20_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
|
bitfld.long 0x0 19. "PCS19_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 18. "PCS18_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 17. "PCS17_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
|
bitfld.long 0x0 16. "PCS16_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
|
bitfld.long 0x0 15. "PCS15_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 14. "PCS14_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 13. "PCS13_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 12. "PCS12_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 11. "PCS11_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 10. "PCS10_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 9. "PCS9_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
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bitfld.long 0x0 8. "PCS8_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
|
bitfld.long 0x0 7. "PCS7_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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|
newline
|
|
bitfld.long 0x0 6. "PCS6_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 5. "PCS5_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 4. "PCS4_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 3. "PCS3_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCS2_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 1. "PCS1_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 0. "PCS0_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
line.long 0x4 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
|
|
bitfld.long 0x4 31. "PCS63_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 30. "PCS62_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 29. "PCS61_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 28. "PCS60_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 27. "PCS59_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 26. "PCS58_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 25. "PCS57_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 24. "PCS56_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 23. "PCS55_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 22. "PCS54_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 21. "PCS53_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 20. "PCS52_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 19. "PCS51_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 18. "PCS50_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 17. "PCS49_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 16. "PCS48_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 15. "PCS47_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 14. "PCS46_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 13. "PCS45_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 12. "PCS44_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 11. "PCS43_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 10. "PCS42_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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|
newline
|
|
bitfld.long 0x4 9. "PCS41_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
|
|
newline
|
|
bitfld.long 0x4 8. "PCS40_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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|
newline
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bitfld.long 0x4 7. "PCS39_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 6. "PCS38_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 5. "PCS37_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 4. "PCS36_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 3. "PCS35_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 2. "PCS34_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 1. "PCS33_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 0. "PCS32_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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group.long 0x10++0x7
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line.long 0x0 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
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bitfld.long 0x0 31. "PCS31_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 30. "PCS30_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 29. "PCS29_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 28. "PCS28_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 27. "PCS27_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 26. "PCS26_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 25. "PCS25_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 24. "PCS24_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 23. "PCS23_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 22. "PCS22_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 21. "PCS21_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 20. "PCS20_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 19. "PCS19_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 18. "PCS18_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 17. "PCS17_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 16. "PCS16_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 15. "PCS15_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 14. "PCS14_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 13. "PCS13_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 12. "PCS12_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 11. "PCS11_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 10. "PCS10_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 9. "PCS9_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 8. "PCS8_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 7. "PCS7_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 6. "PCS6_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 5. "PCS5_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 4. "PCS4_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 3. "PCS3_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 2. "PCS2_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 1. "PCS1_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 0. "PCS0_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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line.long 0x4 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
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bitfld.long 0x4 31. "PCS63_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 30. "PCS62_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 29. "PCS61_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 28. "PCS60_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 27. "PCS59_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 26. "PCS58_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 25. "PCS57_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 24. "PCS56_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 23. "PCS55_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 22. "PCS54_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 21. "PCS53_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 20. "PCS52_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 19. "PCS51_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 18. "PCS50_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 17. "PCS49_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 16. "PCS48_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 15. "PCS47_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 14. "PCS46_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 13. "PCS45_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 12. "PCS44_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 11. "PCS43_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 10. "PCS42_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 9. "PCS41_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 8. "PCS40_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 7. "PCS39_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 6. "PCS38_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 5. "PCS37_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 4. "PCS36_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 3. "PCS35_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 2. "PCS34_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 1. "PCS33_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 0. "PCS32_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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group.long 0x20++0xF
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line.long 0x0 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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line.long 0x4 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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line.long 0x8 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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|
newline
|
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bitfld.long 0x8 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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bitfld.long 0x8 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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line.long 0xC "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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group.long 0x40++0xF
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line.long 0x0 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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line.long 0x4 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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line.long 0x8 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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|
newline
|
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bitfld.long 0x8 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
|
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bitfld.long 0x8 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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line.long 0xC "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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group.long 0x60++0x7
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line.long 0x0 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
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bitfld.long 0x0 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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line.long 0x4 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
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bitfld.long 0x4 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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group.long 0x70++0x7
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line.long 0x0 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
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bitfld.long 0x0 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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line.long 0x4 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
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bitfld.long 0x4 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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group.long 0x80++0xF
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line.long 0x0 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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line.long 0x4 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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line.long 0x8 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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line.long 0xC "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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group.long 0xA0++0xF
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line.long 0x0 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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line.long 0x4 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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line.long 0x8 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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line.long 0xC "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
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bitfld.long 0xC 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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group.long 0xC0++0x7
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line.long 0x0 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
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hexmask.long 0x0 1.--31. 1. "Reserved,Reserved"
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bitfld.long 0x0 0. "PD_PWRDWN_SET,Readable in both user and privileged modes. 1 = Clock to the debug frame needs to be powered down. 0 = Clock to the debug frame needs to be powered up. Writable only in privileged mode 1 = Bit 0 when written 1 will get set in both.." "0: Has no effect,1: Bit 0 when written 1"
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line.long 0x4 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
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hexmask.long 0x4 1.--31. 1. "Reserved,Reserved"
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bitfld.long 0x4 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the debug frame needs to be powered down. 0 = The clock to the debug frame needs to be powered up. Writable only in privileged mode 1 = Bit 0 when written 1 will get cleared in.." "0: Has no effect,1: Bit 0 when written 1"
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group.long 0x200++0xB
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line.long 0x0 "MSTIDWRENA,MasterID Protection Write Enable Register"
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hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x0 0.--3. 1. "MSTIDREG_WRENA,Readable in both user and privileged modes. 1010 = All master-id registers are unlocked and available for write. others = Writes to all master-id registers are locked. Writable only in privileged mode 1010 = Writes to master-id registers.."
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line.long 0x4 "MSTIDENA,MasterID Protection Enable Register"
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hexmask.long 0x4 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x4 0.--3. 1. "MSTID_CHK_EN,Readable in both user and privileged modes. Writable only in privileged mode 1010 = Enable the master-id feature check. others = Master-id check is disabled."
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line.long 0x8 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
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hexmask.long.tbyte 0x8 12.--31. 1. "Reserved2,Reserved"
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hexmask.long.byte 0x8 8.--11. 1. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode. Any error in compare logic is indicated through AERROR output from PCR. Readable in both.."
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hexmask.long.byte 0x8 4.--7. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x8 0.--3. 1. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic. Readable in both user and privileged modes. Writable only in privileged mode 1010 = Master-id compare diagnostic mode is.."
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group.long 0x300++0x2E3
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line.long 0x0 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
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hexmask.long.word 0x0 16.--31. 1. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x0 0.--15. 1. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x4 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
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hexmask.long.word 0x4 16.--31. 1. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x4 0.--15. 1. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x8 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
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hexmask.long.word 0x8 16.--31. 1. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x8 0.--15. 1. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0xC "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
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hexmask.long.word 0xC 16.--31. 1. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0xC 0.--15. 1. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
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hexmask.long.word 0x10 16.--31. 1. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x10 0.--15. 1. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
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hexmask.long.word 0x14 16.--31. 1. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x14 0.--15. 1. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
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hexmask.long.word 0x18 16.--31. 1. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x18 0.--15. 1. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
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hexmask.long.word 0x1C 16.--31. 1. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x1C 0.--15. 1. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
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hexmask.long.word 0x20 16.--31. 1. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x20 0.--15. 1. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
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hexmask.long.word 0x24 16.--31. 1. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x24 0.--15. 1. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
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hexmask.long.word 0x28 16.--31. 1. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x28 0.--15. 1. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
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hexmask.long.word 0x2C 16.--31. 1. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x2C 0.--15. 1. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
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hexmask.long.word 0x30 16.--31. 1. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x30 0.--15. 1. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
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hexmask.long.word 0x34 16.--31. 1. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x34 0.--15. 1. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
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hexmask.long.word 0x38 16.--31. 1. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x38 0.--15. 1. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
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hexmask.long.word 0x3C 16.--31. 1. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x3C 0.--15. 1. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
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hexmask.long.word 0x40 16.--31. 1. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x40 0.--15. 1. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
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hexmask.long.word 0x44 16.--31. 1. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x44 0.--15. 1. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
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hexmask.long.word 0x48 16.--31. 1. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x48 0.--15. 1. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
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hexmask.long.word 0x4C 16.--31. 1. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x4C 0.--15. 1. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
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hexmask.long.word 0x50 16.--31. 1. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x50 0.--15. 1. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
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hexmask.long.word 0x54 16.--31. 1. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x54 0.--15. 1. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
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hexmask.long.word 0x58 16.--31. 1. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x58 0.--15. 1. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
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hexmask.long.word 0x5C 16.--31. 1. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x5C 0.--15. 1. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
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hexmask.long.word 0x60 16.--31. 1. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x60 0.--15. 1. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
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hexmask.long.word 0x64 16.--31. 1. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x64 0.--15. 1. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
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hexmask.long.word 0x68 16.--31. 1. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x68 0.--15. 1. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
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hexmask.long.word 0x6C 16.--31. 1. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x6C 0.--15. 1. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
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hexmask.long.word 0x70 16.--31. 1. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x70 0.--15. 1. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
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hexmask.long.word 0x74 16.--31. 1. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x74 0.--15. 1. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
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hexmask.long.word 0x78 16.--31. 1. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x78 0.--15. 1. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
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hexmask.long.word 0x7C 16.--31. 1. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x7C 0.--15. 1. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
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hexmask.long.word 0x80 16.--31. 1. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x80 0.--15. 1. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
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hexmask.long.word 0x84 16.--31. 1. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x84 0.--15. 1. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
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hexmask.long.word 0x88 16.--31. 1. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x88 0.--15. 1. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
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hexmask.long.word 0x8C 16.--31. 1. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x8C 0.--15. 1. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
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hexmask.long.word 0x90 16.--31. 1. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x90 0.--15. 1. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
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hexmask.long.word 0x94 16.--31. 1. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x94 0.--15. 1. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
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hexmask.long.word 0x98 16.--31. 1. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0x98 0.--15. 1. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
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hexmask.long.word 0x9C 16.--31. 1. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0x9C 0.--15. 1. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
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hexmask.long.word 0xA0 16.--31. 1. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xA0 0.--15. 1. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
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hexmask.long.word 0xA4 16.--31. 1. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xA4 0.--15. 1. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
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hexmask.long.word 0xA8 16.--31. 1. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xA8 0.--15. 1. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
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hexmask.long.word 0xAC 16.--31. 1. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xAC 0.--15. 1. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
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hexmask.long.word 0xB0 16.--31. 1. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xB0 0.--15. 1. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
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hexmask.long.word 0xB4 16.--31. 1. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xB4 0.--15. 1. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
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hexmask.long.word 0xB8 16.--31. 1. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xB8 0.--15. 1. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
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hexmask.long.word 0xBC 16.--31. 1. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xBC 0.--15. 1. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
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hexmask.long.word 0xC0 16.--31. 1. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xC0 0.--15. 1. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
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hexmask.long.word 0xC4 16.--31. 1. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xC4 0.--15. 1. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
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hexmask.long.word 0xC8 16.--31. 1. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xC8 0.--15. 1. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
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hexmask.long.word 0xCC 16.--31. 1. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xCC 0.--15. 1. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
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hexmask.long.word 0xD0 16.--31. 1. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xD0 0.--15. 1. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
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hexmask.long.word 0xD4 16.--31. 1. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xD4 0.--15. 1. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
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hexmask.long.word 0xD8 16.--31. 1. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xD8 0.--15. 1. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
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hexmask.long.word 0xDC 16.--31. 1. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xDC 0.--15. 1. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
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hexmask.long.word 0xE0 16.--31. 1. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xE0 0.--15. 1. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
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hexmask.long.word 0xE4 16.--31. 1. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xE4 0.--15. 1. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
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hexmask.long.word 0xE8 16.--31. 1. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xE8 0.--15. 1. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
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hexmask.long.word 0xEC 16.--31. 1. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xEC 0.--15. 1. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
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hexmask.long.word 0xF0 16.--31. 1. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xF0 0.--15. 1. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
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hexmask.long.word 0xF4 16.--31. 1. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xF4 0.--15. 1. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
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hexmask.long.word 0xF8 16.--31. 1. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xF8 0.--15. 1. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
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hexmask.long.word 0xFC 16.--31. 1. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xFC 0.--15. 1. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
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hexmask.long.word 0x100 16.--31. 1. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x100 0.--15. 1. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
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hexmask.long.word 0x104 16.--31. 1. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x104 0.--15. 1. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
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hexmask.long.word 0x108 16.--31. 1. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x108 0.--15. 1. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
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hexmask.long.word 0x10C 16.--31. 1. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x10C 0.--15. 1. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
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hexmask.long.word 0x110 16.--31. 1. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x110 0.--15. 1. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
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hexmask.long.word 0x114 16.--31. 1. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x114 0.--15. 1. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
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hexmask.long.word 0x118 16.--31. 1. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x118 0.--15. 1. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
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hexmask.long.word 0x11C 16.--31. 1. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x11C 0.--15. 1. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
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hexmask.long.word 0x120 16.--31. 1. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x120 0.--15. 1. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
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hexmask.long.word 0x124 16.--31. 1. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x124 0.--15. 1. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
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hexmask.long.word 0x128 16.--31. 1. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x128 0.--15. 1. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
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hexmask.long.word 0x12C 16.--31. 1. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x12C 0.--15. 1. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
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hexmask.long.word 0x130 16.--31. 1. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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newline
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hexmask.long.word 0x130 0.--15. 1. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
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hexmask.long.word 0x134 16.--31. 1. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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newline
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hexmask.long.word 0x134 0.--15. 1. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
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hexmask.long.word 0x138 16.--31. 1. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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newline
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hexmask.long.word 0x138 0.--15. 1. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
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hexmask.long.word 0x13C 16.--31. 1. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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newline
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hexmask.long.word 0x13C 0.--15. 1. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
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hexmask.long.word 0x140 16.--31. 1. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x140 0.--15. 1. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
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hexmask.long.word 0x144 16.--31. 1. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x144 0.--15. 1. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
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hexmask.long.word 0x148 16.--31. 1. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x148 0.--15. 1. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
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hexmask.long.word 0x14C 16.--31. 1. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x14C 0.--15. 1. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
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hexmask.long.word 0x150 16.--31. 1. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x150 0.--15. 1. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
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hexmask.long.word 0x154 16.--31. 1. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x154 0.--15. 1. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
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hexmask.long.word 0x158 16.--31. 1. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x158 0.--15. 1. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
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hexmask.long.word 0x15C 16.--31. 1. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x15C 0.--15. 1. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
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hexmask.long.word 0x160 16.--31. 1. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x160 0.--15. 1. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
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hexmask.long.word 0x164 16.--31. 1. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x164 0.--15. 1. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
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hexmask.long.word 0x168 16.--31. 1. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x168 0.--15. 1. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
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hexmask.long.word 0x16C 16.--31. 1. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x16C 0.--15. 1. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
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hexmask.long.word 0x170 16.--31. 1. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x170 0.--15. 1. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
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hexmask.long.word 0x174 16.--31. 1. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x174 0.--15. 1. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
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hexmask.long.word 0x178 16.--31. 1. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x178 0.--15. 1. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
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hexmask.long.word 0x17C 16.--31. 1. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x17C 0.--15. 1. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
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hexmask.long.word 0x180 16.--31. 1. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x180 0.--15. 1. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
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hexmask.long.word 0x184 16.--31. 1. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x184 0.--15. 1. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
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hexmask.long.word 0x188 16.--31. 1. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x188 0.--15. 1. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
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hexmask.long.word 0x18C 16.--31. 1. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x18C 0.--15. 1. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
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hexmask.long.word 0x190 16.--31. 1. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x190 0.--15. 1. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
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hexmask.long.word 0x194 16.--31. 1. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x194 0.--15. 1. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
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|
hexmask.long.word 0x198 16.--31. 1. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x198 0.--15. 1. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
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hexmask.long.word 0x19C 16.--31. 1. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x19C 0.--15. 1. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
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|
hexmask.long.word 0x1A0 16.--31. 1. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1A0 0.--15. 1. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
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hexmask.long.word 0x1A4 16.--31. 1. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1A4 0.--15. 1. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
|
|
hexmask.long.word 0x1A8 16.--31. 1. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1A8 0.--15. 1. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
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|
hexmask.long.word 0x1AC 16.--31. 1. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1AC 0.--15. 1. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
|
|
hexmask.long.word 0x1B0 16.--31. 1. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1B0 0.--15. 1. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
|
|
hexmask.long.word 0x1B4 16.--31. 1. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1B4 0.--15. 1. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
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|
hexmask.long.word 0x1B8 16.--31. 1. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1B8 0.--15. 1. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
|
|
hexmask.long.word 0x1BC 16.--31. 1. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1BC 0.--15. 1. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
|
|
hexmask.long.word 0x1C0 16.--31. 1. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1C0 0.--15. 1. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
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|
hexmask.long.word 0x1C4 16.--31. 1. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1C4 0.--15. 1. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
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|
hexmask.long.word 0x1C8 16.--31. 1. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1C8 0.--15. 1. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
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hexmask.long.word 0x1CC 16.--31. 1. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1CC 0.--15. 1. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
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hexmask.long.word 0x1D0 16.--31. 1. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1D0 0.--15. 1. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
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hexmask.long.word 0x1D4 16.--31. 1. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1D4 0.--15. 1. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
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hexmask.long.word 0x1D8 16.--31. 1. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1D8 0.--15. 1. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
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hexmask.long.word 0x1DC 16.--31. 1. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1DC 0.--15. 1. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
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hexmask.long.word 0x1E0 16.--31. 1. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1E0 0.--15. 1. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
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hexmask.long.word 0x1E4 16.--31. 1. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1E4 0.--15. 1. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
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hexmask.long.word 0x1E8 16.--31. 1. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1E8 0.--15. 1. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
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hexmask.long.word 0x1EC 16.--31. 1. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1EC 0.--15. 1. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
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hexmask.long.word 0x1F0 16.--31. 1. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1F0 0.--15. 1. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
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hexmask.long.word 0x1F4 16.--31. 1. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1F4 0.--15. 1. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
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hexmask.long.word 0x1F8 16.--31. 1. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1F8 0.--15. 1. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
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hexmask.long.word 0x1FC 16.--31. 1. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1FC 0.--15. 1. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
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hexmask.long.word 0x200 16.--31. 1. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x200 0.--15. 1. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
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hexmask.long.word 0x204 16.--31. 1. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x204 0.--15. 1. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
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hexmask.long.word 0x208 16.--31. 1. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x208 0.--15. 1. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
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hexmask.long.word 0x20C 16.--31. 1. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x20C 0.--15. 1. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
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hexmask.long.word 0x210 16.--31. 1. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x210 0.--15. 1. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
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hexmask.long.word 0x214 16.--31. 1. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
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hexmask.long.word 0x214 0.--15. 1. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
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hexmask.long.word 0x218 16.--31. 1. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x218 0.--15. 1. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
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|
hexmask.long.word 0x21C 16.--31. 1. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x21C 0.--15. 1. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
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|
hexmask.long.word 0x220 16.--31. 1. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x220 0.--15. 1. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
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hexmask.long.word 0x224 16.--31. 1. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x224 0.--15. 1. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
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hexmask.long.word 0x228 16.--31. 1. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
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hexmask.long.word 0x228 0.--15. 1. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
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hexmask.long.word 0x22C 16.--31. 1. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x22C 0.--15. 1. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
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hexmask.long.word 0x230 16.--31. 1. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
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hexmask.long.word 0x230 0.--15. 1. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
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hexmask.long.word 0x234 16.--31. 1. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
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hexmask.long.word 0x234 0.--15. 1. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
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|
hexmask.long.word 0x238 16.--31. 1. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
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hexmask.long.word 0x238 0.--15. 1. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
|
|
hexmask.long.word 0x23C 16.--31. 1. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x23C 0.--15. 1. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
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hexmask.long.word 0x240 16.--31. 1. "PCS1MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x240 0.--15. 1. "PCS0MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
|
|
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
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|
hexmask.long.word 0x244 16.--31. 1. "PCS3MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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|
newline
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hexmask.long.word 0x244 0.--15. 1. "PCS2MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
|
|
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
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|
hexmask.long.word 0x248 16.--31. 1. "PCS5MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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|
newline
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hexmask.long.word 0x248 0.--15. 1. "PCS4MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
|
|
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
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|
hexmask.long.word 0x24C 16.--31. 1. "PCS7MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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|
newline
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hexmask.long.word 0x24C 0.--15. 1. "PCS6MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
|
|
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
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|
hexmask.long.word 0x250 16.--31. 1. "PCS9MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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|
newline
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hexmask.long.word 0x250 0.--15. 1. "PCS8MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
|
|
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
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|
hexmask.long.word 0x254 16.--31. 1. "PCS11MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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|
newline
|
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hexmask.long.word 0x254 0.--15. 1. "PCS10MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
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hexmask.long.word 0x258 16.--31. 1. "PCS13MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x258 0.--15. 1. "PCS12MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
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hexmask.long.word 0x25C 16.--31. 1. "PCS15MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x25C 0.--15. 1. "PCS14MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
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hexmask.long.word 0x260 16.--31. 1. "PCS17MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x260 0.--15. 1. "PCS16MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
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hexmask.long.word 0x264 16.--31. 1. "PCS19MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x264 0.--15. 1. "PCS18MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
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hexmask.long.word 0x268 16.--31. 1. "PCS21MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x268 0.--15. 1. "PCS20MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
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hexmask.long.word 0x26C 16.--31. 1. "PCS23MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x26C 0.--15. 1. "PCS22MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
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hexmask.long.word 0x270 16.--31. 1. "PCS25MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x270 0.--15. 1. "PCS24MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
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hexmask.long.word 0x274 16.--31. 1. "PCS27MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x274 0.--15. 1. "PCS26MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
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hexmask.long.word 0x278 16.--31. 1. "PCS29MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x278 0.--15. 1. "PCS28MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
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hexmask.long.word 0x27C 16.--31. 1. "PCS31MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x27C 0.--15. 1. "PCS30MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
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hexmask.long.word 0x280 16.--31. 1. "PCS33MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x280 0.--15. 1. "PCS32MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
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hexmask.long.word 0x284 16.--31. 1. "PCS35MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x284 0.--15. 1. "PCS34MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
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hexmask.long.word 0x288 16.--31. 1. "PCS37MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x288 0.--15. 1. "PCS36MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
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hexmask.long.word 0x28C 16.--31. 1. "PCS39MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x28C 0.--15. 1. "PCS38MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
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hexmask.long.word 0x290 16.--31. 1. "PCS41MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x290 0.--15. 1. "PCS40MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
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hexmask.long.word 0x294 16.--31. 1. "PCS43MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x294 0.--15. 1. "PCS42MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
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hexmask.long.word 0x298 16.--31. 1. "PCS45MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x298 0.--15. 1. "PCS44MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
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hexmask.long.word 0x29C 16.--31. 1. "PCS47MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x29C 0.--15. 1. "PCS46MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
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hexmask.long.word 0x2A0 16.--31. 1. "PCS49MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2A0 0.--15. 1. "PCS48MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
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hexmask.long.word 0x2A4 16.--31. 1. "PCS51MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2A4 0.--15. 1. "PCS50MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
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hexmask.long.word 0x2A8 16.--31. 1. "PCS53MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2A8 0.--15. 1. "PCS52MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
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hexmask.long.word 0x2AC 16.--31. 1. "PCS55MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2AC 0.--15. 1. "PCS54MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
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hexmask.long.word 0x2B0 16.--31. 1. "PCS57MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2B0 0.--15. 1. "PCS56MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
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hexmask.long.word 0x2B4 16.--31. 1. "PCS59MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2B4 0.--15. 1. "PCS58MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
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hexmask.long.word 0x2B8 16.--31. 1. "PCS61MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2B8 0.--15. 1. "PCS60MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
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hexmask.long.word 0x2BC 16.--31. 1. "PCS63MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2BC 0.--15. 1. "PCS62MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
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hexmask.long.word 0x2C0 16.--31. 1. "PPCS1MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2C0 0.--15. 1. "PPCS0MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
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hexmask.long.word 0x2C4 16.--31. 1. "PPCS3MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2C4 0.--15. 1. "PPCS2MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
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hexmask.long.word 0x2C8 16.--31. 1. "PPCS5MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2C8 0.--15. 1. "PPCS4MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
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hexmask.long.word 0x2CC 16.--31. 1. "PPCS7MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2CC 0.--15. 1. "PPCS6MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
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hexmask.long.word 0x2D0 16.--31. 1. "PPCS9MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2D0 0.--15. 1. "PPCS8MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
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hexmask.long.word 0x2D4 16.--31. 1. "PPCS11MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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hexmask.long.word 0x2D4 0.--15. 1. "PPCS10MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
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hexmask.long.word 0x2D8 16.--31. 1. "PPCS13MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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hexmask.long.word 0x2D8 0.--15. 1. "PPCS12MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
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hexmask.long.word 0x2DC 16.--31. 1. "PPCS15MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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hexmask.long.word 0x2DC 0.--15. 1. "PPCS14MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
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hexmask.long 0x2E0 0.--31. 1. "PCREXT_MSTID,These bits sets the permission for maximum of 16 masters to address the external PCR frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both user and privileged modes. 1 = The memory mapped in.."
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tree.end
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tree "DSS_RCM"
|
|
base ad:0x6000000
|
|
rgroup.long 0x0++0x3
|
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line.long 0x0 "PID,PID register"
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hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
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hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
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newline
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bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
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|
repeat 3. (list 0x0 0x1 0x3)(list 0x0 0x4 0xC)
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "HW_REG$1,"
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|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser"
|
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repeat.end
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PREVIOUS_NAME,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser"
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "DSP_PD_CTRL,"
|
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bitfld.long 0x0 4. "proc_halt,Controls the unhalting on the processor during the power-up sequence Write 1 : The DSP is kept in halt state at the end of the power up sequence. The L2 memories can now be initialised and loaded before setting this bit to 0 unhalting the.." "0: The processor is unhalted at the end of the..,1: The DSP is kept in halt state at the end of the.."
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bitfld.long 0x0 0. "interrupt_mask,Masks interrupts to the DSP. Write 1 : Mask interrupts to the DSP before powering off the DSP. When masked any interrupts are now stored in the Missed event register. Write 0 : Send the interrupts to the DSP after power on." "0: Send the interrupts to the DSP after power on,1: Mask interrupts to the DSP before powering off.."
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line.long 0x4 "DSP_PD_TRIGGER_WAKUP,"
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bitfld.long 0x4 0. "wakeup_trigger,Write pulse bit field: Trigger Power Up of the DSP. Write 1 : Triggers DSP power up sequence" "?,1: Triggers DSP power up sequence"
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|
line.long 0x8 "DSP_PD_TRIGGER_SLEEP,"
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|
bitfld.long 0x8 0. "sleep_trigger,Write pulse bit field: Trigger Power Down of the DSP. Write 1 : Triggers DSP power down sequence" "?,1: Triggers DSP power down sequence"
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|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "DSP_PD_STATUS,"
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|
bitfld.long 0x0 8. "pwrsm_dbg_ovrd,Status bit indicating if there is an override for the DSP from Debug SubSystem. 0 : No override from DebugSS 1 : Override from DebugSS" "0: No override from DebugSS,1: Override from DebugSS"
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|
newline
|
|
bitfld.long 0x0 4.--5. "pd_status,Power Mode status of DSP 00 : Powered OFF 01 : Transitioning from OFF to ON state 10 : Transitioning from ON to OFF state 11 : Powered ON" "0: Powered OFF,1: Transitioning from OFF to ON state,?,?"
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|
newline
|
|
bitfld.long 0x0 0. "proc_halted,Processor is halted" "0,1"
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|
group.long 0x24++0x7
|
|
line.long 0x0 "DSP_PD_CTRL_MISC0,"
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|
hexmask.long.byte 0x0 24.--29. 1. "pwrsm_grst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GRSTN during DSP Power-up sequence. Max allowed value is 31."
|
|
newline
|
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hexmask.long.byte 0x0 18.--23. 1. "pwrsm_porrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of POR during DSP Power-up sequence. Max allowed value is 31."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--17. 1. "pwrsm_lrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of LRSTN during DSP Power-up sequence. Max allowed value is 31."
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|
newline
|
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hexmask.long.byte 0x0 6.--11. 1. "pwrsm_grst_assertcnt,TI Internal Feature No of cycles to wait after assertion of GRSTN during DSP Power-up sequence. Max allowed value is 31."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "pwrsm_porrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of POR during DSP Power-up sequence. Max allowed value is 31."
|
|
line.long 0x4 "DSP_PD_CTRL_MISC1,"
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|
bitfld.long 0x4 24.--26. "iso_sync_bypass,HW RnD reserved. Do not Touch - Only for debug purpose" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x4 20.--22. "rst_sync_bypass,HW RnD reserved. Do not Touch - Only for debug purpose" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 18. "pwrsm_lresetout_mask,TI Internal Feature 1:mask lresetout from DSPin FSM" "?,1: mask lresetout from DSPin FSM"
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|
newline
|
|
hexmask.long.byte 0x4 12.--17. 1. "pwrsm_isoen_assertcnt,TI Internal Feature No of cycles to wait after assertion of ISO_ENABLE during GEM power-down sequence. Max allowed value is 31."
|
|
newline
|
|
hexmask.long.byte 0x4 6.--11. 1. "pwrsm_clkstop_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GEM_CLK_STOP_REQ during GEM Power-up sequence. Max allowed value is 31."
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|
newline
|
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hexmask.long.byte 0x4 0.--5. 1. "pwrsm_lrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of LRSTN during DSP Power-up sequence. Max allowed value is 31."
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|
rgroup.long 0x2C++0x3
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|
line.long 0x0 "DSP_PD_STATUS_MISC0,"
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|
bitfld.long 0x0 17. "pwrsm_lrstout,TI Internal Feature Lreset output indication from GEM" "0,1"
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|
newline
|
|
bitfld.long 0x0 16. "pwrsm_c66_clkstop_ack,TI Internal Feature Clock stop request ack from GEM" "0,1"
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|
newline
|
|
bitfld.long 0x0 15. "pwrsm_sdma_async2scr_clkstop_ack,TI Internal Feature SDMA slave disable Done from clock stop ack from the master port of the async bridge present in the SDMA port." "0,1"
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|
newline
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bitfld.long 0x0 14. "pwrsm_sdma_async2rcm_clkstop_req,TI Internal Feature SDMA Slave disable Ack from Interconnect. This is from the clock stop req signal coming from the slave port of the async bridge in SDMA." "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "pwrsm_sdma_scr2async_clkstop_req,TI Internal Feature Clock Stop request from SCR to SDMA Async Bridge" "0,1"
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|
newline
|
|
bitfld.long 0x0 12. "pwrsm_mem_agoodout,TI Internal Feature Memory AGOOD Output from GEM (synchronized to Bus clock)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "pwrsm_mem_aonout,TI Internal Feature Memory AON Output from GEM (synchronized to Bus clock)" "0,1"
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|
newline
|
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bitfld.long 0x0 10. "pwrsm_mem_pgoodout,TI Internal Feature Memory PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "pwrsm_mem_ponout,TI Internal Feature Memory PON Output from DSP (synchronized to Bus clock)" "0,1"
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|
newline
|
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bitfld.long 0x0 8. "pwrsm_pgoodout,TI Internal Feature Logic PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
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newline
|
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bitfld.long 0x0 7. "pwrsm_ponout,TI Internal Feature Logic PON Output from DSP (synchronized to Bus clock)" "0,1"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "state,This is the internal state of the DSP power State machine. Curretnly value of 13 needs to be polled to confirm we we can now download code to the L2 memory before unhalting the processor. Plan to change this in TPR and provide a single bit to poll.."
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group.long 0x30++0xB
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line.long 0x0 "DSP_PD_WAKEUP_MASK0,"
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hexmask.long 0x0 0.--31. 1. "wakeup_mask0,Bit level mask for each of the wakeup source bits [31:0] 1 : Masked 0 : Unmasked"
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line.long 0x4 "DSP_PD_WAKEUP_MASK1,"
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hexmask.long 0x4 0.--31. 1. "wakeup_mask1,Bit level mask for each of the wakeup source bits [63:32] 1 : Masked 0 : Unmasked."
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line.long 0x8 "DSP_PD_WAKEUP_MASK2,"
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hexmask.long 0x8 0.--31. 1. "wakeup_mask2,Bit level mask for each of the wakeup source bits [95:64] 1 : Masked 0 : Unmasked."
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repeat 3. (list 0x0 0x1 0x2)(list 0x0 0x4 0x8)
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rgroup.long ($2+0x3C)++0x3
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line.long 0x0 "DSP_PD_WAKEUP_STATUS$1,"
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hexmask.long 0x0 0.--31. 1. "wakeup_status0,Wakeup source status bits [31:0]"
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repeat.end
|
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group.long 0x48++0x17
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line.long 0x0 "DSP_PD_WAKEUP_STATUS0_CLR,"
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|
hexmask.long 0x0 0.--31. 1. "wakeup_status0_clr,Write pulse bit field: Clear bit for wakeup source status bits [31:0]. Write 0x1 to clear the corrsponding status bit : Its a wspecial access type write to this field will generate a pulse"
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line.long 0x4 "DSP_PD_WAKEUP_STATUS1_CLR,"
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hexmask.long 0x4 0.--31. 1. "wakeup_status1_clr,Write pulse bit field: Clear bit for wakeup source status bits [63:32]. Write 0x1 to clear the corrsponding status bit : Its a wspecial access type write to this field will generate a pulse"
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line.long 0x8 "DSP_PD_WAKEUP_STATUS2_CLR,"
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hexmask.long 0x8 0.--31. 1. "wakeup_status2_clr,Write pulse bit field: Clear bit for wakeup source status bits [95:64]. Write 0x1 to clear the corrsponding status bit : Its a wspecial access type write to this field will generate a pulse"
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line.long 0xC "DSP_PD_MISSED_EVENT_MASK0,"
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hexmask.long 0xC 0.--31. 1. "missed_event_mask0,Bit level mask for each of the missed events before getting pushed into DSP. Corresponds to Event lines[31:0] 1 : Masked 0 : Unmasked."
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line.long 0x10 "DSP_PD_MISSED_EVENT_MASK1,"
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hexmask.long 0x10 0.--31. 1. "missed_event_mask1,Bit level mask for each of the missed events before getting pushed into DSP. Corresponds to Event lines[63:32] 1 : Masked 0 : Unmasked."
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line.long 0x14 "DSP_PD_MISSED_EVENT_MASK2,"
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hexmask.long 0x14 0.--31. 1. "missed_event_mask2,Bit level mask for each of the missed events before getting pushed into DSP. Corresponds to Event lines[95:64] 1 : Masked 0 : Unmasked."
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rgroup.long 0x60++0xF
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line.long 0x0 "DSP_PD_MISSED_EVENT_STATUS0,"
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hexmask.long 0x0 0.--31. 1. "missed_event_status0,Missed events monitor status for interrupts [31:0]. Interrupts to DSP that are masked by INTERRUPT_MASK register field are captured in this register"
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line.long 0x4 "DSP_PD_MISSED_EVENT_STATUS1,"
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hexmask.long 0x4 0.--31. 1. "missed_event_status1,Missed events monitor status for interrupts [63:32] Interrupts to DSP that are masked by INTERRUPT_MASK register field are captured in this register"
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|
line.long 0x8 "DSP_PD_MISSED_EVENT_STATUS2,"
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|
hexmask.long 0x8 0.--31. 1. "missed_event_status2,Missed events monitor status for interrupts [95:64] Interrupts to DSP that are masked by INTERRUPT_MASK register field are captured in this register"
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|
line.long 0xC "DSP_RST_CAUSE,"
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hexmask.long.byte 0xC 16.--23. 1. "por_cause,DSP POR reset Bitwise Indication : Bit 0 : Por Reset Bit 1 : Sub system Reset from TOPRCM Bit 2 : Reset from DSS_RCM::DSS_DSP_RST_CTRL Bit 3 : Reset from Power FSM Bit 4 : Reset from STC FSM"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "grst_cause,DSP Greset Bitwise Indication : Bit 0 : Por Reset Bit 1 : Sub system Reset from TOPRCM Bit 2 : Reset from DSS_RCM::DSS_DSP_RST_CTRL Bit 3 : Reset from Power FSM Bit 4 : Reset from STC FSM"
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|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "lrst_cause,DSP Lreset Bitwise Indication : Bit 0 : Por Reset Bit 1 : Sub system Reset from TOPRCM Bit 2 : Reset from DSS_RCM::DSS_DSP_RST_CTRL Bit 3 : Reset from Debugss Bit 4 : Reset from Power FSM Bit 5 : Reset from STC FSM"
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group.long 0x70++0x7
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line.long 0x0 "DSP_RST_CAUSE_CLR,"
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|
bitfld.long 0x0 0. "clear,Write pulse bit field: Write 0x1 to clear the reset cause register for any previous resets : Its a wspecial access type write to this field will generate a pulse" "0,1"
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|
line.long 0x4 "DSP_STC_PBIST_CTRL,"
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hexmask.long.byte 0x4 16.--21. 1. "pbist_tmode_vlct_assertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after asserting GEM TMODE VLCT signal before proceeding to the next state. Max allowed value is 31."
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newline
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hexmask.long.byte 0x4 10.--15. 1. "pbist_tmode_vlct_deassertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after De-asserting GEM TMODE VLCT signal before proceeding to the next state. Max allowed value is 31."
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|
newline
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|
hexmask.long.byte 0x4 6.--9. 1. "pbist_selftest_key,[4:1] DSP PBIST SELFTEST KEY = 4'b1010"
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|
newline
|
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bitfld.long 0x4 5. "stc_b2b_en,Enables back to Back STC.Needs to be set to 1 for self test" "0,1"
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|
newline
|
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bitfld.long 0x4 4. "stc_clk_stp_ack_mask,Mask bit for ignoring the clock stop ack from GEM. This will be used for ignoring clock stop ack during boot-up. 1 --> Ignore clock stop ack from GEM. 0 --> Wait for clock stop ack from GEM after giving clock stop request." "0: Wait for clock stop ack from GEM after giving..,1: Ignore clock stop ack from GEM"
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|
newline
|
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bitfld.long 0x4 3. "proc_halt,Configuration to halt the state machine before the final de-assertion of LRST to enable program download. 1 --> Halt 0 --> Proceed." "0: Proceed,1: Halt"
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|
newline
|
|
bitfld.long 0x4 2. "stc_boot_en,Enable GEM STC during GEM power UP" "0,1"
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|
newline
|
|
bitfld.long 0x4 0.--1. "mode_enable,Enable for PBIST and STC. 00 - Reserved 01 --> STC only 10 --> PBIST only 11 --> PBIST followed by STC" "0: Reserved,1: STC only 10,?,?"
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|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "DSP_STC_PBIST_STATUS,"
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|
hexmask.long.byte 0x0 2.--7. 1. "stc_pbist_sm_status,PBIST status from GEM. undefined - Fail Indication undefined - Done indication"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "pbist_status,Current state of STC PBIST state machine" "0,1,2,3"
|
|
group.long 0x7C++0x57
|
|
line.long 0x0 "DSP_STC_PBIST_CTRL_MISC0,"
|
|
hexmask.long.word 0x0 16.--31. 1. "byp_value,DSP PBIST STC misc Control"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "byp_en,DSP PBIST STC misc Control"
|
|
line.long 0x4 "DSP_STC_PBIST_CTRL_MISC1,"
|
|
hexmask.long.byte 0x4 4.--9. 1. "sm_ovr_val,TI Internal Register.Reserved for HW RnD"
|
|
newline
|
|
bitfld.long 0x4 3. "sm_ovr_en,TI Internal Register.Reserved for HW RnD" "0,1"
|
|
line.long 0x8 "DSP_STC_PBIST_START,"
|
|
bitfld.long 0x8 0. "sm_trig,Write pulse bit field: Trigger pulse for the STC PBIST state machine. This is a self-clearing pulse. : Its a wspecial access type write to this field will generate a pulse" "0,1"
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|
line.long 0xC "DSP_STC_PBIST_STATUS_CLR,"
|
|
bitfld.long 0xC 0. "clear,Write pulse bit field: Clear bit for PBIST Status : Its a wspecial access type write to this field will generate a pulse" "0,1"
|
|
line.long 0x10 "DSS_DSP_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS DSP. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x14 "DSS_HWA_CLK_SRC_SEL,"
|
|
bitfld.long 0x14 0.--2. "clksrcsel,Select line for selecting source clock for DSS HWA. Data should be loaded as multibit. Write 3'b000 : TOPRCM_CR5_CLK Write 3'b111 : TOPRCM_SYS_CLK" "0: TOPRCM_CR5_CLK Write 3'b111 : TOPRCM_SYS_CLK,?,?,?,?,?,?,?"
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|
line.long 0x18 "DSS_RTIA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x18 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS_RTIA. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x1C "DSS_RTIB_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS RTIB. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x20 "DSS_WDT_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS Watchdog. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock.."
|
|
line.long 0x24 "DSS_SCIA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS SCIA. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x28 "DSS_DSP_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x28 0.--11. 1. "clkdiv,Divider value for DSS DSP selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x2C "DSS_RTIA_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x2C 0.--11. 1. "clkdiv,Divider value for DSS RTIA selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x30 "DSS_RTIB_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x30 0.--11. 1. "clkdiv,Divider value for DSS RTIB selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x34 "DSS_WDT_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x34 0.--11. 1. "clkdiv,Divider value for DSS Watchdog selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x38 "DSS_SCIA_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x38 0.--11. 1. "clkdiv,Divider value for DSS SCIA selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x3C "DSS_DSP_CLK_GATE,"
|
|
bitfld.long 0x3C 0.--2. "gated,Clock gatring config for DSS DSP. Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x40 "DSS_HWA_CLK_GATE,"
|
|
bitfld.long 0x40 0.--2. "gated,Clock gatring config for DSS HWA Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x44 "DSS_RTIA_CLK_GATE,"
|
|
bitfld.long 0x44 0.--2. "gated,Clock gatring config for DSS RTA Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x48 "DSS_RTIB_CLK_GATE,"
|
|
bitfld.long 0x48 0.--2. "gated,Clock gatring config for DSS RTIB Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x4C "DSS_WDT_CLK_GATE,"
|
|
bitfld.long 0x4C 0.--2. "gated,Clock gatring config for DSS Watchdog Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x50 "DSS_SCIA_CLK_GATE,"
|
|
bitfld.long 0x50 0.--2. "gated,Clock gatring config for DSS SCIA Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x54 "DSS_CBUFF_CLK_GATE,"
|
|
bitfld.long 0x54 0.--2. "gated,Clock gatring config for DSS SCIA Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x17
|
|
line.long 0x0 "DSS_DSP_CLK_STATUS,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS DSP Clock"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS DSP Clock"
|
|
line.long 0x4 "DSS_HWA_CLK_STATUS,"
|
|
bitfld.long 0x4 0.--1. "clkinuse,Status shows the source clock slected for DSS HWA Clock" "0,1,2,3"
|
|
line.long 0x8 "DSS_RTIA_CLK_STATUS,"
|
|
hexmask.long.byte 0x8 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIA Clock"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIA Clock"
|
|
line.long 0xC "DSS_RTIB_CLK_STATUS,"
|
|
hexmask.long.byte 0xC 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIB Clock"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIB Clock"
|
|
line.long 0x10 "DSS_WDT_CLK_STATUS,"
|
|
hexmask.long.byte 0x10 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS Watchdog Clock"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS Watchdog Clock"
|
|
line.long 0x14 "DSS_SCIA_CLK_STATUS,"
|
|
hexmask.long.byte 0x14 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS SCIA Clock"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS SCIA Clock"
|
|
group.long 0xEC++0x37
|
|
line.long 0x0 "DSS_DSP_RST_CTRL,"
|
|
bitfld.long 0x0 8.--10. "assert_local,Local Reset control for DSS DSP Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more details Write 3'b111 : Reset is.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "assert_global,Global Reset control forDSS DSP Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more details Write 3'b111 : Reset is.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "assert_por,Power on Reset control for DSS DSP Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more details Write 3'b111 : Reset is.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
line.long 0x4 "DSS_ESM_RST_CTRL,"
|
|
bitfld.long 0x4 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS ESM" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "DSS_SCIA_RST_CTRL,"
|
|
bitfld.long 0x8 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS SCIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DSS_RTIA_RST_CTRL,"
|
|
bitfld.long 0xC 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS RTIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "DSS_RTIB_RST_CTRL,"
|
|
bitfld.long 0x10 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS RTIB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "DSS_WDT_RST_CTRL,"
|
|
bitfld.long 0x14 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS Watchdog" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "DSS_DCCA_RST_CTRL,"
|
|
bitfld.long 0x18 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS DCCA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "DSS_DCCB_RST_CTRL,"
|
|
bitfld.long 0x1C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS DCCB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "DSS_MCRC_RST_CTRL,"
|
|
bitfld.long 0x20 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of Device/IP before configuring. Writing 3'b11 will assert reset for DSS MCRC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "DSP_DFT_DIV_CTRL,"
|
|
bitfld.long 0x24 4.--6. "clk_disable,DSP DFT Control for clock_disable. Multibit implementation. Write 0x0 to enable Write 0x7 to diable" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--3. 1. "div_factor,DSP DFT Control for div factor"
|
|
line.long 0x28 "DSS_DSP_L2_PD_CTRL,"
|
|
bitfld.long 0x28 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x28 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x28 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "DSS_L3_BANKA0_PD_CTRL,"
|
|
bitfld.long 0x2C 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x2C 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x2C 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "DSS_L3_BANKA1_PD_CTRL,"
|
|
bitfld.long 0x30 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x30 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x30 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
line.long 0x34 "DSS_L3_BANKA2_PD_CTRL,"
|
|
bitfld.long 0x34 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x34 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x34 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
group.long 0x128++0xB
|
|
line.long 0x0 "DSS_L3_BANKB0_PD_CTRL,"
|
|
bitfld.long 0x0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_L3_BANKB1_PD_CTRL,"
|
|
bitfld.long 0x4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "DSS_L3_BANKB2_PD_CTRL,"
|
|
bitfld.long 0x8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
group.long 0x138++0x7
|
|
line.long 0x0 "DSS_L3_BANKC0_PD_CTRL,"
|
|
bitfld.long 0x0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_L3_BANKC1_PD_CTRL,"
|
|
bitfld.long 0x4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
group.long 0x148++0x7
|
|
line.long 0x0 "DSS_L3_BANKD0_PD_CTRL,"
|
|
bitfld.long 0x0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DSS_L3_BANKD1_PD_CTRL,"
|
|
bitfld.long 0x4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
group.long 0x158++0x3
|
|
line.long 0x0 "DSS_HWA_PD_CTRL,"
|
|
bitfld.long 0x0 16.--18. "pgoodin,SW Control for <IP>_PD_CTRL Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "ponin,SW Control for <IP>_PD_CTRL Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x15C++0xF
|
|
line.long 0x0 "DSS_DSP_L2_PD_STATUS,"
|
|
bitfld.long 0x0 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
line.long 0x4 "DSS_L3_BANKA0_PD_STATUS,"
|
|
bitfld.long 0x4 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
line.long 0x8 "DSS_L3_BANKA1_PD_STATUS,"
|
|
bitfld.long 0x8 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
line.long 0xC "DSS_L3_BANKA2_PD_STATUS,"
|
|
bitfld.long 0xC 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
rgroup.long 0x170++0xB
|
|
line.long 0x0 "DSS_L3_BANKB0_PD_STATUS,"
|
|
bitfld.long 0x0 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
line.long 0x4 "DSS_L3_BANKB1_PD_STATUS,"
|
|
bitfld.long 0x4 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
line.long 0x8 "DSS_L3_BANKB2_PD_STATUS,"
|
|
bitfld.long 0x8 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
rgroup.long 0x180++0x7
|
|
line.long 0x0 "DSS_L3_BANKC0_PD_STATUS,"
|
|
bitfld.long 0x0 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
line.long 0x4 "DSS_L3_BANKC1_PD_STATUS,"
|
|
bitfld.long 0x4 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
rgroup.long 0x190++0x7
|
|
line.long 0x0 "DSS_L3_BANKD0_PD_STATUS,"
|
|
bitfld.long 0x0 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
line.long 0x4 "DSS_L3_BANKD1_PD_STATUS,"
|
|
bitfld.long 0x4 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
rgroup.long 0x1A0++0x3
|
|
line.long 0x0 "DSS_HWA_PD_STATUS,"
|
|
bitfld.long 0x0 3. "pgoodout,Status for <IP>_PD_CTRL Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ponout,Status for <IP>_PD_CTRL Power up CRTL0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
|
|
group.long 0x1A4++0x3F
|
|
line.long 0x0 "DSS_DSP_TRCCLK_DIVRATIO,"
|
|
hexmask.long.byte 0x0 0.--3. 1. "divratio,DSP Trace Clock Divide Ratio"
|
|
line.long 0x4 "DSS_DSP_TCLK_DIVRATIO,"
|
|
hexmask.long.byte 0x4 0.--3. 1. "divratio,DSP TCLK Divide Ratio"
|
|
line.long 0x8 "DSS_DSP_DITHERED_CLK_CTRL,"
|
|
bitfld.long 0x8 31. "load,Write pulse bit field: DSP Dithered Clock LFSR Load" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28.--30. "enable,DSP Dithered Clock Enable. Write 3'b000 : Disabled Write 3'b111 : Enabled" "0: Disabled Write 3'b111 : Enabled,?,?,?,?,?,?,?"
|
|
newline
|
|
hexmask.long 0x8 0.--27. 1. "seed,DSP Dithered Clock LFSR Seed"
|
|
line.long 0xC "DSS_L3_PD_CTRL_STICKYBIT,"
|
|
bitfld.long 0xC 0.--2. "set,Sticky bit for DSS L3 PD CTRL. Write 3'b111 to lock the configuration of DSS_L3_BANK*_PD_CTRL. Once this field is writen there is no impact of changing the value of aonin and agoodin fields in DSS_L3_BANK*_PD_CTRL registers" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "DSP_PD_CTRL_MISC2,"
|
|
hexmask.long.word 0x10 16.--31. 1. "pwrsm_agood_assertcnt,Value of agood asertion delay"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "pwrsm_pgood_assertcnt,Value of pgood asertion delay"
|
|
line.long 0x14 "DSP_PD_CTRL_MISC3,"
|
|
bitfld.long 0x14 16. "lreset_req_gate,Gate the lreset request from GEM. For debug purpose." "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "pwrs_pd_waitcnt,Value of power down wait delay"
|
|
line.long 0x18 "DSP_PD_CTRL_OVERRIDE0,"
|
|
hexmask.long.byte 0x18 24.--29. 1. "state_bypass_val,DSS DSP power FSM state bypass control. For debug pupose."
|
|
newline
|
|
hexmask.long.tbyte 0x18 0.--23. 1. "bypass_val,DSS DSP power FSM bypass control. For debug pupose."
|
|
line.long 0x1C "DSP_PD_CTRL_OVERRIDE1,"
|
|
bitfld.long 0x1C 24. "state_bypass_en,DSS DSP power FSM state bypass control enable.For debug pupose." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "bypass_en,DSS DSP power FSM bypass control enable.For debug pupose."
|
|
line.long 0x20 "DSP_PD_CTRL_OVERRIDE2,"
|
|
bitfld.long 0x20 0.--2. "override_enable,DSS DSP power FSM override enable .For debug pupose." "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "DSS_HWA_RST_CTRL,"
|
|
bitfld.long 0x24 0.--2. "assert,This register is for Debug Purposes only. Reset control for DSS HWA Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
line.long 0x28 "DSS_HWA_RST_CTRL,"
|
|
bitfld.long 0x28 0.--2. "assert,This register is for Debug Purposes only. Reset control for DSS TPCCA Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
line.long 0x2C "DSS_EDMA_RST_CTRL,"
|
|
bitfld.long 0x2C 0.--2. "assert,This register is for Debug Purposes only. Reset control for DSS TPCCB Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
line.long 0x30 "DSS_EDMA_RST_CTRL,"
|
|
bitfld.long 0x30 0.--2. "assert,This register is for Debug Purposes only. Reset control for DSS TPCCC Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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|
line.long 0x34 "DSS_EDMA_RST_CTRL,"
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|
bitfld.long 0x34 4.--6. "assert_tc1,This register is for Debug Purposes only. Reset control for DSS TPTCA1 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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|
newline
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bitfld.long 0x34 0.--2. "assert_tc0,This register is for Debug Purposes only. Reset control for DSS TPTCA0 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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|
line.long 0x38 "DSS_EDMA_RST_CTRL,"
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bitfld.long 0x38 4.--6. "assert_tc1,This register is for Debug Purposes only. Reset control for DSS TPTCB1 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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|
newline
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bitfld.long 0x38 0.--2. "assert_tc0,This register is for Debug Purposes only. Reset control for DSS TPTCB0 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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line.long 0x3C "DSS_TPTCC_RST_CTRL,"
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bitfld.long 0x3C 20.--22. "assert_tc5,This register is for Debug Purposes only. Reset control for DSS TPTCC1 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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newline
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bitfld.long 0x3C 16.--18. "assert_tc4,This register is for Debug Purposes only. Reset control for DSS TPTCC0 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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newline
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bitfld.long 0x3C 12.--14. "assert_tc3,This register is for Debug Purposes only. Reset control for DSS TPTCC1 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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newline
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bitfld.long 0x3C 8.--10. "assert_tc2,This register is for Debug Purposes only. Reset control for DSS TPTCC0 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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newline
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bitfld.long 0x3C 4.--6. "assert_tc1,This register is for Debug Purposes only. Reset control for DSS TPTCC1 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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newline
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bitfld.long 0x3C 0.--2. "assert_tc0,This register is for Debug Purposes only. Reset control for DSS TPTCC0 Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another reset source which could reset the module. Refer to RCM spec for more.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
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repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
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group.long ($2+0xFD0)++0x3
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line.long 0x0 "HW_SPARE_RW$1,"
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hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
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repeat.end
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repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
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rgroup.long ($2+0xFE0)++0x3
|
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line.long 0x0 "HW_SPARE_RO$1,"
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hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
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repeat.end
|
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group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
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hexmask.long 0x0 0.--31. 1. "hw_spare_wph,Reserved for HW R&D"
|
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line.long 0x4 "HW_SPARE_REC,"
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bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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newline
|
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bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
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newline
|
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bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
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newline
|
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bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
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newline
|
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bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
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newline
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bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
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newline
|
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bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
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|
newline
|
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bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
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newline
|
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bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
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|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
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line.long 0x4 "LOCK0_KICK1,- KICK1 component"
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hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
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line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
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bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
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newline
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bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
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|
newline
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bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
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|
newline
|
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bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
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line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
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bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
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|
newline
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bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
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|
newline
|
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bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
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|
newline
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bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
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line.long 0x10 "intr_enable,Interrupt Enable register"
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bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
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newline
|
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bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
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bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
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bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
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|
newline
|
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bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
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|
newline
|
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bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
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|
newline
|
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bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
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|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "DSS_RTIA"
|
|
base ad:0x6F7A000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "RTIGCTRL,Global Control Register starts / stops the counters"
|
|
hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved. Reads return 0 and writes have no effect"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.."
|
|
newline
|
|
bitfld.long 0x0 15. "COS,COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while.." "0: stop counters in debug mode,1: continue counting in debug mode"
|
|
hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved. Reads return 0 and writes have no effect"
|
|
newline
|
|
bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bit.."
|
|
bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bits source.."
|
|
line.long 0x4 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
|
|
hexmask.long 0x4 2.--31. 1. "RESERVED3,Reserved"
|
|
bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
|
|
newline
|
|
bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
|
|
line.long 0x8 "RTICAPCTRL,Capture Control controls the capture source for the counters"
|
|
hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1. This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
|
|
newline
|
|
bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
|
|
line.long 0xC "RTICOMPCTRL,Compare Control controls the source for the compare registers"
|
|
hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
newline
|
|
bitfld.long 0xC 9.--11. "RESERVED7,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
newline
|
|
bitfld.long 0xC 5.--7. "RESERVED6,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
newline
|
|
bitfld.long 0xC 1.--3. "RESERVED5,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
|
|
hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
|
|
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
|
|
hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.."
|
|
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
|
|
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
|
|
hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0.."
|
|
line.long 0x4 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
|
|
hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0."
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
|
|
hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
|
|
line.long 0x4 "RTIUC1,Up Counter 1 current value of prescale counter 1"
|
|
hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.."
|
|
line.long 0x8 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
|
|
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
|
|
hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1.."
|
|
line.long 0x4 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
|
|
hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1."
|
|
group.long 0x50++0x27
|
|
line.long 0x0 "RTICOMP0,Compare 0 compare value to be compared with the counters"
|
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hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x4 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
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hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x8 "RTICOMP1,Compare 1 compare value to be compared with the counters"
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hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0xC "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
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hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register. This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
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hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
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hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
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hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
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hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
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hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when.."
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line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
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hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.."
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group.long 0x80++0xB
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line.long 0x0 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,1: interrupt is enabled Privilege mode"
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bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
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bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved. Reads return 0 and writes have no effect"
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newline
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bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
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bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
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hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
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hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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group.long 0x90++0x2F
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line.long 0x0 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
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hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled).."
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line.long 0x4 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
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hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts.."
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line.long 0x8 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
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hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read):.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 -> 1 threshold not exceeded 1 = AWD pin 0 -> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
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line.long 0xC "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
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hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.."
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line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
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hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved. Reads return 0 and writes have no effect"
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hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.."
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line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
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hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.."
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line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
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hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read) privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital.."
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line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
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hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled."
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hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled."
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hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled."
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newline
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hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled."
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line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
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hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.."
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line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
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hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.."
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line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
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hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.."
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line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
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hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.."
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tree.end
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tree "DSS_RTIB"
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base ad:0x6F7A100
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group.long 0x0++0x1B
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line.long 0x0 "RTIGCTRL,Global Control Register starts / stops the counters"
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hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.."
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newline
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bitfld.long 0x0 15. "COS,COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while.." "0: stop counters in debug mode,1: continue counting in debug mode"
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hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved. Reads return 0 and writes have no effect"
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newline
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bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bit.."
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bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bits source.."
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line.long 0x4 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
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hexmask.long 0x4 2.--31. 1. "RESERVED3,Reserved"
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bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
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newline
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bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
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line.long 0x8 "RTICAPCTRL,Capture Control controls the capture source for the counters"
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hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1. This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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newline
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bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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line.long 0xC "RTICOMPCTRL,Compare Control controls the source for the compare registers"
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hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 9.--11. "RESERVED7,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 5.--7. "RESERVED6,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 1.--3. "RESERVED5,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
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hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
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hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
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hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
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group.long 0x20++0x7
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line.long 0x0 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0.."
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line.long 0x4 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0."
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group.long 0x30++0xB
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line.long 0x0 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
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hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x4 "RTIUC1,Up Counter 1 current value of prescale counter 1"
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hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x8 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
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hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
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group.long 0x40++0x7
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line.long 0x0 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1.."
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line.long 0x4 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1."
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group.long 0x50++0x27
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line.long 0x0 "RTICOMP0,Compare 0 compare value to be compared with the counters"
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hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x4 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
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hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x8 "RTICOMP1,Compare 1 compare value to be compared with the counters"
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hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0xC "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
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hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register. This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
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hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
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hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
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hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
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hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
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hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when.."
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line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
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hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.."
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group.long 0x80++0xB
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line.long 0x0 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,1: interrupt is enabled Privilege mode"
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bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
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hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
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hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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group.long 0x90++0x2F
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line.long 0x0 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
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hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled).."
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line.long 0x4 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
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hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts.."
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line.long 0x8 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
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hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read):.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 -> 1 threshold not exceeded 1 = AWD pin 0 -> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
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line.long 0xC "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
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hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.."
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line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
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hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved. Reads return 0 and writes have no effect"
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hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.."
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line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
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hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.."
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line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
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hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read) privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital.."
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line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
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hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled."
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hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled."
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hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled."
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hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled."
|
|
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
|
|
hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.."
|
|
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
|
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hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.."
|
|
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
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|
hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.."
|
|
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
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hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.."
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|
tree.end
|
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tree "DSS_SCIA"
|
|
base ad:0x6F7B000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "SCIGCR0,The SCIGCR0 register defines the module reset"
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hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved"
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|
newline
|
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bitfld.long 0x0 0. "RESET,GIO reset" "0,1"
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|
line.long 0x4 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
|
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hexmask.long.byte 0x4 26.--31. 1. "RESERVED4,Reserved"
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|
newline
|
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bitfld.long 0x4 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
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newline
|
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bitfld.long 0x4 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
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|
newline
|
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hexmask.long.byte 0x4 18.--23. 1. "RESERVED3,Reserved"
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newline
|
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bitfld.long 0x4 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
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newline
|
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bitfld.long 0x4 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
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|
newline
|
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hexmask.long.byte 0x4 10.--15. 1. "RESERVED2,Reserved"
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|
newline
|
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bitfld.long 0x4 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
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newline
|
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bitfld.long 0x4 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode" "0,1"
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|
newline
|
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bitfld.long 0x4 7. "SW_nRESET,Software reset (active low)" "0,1"
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|
newline
|
|
rbitfld.long 0x4 6. "RESERVED1,Reserved" "0,1"
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|
newline
|
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bitfld.long 0x4 5. "CLOCK,SCI internal clock enable" "0,1"
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newline
|
|
bitfld.long 0x4 4. "STOP,SCI number of stop bits" "0,1"
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newline
|
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bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection" "0,1"
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|
newline
|
|
bitfld.long 0x4 2. "PARITY_ENA,SCI parity enable" "0,1"
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|
newline
|
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bitfld.long 0x4 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0: Isosynchronous timing,1: Asynchronous timing)"
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newline
|
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bitfld.long 0x4 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0: Idle-line mode,1: Address-bit mode)"
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repeat 9. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list 0x0 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74)
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|
rgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "RESERVED$1,Reserved"
|
|
hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved"
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|
repeat.end
|
|
group.long 0xC++0x13
|
|
line.long 0x0 "SCISETINT,SCI Set Interrupt Register"
|
|
hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x0 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
|
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hexmask.long.byte 0x0 19.--23. 1. "RESERVED3,Reserved"
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newline
|
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bitfld.long 0x0 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address.." "0: leaves the corresponding bit unchanged,1: enable DMA request for address and data frames"
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newline
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bitfld.long 0x0 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set. If it is cleared interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode.." "0: leaves the corresponding bit unchanged,1: enable DMA request"
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newline
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bitfld.long 0x0 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x0 10.--15. 1. "RESERVED2,Reserved"
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newline
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bitfld.long 0x0 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 8. "SET_TX_INT,Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 =.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x0 2.--7. 1. "RESERVED1,Reserved"
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newline
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bitfld.long 0x0 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 0. "SET_BRKDT_INT,Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "SCICLEARINT,SCI Clear Interrupt Register"
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hexmask.long.byte 0x4 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x4 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
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bitfld.long 0x4 25. "CLR_OE_INT,Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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bitfld.long 0x4 24. "CLR_PE_INT,Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
|
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hexmask.long.byte 0x4 19.--23. 1. "RESERVED3,Reserved"
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newline
|
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bitfld.long 0x4 18. "CLR_RX_DMA_ALL,User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and.." "0: leaves the corresponding bit unchanged,1: disable DMA request for address frames"
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newline
|
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bitfld.long 0x4 17. "CLR_RX_DMA,Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
|
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bitfld.long 0x4 16. "CLR_TX_DMA,Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
|
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hexmask.long.byte 0x4 10.--15. 1. "RESERVED2,Reserved"
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newline
|
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bitfld.long 0x4 9. "CLR_RX_INT,Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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bitfld.long 0x4 8. "CLR_TX_INT,Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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hexmask.long.byte 0x4 2.--7. 1. "RESERVED1,Reserved"
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|
newline
|
|
bitfld.long 0x4 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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bitfld.long 0x4 0. "CLR_BRKDT_INT,Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "SCISETINTLVL,SCI Set Interrupt Level Register"
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hexmask.long.byte 0x8 27.--31. 1. "RESERVED5,Reserved"
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newline
|
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bitfld.long 0x8 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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bitfld.long 0x8 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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bitfld.long 0x8 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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hexmask.long.byte 0x8 19.--23. 1. "RESERVED4,Reserved"
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|
newline
|
|
bitfld.long 0x8 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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rbitfld.long 0x8 16.--17. "RESERVED3,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 15. "SET_INC_BR_INT_LVL," "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 10.--14. 1. "RESERVED2,Reserved"
|
|
newline
|
|
bitfld.long 0x8 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
|
bitfld.long 0x8 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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|
newline
|
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hexmask.long.byte 0x8 2.--7. 1. "RESERVED1,Reserved"
|
|
newline
|
|
bitfld.long 0x8 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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bitfld.long 0x8 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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line.long 0xC "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
|
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hexmask.long.byte 0xC 27.--31. 1. "RESERVED5,Reserved"
|
|
newline
|
|
bitfld.long 0xC 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
|
bitfld.long 0xC 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
|
bitfld.long 0xC 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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|
newline
|
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hexmask.long.byte 0xC 19.--23. 1. "RESERVED4,Reserved"
|
|
newline
|
|
bitfld.long 0xC 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
|
rbitfld.long 0xC 16.--17. "RESERVED3,Reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 15. "CLR_INC_BR_INT_LVL," "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 10.--14. 1. "RESERVED2,Reserved"
|
|
newline
|
|
bitfld.long 0xC 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
|
bitfld.long 0xC 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
|
hexmask.long.byte 0xC 2.--7. 1. "RESERVED1,Reserved"
|
|
newline
|
|
bitfld.long 0xC 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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|
newline
|
|
bitfld.long 0xC 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
line.long 0x10 "SCIFLR,SCI Flags Register"
|
|
hexmask.long.byte 0x10 27.--31. 1. "RESERVED3,Reserved"
|
|
newline
|
|
bitfld.long 0x10 26. "FE,SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0" "0: No framing error detected 1=Framing error..,?"
|
|
newline
|
|
rbitfld.long 0x10 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 24. "PE,SCI parity error flag. This bit is set when a parity error is detected in the received data" "0,1"
|
|
newline
|
|
hexmask.long.word 0x10 13.--23. 1. "RESERVED2,Reserved"
|
|
newline
|
|
rbitfld.long 0x10 12. "RXWAKE,Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 11. "TX_EMPTY,Transmitter empty flag. The value of this flag indicates the contents of the transmitter's buffer register (SCITD) and shift register (SCITXSHF)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "TXWAKE,SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 9. "RXRDY,SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 8. "TXRDY,Transmitter buffer register ready flag. When set this bit indicates that the transmit buffer register (SCITD) is ready to receive another character." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--7. 1. "RESERVED1,Reserved"
|
|
newline
|
|
rbitfld.long 0x10 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 2. "IDLE,SCI receiver in idle state. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 1. "WAKEUP,Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "BRKDT,SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin." "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
|
|
hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTVECT0,Interrupt vector offset for INT0"
|
|
line.long 0x4 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
|
|
hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "INTVECT1,Interrupt vector offset for INT1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SCICHAR,SCI Character Control Register"
|
|
hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SCIBAUD,SCI Baud Rate Selection Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved"
|
|
newline
|
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hexmask.long.tbyte 0x4 0.--23. 1. "BAUD,SCI 24-bit baud selection"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SCIED,Receiver Emulation Data Buffer"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data Buffer"
|
|
line.long 0x4 "SCIRD,Receiver Data Buffer"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RD,Contains received data."
|
|
group.long 0x38++0x27
|
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line.long 0x0 "SCITD,Transmit Data Buffer Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x0 0.--7. 1. "TD,Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."
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line.long 0x4 "SCIPIO0,SCI Pin I/O Control Register 0"
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hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x4 2. "TX_FUNC,Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin. 0=SCIRX is a general-purpose digital I/O pin. 1=SCIRX is the SCI receive pin." "0: SCIRX is a general-purpose digital I/O pin,1: SCIRX is the SCI receive pin"
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bitfld.long 0x4 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin" "0: SCIRX is a general-purpose input pin,1: SCIRX is a general-purpose output pin"
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newline
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bitfld.long 0x4 0. "CLK_FUNC,Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the.." "0: SCICLK is a general-purpose digital I/O pin,1: SCICLK is the SCI serial clock pin"
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line.long 0x8 "SCIPIO1,SCI Pin I/O Control Register 1"
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hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x8 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin" "0: SCITX is a general-purpose input pin,1: SCITX is a general-purpose output pin"
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newline
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bitfld.long 0x8 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin" "0: SCIRX is a general-purpose input pin,1: SCIRX is a general-purpose output pin"
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newline
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bitfld.long 0x8 0. "CLK_DIR,Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit" "0,1"
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line.long 0xC "SCIPIO2,SCI Pin I/O Control Register 2"
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hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0xC 2. "TX_DATA_IN,Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high." "0: SCITX value is logic low,1: SCITX value is logic high"
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newline
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bitfld.long 0xC 1. "RX_DATA_IN,Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high." "0: SCIRX value is logic low,1: SCIRX value is logic high"
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newline
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bitfld.long 0xC 0. "CLK_DATA_IN,Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high." "0: Pin SCICLK value is logic low,1: Pin SCICLK value is logic high"
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line.long 0x10 "SCIPIO3,SCI Pin I/O Control Register 3"
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hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x10 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output.." "0: Output value on SCITX is a 0,1: Output value on SCITX is a 1"
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newline
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bitfld.long 0x10 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output.." "0: Output value on SCIRX is 0,1: Output value on SCIRX is 1"
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newline
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bitfld.long 0x10 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low)." "0: Output value on SCICLK is a 0,1: Output value on SCICLK is a 1"
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line.long 0x14 "SCIPIO4,SCI Pin I/O Control Register 4"
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hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x14 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x14 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x14 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
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line.long 0x18 "SCIPIO5,SCI Pin I/O Control Register 5"
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hexmask.long 0x18 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x18 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x18 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x18 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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line.long 0x1C "SCIPIO6,SCI Pin I/O Control Register 6"
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hexmask.long 0x1C 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x1C 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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newline
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bitfld.long 0x1C 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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newline
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bitfld.long 0x1C 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
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line.long 0x20 "SCIPIO7,SCI Pin I/O Control Register 7"
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hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x20 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled." "0: Pull Control on SCITX pin is enabled,1: Pull Control on SCITX pin is disabled"
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newline
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bitfld.long 0x20 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled." "0: Pull Control on SCIRX pin is enabled,1: Pull Control on SCIRX pin is disabled"
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newline
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bitfld.long 0x20 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled." "0: Pull Control on SCICLK pin is enabled,1: Pull Control on SCICLK pin is disabled"
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line.long 0x24 "SCIPIO8,SCI Pin I/O Control Register 8"
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hexmask.long 0x24 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x24 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin." "0: Pull-Down is on SCITX pin,1: Pull-Up is on SCITX pin"
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newline
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bitfld.long 0x24 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin." "0: Pull-Down is on SCIRX pin,1: Pull-Up is on SCIRX pin"
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newline
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bitfld.long 0x24 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin." "0: Pull-Down is on SCICLK pin,1: Pull-Up is on SCICLK pin"
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group.long 0x80++0x3
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line.long 0x0 "SCIPIO9,SCI Pin I/O Control Register 9"
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hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x0 2. "TX_SL,This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin." "0: The normal output buffer is used for SCITX pin..,?"
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newline
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bitfld.long 0x0 1. "RX_SL,This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin" "0: The normal output buffer is used for SCIRX pin..,?"
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newline
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bitfld.long 0x0 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin" "0: The normal output buffer is used for SCICLK pin..,?"
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group.long 0x90++0x3
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line.long 0x0 "SCIIODCTRL,SCI IO DFT Control"
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hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x0 26. "FEN,Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with '0' and passed to the stop bit check circuitry. 0 = No effect." "0: No effect,1: This bit is used to create a Frame Error"
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newline
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bitfld.long 0x0 25. "PEN,Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect" "0: No effect,1: This bit is used to create a Parity Error"
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newline
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bitfld.long 0x0 24. "BRKDT_ENA,Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error occurs. Then the RX pin is forced to.." "0: No effect,1: This bit is used to create BRKDT Error"
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newline
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rbitfld.long 0x0 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask 01 -- Invert the TX.." "0: No Mask,1: Invert the TX Pin value at 7th SCLK,?,?"
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bitfld.long 0x0 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay 001 -- Delay by 1 SCLK 010 -- Delay by 2 SCLKs 011 -- Delay by 3 SCLKs .." "0: No Delay,1: Delay by 1 SCLK,?,?,?,?,?,?"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED2,Reserved"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay 001 -- Delay by 1 SCLK 010 -- Delay by 2 SCLKs 011 -- Delay by 3 SCLKs .."
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newline
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hexmask.long.byte 0x0 2.--7. 1. "RESERVED1,Reserved"
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newline
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bitfld.long 0x0 1. "LBP_ENA,Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled." "0: Digital loopback is enabled,1: Analog loopback is enabled in module I/O DFT mode"
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newline
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bitfld.long 0x0 0. "RXP_ENA,Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin." "0: Analog loopback through transmit pin,1: Analog loopback through receive pin"
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tree.end
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tree "DSS_TPCC_A"
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base ad:0x6100000
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rgroup.long 0x0++0x7
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line.long 0x0 "PID,Peripheral ID Register"
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bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
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bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
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newline
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hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
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hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
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newline
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bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
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line.long 0x4 "CCCFG,CC Configuration Register"
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hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD"
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bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included"
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newline
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bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included"
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bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
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newline
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bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
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bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
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group.long 0x200++0x3
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line.long 0x0 "QCHMAPN,QDMA Channel N Mapping Register"
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hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD"
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hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N."
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newline
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bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7"
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group.long 0x240++0x3
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line.long 0x0 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."
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rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1"
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bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1"
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bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1"
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bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1"
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bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1"
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bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1"
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bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1"
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bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1"
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bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
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group.long 0x260++0x3
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line.long 0x0 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."
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rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1"
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bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1"
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bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1"
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bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1"
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bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
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group.long 0x280++0x7
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line.long 0x0 "QUETCMAP,Queue to TC Mapping"
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hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD"
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bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1"
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bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
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line.long 0x4 "QUEPRI,Queue Priority"
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|
hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD"
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bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
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|
newline
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rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1"
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bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x300++0x7
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line.long 0x0 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit.."
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bitfld.long 0x0 31. "E31,Event Missed #31" "0,1"
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bitfld.long 0x0 30. "E30,Event Missed #30" "0,1"
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newline
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bitfld.long 0x0 29. "E29,Event Missed #29" "0,1"
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bitfld.long 0x0 28. "E28,Event Missed #28" "0,1"
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|
newline
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bitfld.long 0x0 27. "E27,Event Missed #27" "0,1"
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bitfld.long 0x0 26. "E26,Event Missed #26" "0,1"
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|
newline
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bitfld.long 0x0 25. "E25,Event Missed #25" "0,1"
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bitfld.long 0x0 24. "E24,Event Missed #24" "0,1"
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newline
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bitfld.long 0x0 23. "E23,Event Missed #23" "0,1"
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bitfld.long 0x0 22. "E22,Event Missed #22" "0,1"
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newline
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bitfld.long 0x0 21. "E21,Event Missed #21" "0,1"
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bitfld.long 0x0 20. "E20,Event Missed #20" "0,1"
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newline
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bitfld.long 0x0 19. "E19,Event Missed #19" "0,1"
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bitfld.long 0x0 18. "E18,Event Missed #18" "0,1"
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newline
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bitfld.long 0x0 17. "E17,Event Missed #17" "0,1"
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bitfld.long 0x0 16. "E16,Event Missed #16" "0,1"
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newline
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bitfld.long 0x0 15. "E15,Event Missed #15" "0,1"
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bitfld.long 0x0 14. "E14,Event Missed #14" "0,1"
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newline
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bitfld.long 0x0 13. "E13,Event Missed #13" "0,1"
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bitfld.long 0x0 12. "E12,Event Missed #12" "0,1"
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newline
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bitfld.long 0x0 11. "E11,Event Missed #11" "0,1"
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bitfld.long 0x0 10. "E10,Event Missed #10" "0,1"
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newline
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bitfld.long 0x0 9. "E9,Event Missed #9" "0,1"
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bitfld.long 0x0 8. "E8,Event Missed #8" "0,1"
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newline
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bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
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newline
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bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
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newline
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bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
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bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
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newline
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bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
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line.long 0x4 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated.."
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bitfld.long 0x4 31. "E63,Event Missed #63" "0,1"
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bitfld.long 0x4 30. "E62,Event Missed #62" "0,1"
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newline
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bitfld.long 0x4 29. "E61,Event Missed #61" "0,1"
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bitfld.long 0x4 28. "E60,Event Missed #60" "0,1"
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newline
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bitfld.long 0x4 27. "E59,Event Missed #59" "0,1"
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bitfld.long 0x4 26. "E58,Event Missed #58" "0,1"
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newline
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bitfld.long 0x4 25. "E57,Event Missed #57" "0,1"
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bitfld.long 0x4 24. "E56,Event Missed #56" "0,1"
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newline
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bitfld.long 0x4 23. "E55,Event Missed #55" "0,1"
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bitfld.long 0x4 22. "E54,Event Missed #54" "0,1"
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newline
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bitfld.long 0x4 21. "E53,Event Missed #53" "0,1"
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bitfld.long 0x4 20. "E52,Event Missed #52" "0,1"
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newline
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bitfld.long 0x4 19. "E51,Event Missed #51" "0,1"
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bitfld.long 0x4 18. "E50,Event Missed #50" "0,1"
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newline
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bitfld.long 0x4 17. "E49,Event Missed #49" "0,1"
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bitfld.long 0x4 16. "E48,Event Missed #48" "0,1"
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newline
|
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bitfld.long 0x4 15. "E47,Event Missed #47" "0,1"
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bitfld.long 0x4 14. "E46,Event Missed #46" "0,1"
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newline
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bitfld.long 0x4 13. "E45,Event Missed #45" "0,1"
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bitfld.long 0x4 12. "E44,Event Missed #44" "0,1"
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|
newline
|
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bitfld.long 0x4 11. "E43,Event Missed #43" "0,1"
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bitfld.long 0x4 10. "E42,Event Missed #42" "0,1"
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|
newline
|
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bitfld.long 0x4 9. "E41,Event Missed #41" "0,1"
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|
bitfld.long 0x4 8. "E40,Event Missed #40" "0,1"
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|
newline
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bitfld.long 0x4 7. "E39,Event Missed #39" "0,1"
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bitfld.long 0x4 6. "E38,Event Missed #38" "0,1"
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newline
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bitfld.long 0x4 5. "E37,Event Missed #37" "0,1"
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bitfld.long 0x4 4. "E36,Event Missed #36" "0,1"
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newline
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bitfld.long 0x4 3. "E35,Event Missed #35" "0,1"
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bitfld.long 0x4 2. "E34,Event Missed #34" "0,1"
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newline
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bitfld.long 0x4 1. "E33,Event Missed #33" "0,1"
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bitfld.long 0x4 0. "E32,Event Missed #32" "0,1"
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|
wgroup.long 0x308++0x7
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|
line.long 0x0 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
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bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1"
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bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1"
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newline
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bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1"
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bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1"
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newline
|
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bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1"
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bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1"
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newline
|
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bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1"
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bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1"
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newline
|
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bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1"
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bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1"
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newline
|
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bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1"
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bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1"
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newline
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bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1"
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bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1"
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newline
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bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1"
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bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1"
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newline
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bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1"
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bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1"
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newline
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bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1"
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bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1"
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newline
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bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1"
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bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1"
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newline
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bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1"
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bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1"
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newline
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bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
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newline
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bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
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bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
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newline
|
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bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
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newline
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bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
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line.long 0x4 "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
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bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1"
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bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1"
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newline
|
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bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1"
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bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1"
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newline
|
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bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1"
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bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1"
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newline
|
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bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1"
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bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1"
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newline
|
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bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1"
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bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1"
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newline
|
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bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1"
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bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1"
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newline
|
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bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1"
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bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1"
|
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bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1"
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newline
|
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bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1"
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bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1"
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newline
|
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bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1"
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bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1"
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newline
|
|
bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1"
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bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1"
|
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bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1"
|
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newline
|
|
bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1"
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bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1"
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newline
|
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bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1"
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bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1"
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|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1"
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bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1"
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newline
|
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bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1"
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bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1"
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rgroup.long 0x310++0x3
|
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line.long 0x0 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR).."
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hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD"
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bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
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bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
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newline
|
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bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
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bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
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newline
|
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bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
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bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
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newline
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
group.long 0x314++0x3
|
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line.long 0x0 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
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hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD"
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bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
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newline
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
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bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
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bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
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|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
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|
rgroup.long 0x318++0x3
|
|
line.long 0x0 "CCERR,CC Error Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached"
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|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
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|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
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|
bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
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|
bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
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|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
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|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: QTHRXCD0 = 0 : Watermark/threshold has not been..,1: Watermark/threshold has been exceeded"
|
|
group.long 0x31C++0x7
|
|
line.long 0x0 "CCERRCLR,CC Error Clear Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "?,1: Write of '1' clears the values of QSTAT1"
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|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0: Write of '1' clears the values of QSTAT0,?"
|
|
line.long 0x4 "EEVAL,Error Eval Register"
|
|
hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD"
|
|
bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1"
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|
newline
|
|
bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1"
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|
group.long 0x340++0x7
|
|
line.long 0x0 "DRAEM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
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|
bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
|
|
line.long 0x4 "DRAEHM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "QRAEN,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
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|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD"
|
|
bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.."
|
|
repeat.end
|
|
rgroup.long 0x600++0x3
|
|
line.long 0x0 "QSTATN,QSTATn Register Set"
|
|
hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD"
|
|
bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR,1: Threshold specified by QWMTHR"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10.."
|
|
newline
|
|
bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"
|
|
group.long 0x620++0x3
|
|
line.long 0x0 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0.."
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value"
|
|
newline
|
|
rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value"
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x0 "CCSTAT,CC Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD"
|
|
bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7"
|
|
newline
|
|
bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6"
|
|
bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5"
|
|
newline
|
|
bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4"
|
|
bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3"
|
|
newline
|
|
bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2"
|
|
bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1"
|
|
newline
|
|
bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0"
|
|
bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.."
|
|
bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.."
|
|
bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
newline
|
|
bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "AETCTL,Advanced Event Trigger Control"
|
|
bitfld.long 0x0 31. "EN,AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled"
|
|
hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"
|
|
rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA Events,1: Event specified by STARTEVT applies to QDMA.."
|
|
hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"
|
|
rgroup.long 0x704++0x3
|
|
line.long 0x0 "AETSTAT,Advanced Event Trigger Stat"
|
|
hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "STAT,AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "AETCMD,AET Command"
|
|
hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1000++0x7
|
|
line.long 0x0 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low).."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1008++0xF
|
|
line.long 0x0 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1018++0xF
|
|
line.long 0x0 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1028++0xF
|
|
line.long 0x0 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1038++0x7
|
|
line.long 0x0 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1040++0x7
|
|
line.long 0x0 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1050++0x7
|
|
line.long 0x0 "IER,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1058++0xF
|
|
line.long 0x0 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x1068++0x7
|
|
line.long 0x0 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1070++0x7
|
|
line.long 0x0 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x1078++0x3
|
|
line.long 0x0 "IEVAL,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1080++0x7
|
|
line.long 0x0 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x1088++0x7
|
|
line.long 0x0 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x1094++0x3
|
|
line.long 0x0 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2000++0x7
|
|
line.long 0x0 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2008++0xF
|
|
line.long 0x0 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2018++0xF
|
|
line.long 0x0 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2028++0xF
|
|
line.long 0x0 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2038++0x7
|
|
line.long 0x0 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2040++0x7
|
|
line.long 0x0 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2050++0x7
|
|
line.long 0x0 "IER_RN,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2058++0xF
|
|
line.long 0x0 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x2068++0x7
|
|
line.long 0x0 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2070++0x7
|
|
line.long 0x0 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x2078++0x3
|
|
line.long 0x0 "IEVAL_RN,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x2080++0x7
|
|
line.long 0x0 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x2088++0x7
|
|
line.long 0x0 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2090++0x3
|
|
line.long 0x0 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x2094++0x3
|
|
line.long 0x0 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
tree.end
|
|
tree "DSS_TPCC_B"
|
|
base ad:0x6120000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "CCCFG,CC Configuration Register"
|
|
hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD"
|
|
bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included"
|
|
newline
|
|
bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included"
|
|
bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
|
|
bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD"
|
|
hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N."
|
|
newline
|
|
bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."
|
|
rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."
|
|
rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "QUETCMAP,Queue to TC Mapping"
|
|
hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD"
|
|
bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QUEPRI,Queue Priority"
|
|
hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD"
|
|
bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit.."
|
|
bitfld.long 0x0 31. "E31,Event Missed #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
line.long 0x4 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated.."
|
|
bitfld.long 0x4 31. "E63,Event Missed #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed #32" "0,1"
|
|
wgroup.long 0x308++0x7
|
|
line.long 0x0 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
line.long 0x4 "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x0 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR).."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x0 "CCERR,CC Error Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: QTHRXCD0 = 0 : Watermark/threshold has not been..,1: Watermark/threshold has been exceeded"
|
|
group.long 0x31C++0x7
|
|
line.long 0x0 "CCERRCLR,CC Error Clear Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "?,1: Write of '1' clears the values of QSTAT1"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0: Write of '1' clears the values of QSTAT0,?"
|
|
line.long 0x4 "EEVAL,Error Eval Register"
|
|
hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD"
|
|
bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1"
|
|
group.long 0x340++0x7
|
|
line.long 0x0 "DRAEM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
|
|
line.long 0x4 "DRAEHM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "QRAEN,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD"
|
|
bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.."
|
|
repeat.end
|
|
rgroup.long 0x600++0x3
|
|
line.long 0x0 "QSTATN,QSTATn Register Set"
|
|
hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD"
|
|
bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR,1: Threshold specified by QWMTHR"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10.."
|
|
newline
|
|
bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"
|
|
group.long 0x620++0x3
|
|
line.long 0x0 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0.."
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value"
|
|
newline
|
|
rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value"
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x0 "CCSTAT,CC Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD"
|
|
bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7"
|
|
newline
|
|
bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6"
|
|
bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5"
|
|
newline
|
|
bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4"
|
|
bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3"
|
|
newline
|
|
bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2"
|
|
bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1"
|
|
newline
|
|
bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0"
|
|
bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.."
|
|
bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.."
|
|
bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
newline
|
|
bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "AETCTL,Advanced Event Trigger Control"
|
|
bitfld.long 0x0 31. "EN,AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled"
|
|
hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"
|
|
rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA Events,1: Event specified by STARTEVT applies to QDMA.."
|
|
hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"
|
|
rgroup.long 0x704++0x3
|
|
line.long 0x0 "AETSTAT,Advanced Event Trigger Stat"
|
|
hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "STAT,AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "AETCMD,AET Command"
|
|
hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1000++0x7
|
|
line.long 0x0 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low).."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1008++0xF
|
|
line.long 0x0 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1018++0xF
|
|
line.long 0x0 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1028++0xF
|
|
line.long 0x0 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1038++0x7
|
|
line.long 0x0 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1040++0x7
|
|
line.long 0x0 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1050++0x7
|
|
line.long 0x0 "IER,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1058++0xF
|
|
line.long 0x0 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x1068++0x7
|
|
line.long 0x0 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1070++0x7
|
|
line.long 0x0 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x1078++0x3
|
|
line.long 0x0 "IEVAL,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1080++0x7
|
|
line.long 0x0 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x1088++0x7
|
|
line.long 0x0 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x1094++0x3
|
|
line.long 0x0 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2000++0x7
|
|
line.long 0x0 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2008++0xF
|
|
line.long 0x0 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2018++0xF
|
|
line.long 0x0 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2028++0xF
|
|
line.long 0x0 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2038++0x7
|
|
line.long 0x0 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2040++0x7
|
|
line.long 0x0 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2050++0x7
|
|
line.long 0x0 "IER_RN,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2058++0xF
|
|
line.long 0x0 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x2068++0x7
|
|
line.long 0x0 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2070++0x7
|
|
line.long 0x0 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x2078++0x3
|
|
line.long 0x0 "IEVAL_RN,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x2080++0x7
|
|
line.long 0x0 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x2088++0x7
|
|
line.long 0x0 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2090++0x3
|
|
line.long 0x0 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x2094++0x3
|
|
line.long 0x0 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
tree.end
|
|
tree "DSS_TPCC_C"
|
|
base ad:0x6140000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "CCCFG,CC Configuration Register"
|
|
hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD"
|
|
bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included"
|
|
newline
|
|
bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included"
|
|
bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
|
|
bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD"
|
|
hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N."
|
|
newline
|
|
bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."
|
|
rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."
|
|
rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "QUETCMAP,Queue to TC Mapping"
|
|
hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD"
|
|
bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QUEPRI,Queue Priority"
|
|
hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD"
|
|
bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit.."
|
|
bitfld.long 0x0 31. "E31,Event Missed #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
line.long 0x4 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated.."
|
|
bitfld.long 0x4 31. "E63,Event Missed #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed #32" "0,1"
|
|
wgroup.long 0x308++0x7
|
|
line.long 0x0 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
line.long 0x4 "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x0 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR).."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x0 "CCERR,CC Error Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
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|
bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: QTHRXCD0 = 0 : Watermark/threshold has not been..,1: Watermark/threshold has been exceeded"
|
|
group.long 0x31C++0x7
|
|
line.long 0x0 "CCERRCLR,CC Error Clear Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "?,1: Write of '1' clears the values of QSTAT1"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0: Write of '1' clears the values of QSTAT0,?"
|
|
line.long 0x4 "EEVAL,Error Eval Register"
|
|
hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD"
|
|
bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1"
|
|
group.long 0x340++0x7
|
|
line.long 0x0 "DRAEM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
|
|
line.long 0x4 "DRAEHM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "QRAEN,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD"
|
|
bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.."
|
|
repeat.end
|
|
rgroup.long 0x600++0x3
|
|
line.long 0x0 "QSTATN,QSTATn Register Set"
|
|
hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD"
|
|
bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR,1: Threshold specified by QWMTHR"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10.."
|
|
newline
|
|
bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"
|
|
group.long 0x620++0x3
|
|
line.long 0x0 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0.."
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value"
|
|
newline
|
|
rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value"
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x0 "CCSTAT,CC Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD"
|
|
bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7"
|
|
newline
|
|
bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6"
|
|
bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5"
|
|
newline
|
|
bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4"
|
|
bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3"
|
|
newline
|
|
bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2"
|
|
bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1"
|
|
newline
|
|
bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0"
|
|
bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.."
|
|
bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.."
|
|
bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
newline
|
|
bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "AETCTL,Advanced Event Trigger Control"
|
|
bitfld.long 0x0 31. "EN,AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled"
|
|
hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"
|
|
rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA Events,1: Event specified by STARTEVT applies to QDMA.."
|
|
hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"
|
|
rgroup.long 0x704++0x3
|
|
line.long 0x0 "AETSTAT,Advanced Event Trigger Stat"
|
|
hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "STAT,AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "AETCMD,AET Command"
|
|
hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1000++0x7
|
|
line.long 0x0 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low).."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1008++0xF
|
|
line.long 0x0 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1018++0xF
|
|
line.long 0x0 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1028++0xF
|
|
line.long 0x0 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1038++0x7
|
|
line.long 0x0 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1040++0x7
|
|
line.long 0x0 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1050++0x7
|
|
line.long 0x0 "IER,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1058++0xF
|
|
line.long 0x0 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x1068++0x7
|
|
line.long 0x0 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1070++0x7
|
|
line.long 0x0 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x1078++0x3
|
|
line.long 0x0 "IEVAL,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1080++0x7
|
|
line.long 0x0 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x1088++0x7
|
|
line.long 0x0 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x1094++0x3
|
|
line.long 0x0 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2000++0x7
|
|
line.long 0x0 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2008++0xF
|
|
line.long 0x0 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2018++0xF
|
|
line.long 0x0 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2028++0xF
|
|
line.long 0x0 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2038++0x7
|
|
line.long 0x0 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2040++0x7
|
|
line.long 0x0 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2050++0x7
|
|
line.long 0x0 "IER_RN,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2058++0xF
|
|
line.long 0x0 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x2068++0x7
|
|
line.long 0x0 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2070++0x7
|
|
line.long 0x0 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x2078++0x3
|
|
line.long 0x0 "IEVAL_RN,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x2080++0x7
|
|
line.long 0x0 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x2088++0x7
|
|
line.long 0x0 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2090++0x3
|
|
line.long 0x0 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x2094++0x3
|
|
line.long 0x0 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
tree.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x6160000 ad:0x6180000)
|
|
tree "DSS_TPTC_A$1"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x100)++0x7
|
|
line.long 0x0 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3"
|
|
bitfld.long 0x0 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "WSACTV,Write Status Active WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands. WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write.." "0: Write status is not pending,1: Write Status is pending"
|
|
newline
|
|
bitfld.long 0x0 1. "SRCACTV,Source Active State SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1]. SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.."
|
|
bitfld.long 0x0 0. "PROGBUSY,Program Register Set Busy PROGBUSY = 0 : Prog set idle and is available for programming. PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy"
|
|
line.long 0x4 "INTSTAT,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "TRDONE,TR Done Event Status: TRDONE = 0 : Condition not detected. TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to.." "0: Condition not detected,1: Set when TC has completed a Transfer Request"
|
|
bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY = 0 : Condition not detected. PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.."
|
|
group.long ($2+0x108)++0x3
|
|
line.long 0x0 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE = 0 : TRDONE Event is disabled. INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.."
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled. INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.."
|
|
wgroup.long ($2+0x10C)++0x7
|
|
line.long 0x0 "INTCLR,Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE = 0 : Writes of '0' have no effect. INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect. INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
line.long 0x4 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x4 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
|
|
rgroup.long ($2+0x120)++0x3
|
|
line.long 0x0 "ERRSTAT,Error Status Register"
|
|
bitfld.long 0x0 3. "MMRAERR,MMR Address Error: MMRAERR = 0 : Condition not detected. MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.."
|
|
bitfld.long 0x0 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Bus Error Event: BUSERR = 0: Condition not detected. BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.."
|
|
group.long ($2+0x124)++0x3
|
|
line.long 0x0 "ERREN,Error Enable Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR = 0 : BUSERR is disabled. ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.."
|
|
bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR = 0 : BUSERR is disabled. ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.."
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR = 0 : BUSERR is disabled. ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.."
|
|
wgroup.long ($2+0x128)++0x3
|
|
line.long 0x0 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR = 0 : Writes of '0' have no effect. ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
|
|
bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR = 0 : Writes of '0' have no effect. ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR = 0 : Writes of '0' have no effect. ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
|
|
rgroup.long ($2+0x12C)++0x3
|
|
line.long 0x0 "ERRDET,Error Details Register"
|
|
bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
|
|
bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "15-14,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."
|
|
hexmask.long.byte 0x0 0.--3. 1. "13-8,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle.."
|
|
wgroup.long ($2+0x130)++0x3
|
|
line.long 0x0 "ERRCMD,Error Command Register"
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|
bitfld.long 0x0 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
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|
bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
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|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7"
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|
group.long ($2+0x200)++0x13
|
|
line.long 0x0 "POPT,Prog Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
|
|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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|
line.long 0x4 "PSRC,Prog Set Src Address"
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|
hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set"
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|
line.long 0x8 "PCNT,Prog Set Count"
|
|
hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."
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|
hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
|
|
line.long 0xC "PDST,Prog Set Dst Address"
|
|
hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set"
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|
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
|
|
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
|
|
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.."
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|
rgroup.long ($2+0x214)++0x3
|
|
line.long 0x0 "PMPPRXY,Prog Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
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|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "SAOPT,Src Actv Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
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|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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|
rgroup.long ($2+0x244)++0x23
|
|
line.long 0x0 "SASRC,Src Actv Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set"
|
|
line.long 0x4 "SACNT,Src Actv Set A-Count"
|
|
hexmask.long.tbyte 0x4 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
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|
line.long 0x8 "SADST,Src Actv Set Dst Address"
|
|
hexmask.long 0x8 0.--31. 1. "DADDR,Destination address for Source Active Register Set"
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|
line.long 0xC "SABIDX,Src Actv Set B-Dim Idx"
|
|
hexmask.long.word 0xC 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
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hexmask.long.word 0xC 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used.."
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|
line.long 0x10 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
|
|
bitfld.long 0x10 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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|
bitfld.long 0x10 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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hexmask.long.byte 0x10 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
line.long 0x14 "SACNTRLD,Src Actv Set Cnt Reload"
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hexmask.long.word 0x14 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.."
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line.long 0x18 "SASRCBREF,Src Actv Set Src Addr B-Reference"
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hexmask.long 0x18 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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|
line.long 0x1C "SADSTBREF,Src Actv Set Dst Addr B-Reference"
|
|
hexmask.long 0x1C 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."
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|
line.long 0x20 "SABCNT,Src Actv Set B-Count"
|
|
hexmask.long.word 0x20 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT.."
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|
rgroup.long ($2+0x280)++0x7
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|
line.long 0x0 "DFCNTRLD,Dst FIFO Set Cnt Reload"
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|
hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by.."
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line.long 0x4 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
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|
hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
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|
group.long ($2+0x300)++0x3
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|
line.long 0x0 "DFOPT$1,Dst FIFO Set Options"
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|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
|
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x304)++0x3
|
|
line.long 0x0 "DFSRC$1,Dst FIFO Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."
|
|
repeat.end
|
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repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x308)++0x3
|
|
line.long 0x0 "DFACNT$1,Dst FIFO Set A-Count"
|
|
hexmask.long.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x30C)++0x3
|
|
line.long 0x0 "DFDST$1,Dst FIFO Set Dst Address"
|
|
hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set: Initial value is copied from PDST.DADDR. TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued. When a TR.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x310)++0x3
|
|
line.long 0x0 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
|
|
hexmask.long.word 0x0 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x314)++0x3
|
|
line.long 0x0 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x318)++0x3
|
|
line.long 0x0 "DFBCNT$1,Dst FIFO Set B-Count"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x61A0000 ad:0x61C0000)
|
|
tree "DSS_TPTC_B$1"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x100)++0x7
|
|
line.long 0x0 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3"
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|
bitfld.long 0x0 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
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|
newline
|
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bitfld.long 0x0 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 2. "WSACTV,Write Status Active WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands. WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write.." "0: Write status is not pending,1: Write Status is pending"
|
|
newline
|
|
bitfld.long 0x0 1. "SRCACTV,Source Active State SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1]. SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.."
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|
bitfld.long 0x0 0. "PROGBUSY,Program Register Set Busy PROGBUSY = 0 : Prog set idle and is available for programming. PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy"
|
|
line.long 0x4 "INTSTAT,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "TRDONE,TR Done Event Status: TRDONE = 0 : Condition not detected. TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to.." "0: Condition not detected,1: Set when TC has completed a Transfer Request"
|
|
bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY = 0 : Condition not detected. PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.."
|
|
group.long ($2+0x108)++0x3
|
|
line.long 0x0 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE = 0 : TRDONE Event is disabled. INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.."
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled. INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.."
|
|
wgroup.long ($2+0x10C)++0x7
|
|
line.long 0x0 "INTCLR,Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE = 0 : Writes of '0' have no effect. INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect. INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
line.long 0x4 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x4 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
|
|
rgroup.long ($2+0x120)++0x3
|
|
line.long 0x0 "ERRSTAT,Error Status Register"
|
|
bitfld.long 0x0 3. "MMRAERR,MMR Address Error: MMRAERR = 0 : Condition not detected. MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.."
|
|
bitfld.long 0x0 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Bus Error Event: BUSERR = 0: Condition not detected. BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.."
|
|
group.long ($2+0x124)++0x3
|
|
line.long 0x0 "ERREN,Error Enable Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR = 0 : BUSERR is disabled. ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.."
|
|
bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR = 0 : BUSERR is disabled. ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.."
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|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR = 0 : BUSERR is disabled. ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.."
|
|
wgroup.long ($2+0x128)++0x3
|
|
line.long 0x0 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR = 0 : Writes of '0' have no effect. ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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|
bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR = 0 : Writes of '0' have no effect. ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR = 0 : Writes of '0' have no effect. ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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|
rgroup.long ($2+0x12C)++0x3
|
|
line.long 0x0 "ERRDET,Error Details Register"
|
|
bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
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|
bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "15-14,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."
|
|
hexmask.long.byte 0x0 0.--3. 1. "13-8,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle.."
|
|
wgroup.long ($2+0x130)++0x3
|
|
line.long 0x0 "ERRCMD,Error Command Register"
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|
bitfld.long 0x0 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
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|
bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
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|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7"
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|
group.long ($2+0x200)++0x13
|
|
line.long 0x0 "POPT,Prog Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
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|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
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|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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|
line.long 0x4 "PSRC,Prog Set Src Address"
|
|
hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set"
|
|
line.long 0x8 "PCNT,Prog Set Count"
|
|
hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."
|
|
hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
|
|
line.long 0xC "PDST,Prog Set Dst Address"
|
|
hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set"
|
|
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
|
|
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
|
|
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.."
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|
rgroup.long ($2+0x214)++0x3
|
|
line.long 0x0 "PMPPRXY,Prog Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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|
hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
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|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "SAOPT,Src Actv Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
rgroup.long ($2+0x244)++0x23
|
|
line.long 0x0 "SASRC,Src Actv Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set"
|
|
line.long 0x4 "SACNT,Src Actv Set A-Count"
|
|
hexmask.long.tbyte 0x4 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
|
|
line.long 0x8 "SADST,Src Actv Set Dst Address"
|
|
hexmask.long 0x8 0.--31. 1. "DADDR,Destination address for Source Active Register Set"
|
|
line.long 0xC "SABIDX,Src Actv Set B-Dim Idx"
|
|
hexmask.long.word 0xC 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
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|
hexmask.long.word 0xC 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used.."
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|
line.long 0x10 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
|
|
bitfld.long 0x10 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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|
bitfld.long 0x10 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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hexmask.long.byte 0x10 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
line.long 0x14 "SACNTRLD,Src Actv Set Cnt Reload"
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hexmask.long.word 0x14 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.."
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line.long 0x18 "SASRCBREF,Src Actv Set Src Addr B-Reference"
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hexmask.long 0x18 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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line.long 0x1C "SADSTBREF,Src Actv Set Dst Addr B-Reference"
|
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hexmask.long 0x1C 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."
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|
line.long 0x20 "SABCNT,Src Actv Set B-Count"
|
|
hexmask.long.word 0x20 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT.."
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|
rgroup.long ($2+0x280)++0x7
|
|
line.long 0x0 "DFCNTRLD,Dst FIFO Set Cnt Reload"
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|
hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by.."
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|
line.long 0x4 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
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hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
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|
group.long ($2+0x300)++0x3
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|
line.long 0x0 "DFOPT$1,Dst FIFO Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
|
|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x304)++0x3
|
|
line.long 0x0 "DFSRC$1,Dst FIFO Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x308)++0x3
|
|
line.long 0x0 "DFACNT$1,Dst FIFO Set A-Count"
|
|
hexmask.long.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x30C)++0x3
|
|
line.long 0x0 "DFDST$1,Dst FIFO Set Dst Address"
|
|
hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set: Initial value is copied from PDST.DADDR. TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued. When a TR.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x310)++0x3
|
|
line.long 0x0 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
|
|
hexmask.long.word 0x0 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x314)++0x3
|
|
line.long 0x0 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x318)++0x3
|
|
line.long 0x0 "DFBCNT$1,Dst FIFO Set B-Count"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5)(list ad:0x61E0000 ad:0x6200000 ad:0x6220000 ad:0x6240000 ad:0x6260000 ad:0x6280000)
|
|
tree "DSS_TPTC_C$1"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x100)++0x7
|
|
line.long 0x0 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3"
|
|
bitfld.long 0x0 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "WSACTV,Write Status Active WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands. WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write.." "0: Write status is not pending,1: Write Status is pending"
|
|
newline
|
|
bitfld.long 0x0 1. "SRCACTV,Source Active State SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1]. SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.."
|
|
bitfld.long 0x0 0. "PROGBUSY,Program Register Set Busy PROGBUSY = 0 : Prog set idle and is available for programming. PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy"
|
|
line.long 0x4 "INTSTAT,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "TRDONE,TR Done Event Status: TRDONE = 0 : Condition not detected. TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to.." "0: Condition not detected,1: Set when TC has completed a Transfer Request"
|
|
bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY = 0 : Condition not detected. PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.."
|
|
group.long ($2+0x108)++0x3
|
|
line.long 0x0 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE = 0 : TRDONE Event is disabled. INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.."
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled. INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.."
|
|
wgroup.long ($2+0x10C)++0x7
|
|
line.long 0x0 "INTCLR,Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE = 0 : Writes of '0' have no effect. INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect. INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
line.long 0x4 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x4 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
|
|
rgroup.long ($2+0x120)++0x3
|
|
line.long 0x0 "ERRSTAT,Error Status Register"
|
|
bitfld.long 0x0 3. "MMRAERR,MMR Address Error: MMRAERR = 0 : Condition not detected. MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.."
|
|
bitfld.long 0x0 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Bus Error Event: BUSERR = 0: Condition not detected. BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.."
|
|
group.long ($2+0x124)++0x3
|
|
line.long 0x0 "ERREN,Error Enable Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR = 0 : BUSERR is disabled. ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.."
|
|
bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR = 0 : BUSERR is disabled. ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.."
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|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR = 0 : BUSERR is disabled. ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.."
|
|
wgroup.long ($2+0x128)++0x3
|
|
line.long 0x0 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR = 0 : Writes of '0' have no effect. ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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|
bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR = 0 : Writes of '0' have no effect. ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR = 0 : Writes of '0' have no effect. ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
|
|
rgroup.long ($2+0x12C)++0x3
|
|
line.long 0x0 "ERRDET,Error Details Register"
|
|
bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
|
|
bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
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|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "15-14,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."
|
|
hexmask.long.byte 0x0 0.--3. 1. "13-8,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle.."
|
|
wgroup.long ($2+0x130)++0x3
|
|
line.long 0x0 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x0 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x200)++0x13
|
|
line.long 0x0 "POPT,Prog Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
|
|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
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bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
line.long 0x4 "PSRC,Prog Set Src Address"
|
|
hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set"
|
|
line.long 0x8 "PCNT,Prog Set Count"
|
|
hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."
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|
hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
|
|
line.long 0xC "PDST,Prog Set Dst Address"
|
|
hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set"
|
|
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
|
|
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
|
|
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.."
|
|
rgroup.long ($2+0x214)++0x3
|
|
line.long 0x0 "PMPPRXY,Prog Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
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|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "SAOPT,Src Actv Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
|
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
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bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
|
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bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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|
rgroup.long ($2+0x244)++0x23
|
|
line.long 0x0 "SASRC,Src Actv Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set"
|
|
line.long 0x4 "SACNT,Src Actv Set A-Count"
|
|
hexmask.long.tbyte 0x4 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
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|
line.long 0x8 "SADST,Src Actv Set Dst Address"
|
|
hexmask.long 0x8 0.--31. 1. "DADDR,Destination address for Source Active Register Set"
|
|
line.long 0xC "SABIDX,Src Actv Set B-Dim Idx"
|
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hexmask.long.word 0xC 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
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hexmask.long.word 0xC 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used.."
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|
line.long 0x10 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
|
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bitfld.long 0x10 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x10 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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hexmask.long.byte 0x10 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
line.long 0x14 "SACNTRLD,Src Actv Set Cnt Reload"
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hexmask.long.word 0x14 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.."
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line.long 0x18 "SASRCBREF,Src Actv Set Src Addr B-Reference"
|
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hexmask.long 0x18 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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line.long 0x1C "SADSTBREF,Src Actv Set Dst Addr B-Reference"
|
|
hexmask.long 0x1C 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."
|
|
line.long 0x20 "SABCNT,Src Actv Set B-Count"
|
|
hexmask.long.word 0x20 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT.."
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|
rgroup.long ($2+0x280)++0x7
|
|
line.long 0x0 "DFCNTRLD,Dst FIFO Set Cnt Reload"
|
|
hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by.."
|
|
line.long 0x4 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
|
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hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "DFOPT$1,Dst FIFO Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
|
|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
|
|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x304)++0x3
|
|
line.long 0x0 "DFSRC$1,Dst FIFO Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x308)++0x3
|
|
line.long 0x0 "DFACNT$1,Dst FIFO Set A-Count"
|
|
hexmask.long.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x30C)++0x3
|
|
line.long 0x0 "DFDST$1,Dst FIFO Set Dst Address"
|
|
hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set: Initial value is copied from PDST.DADDR. TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued. When a TR.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x310)++0x3
|
|
line.long 0x0 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
|
|
hexmask.long.word 0x0 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x314)++0x3
|
|
line.long 0x0 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x318)++0x3
|
|
line.long 0x0 "DFBCNT$1,Dst FIFO Set B-Count"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x61E0000
|
|
tree "DSS_WDT"
|
|
base ad:0x6F7A200
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "RTIGCTRL,Global Control Register starts / stops the counters"
|
|
hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved. Reads return 0 and writes have no effect"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.."
|
|
newline
|
|
bitfld.long 0x0 15. "COS,COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while.." "0: stop counters in debug mode,1: continue counting in debug mode"
|
|
hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved. Reads return 0 and writes have no effect"
|
|
newline
|
|
bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bit.."
|
|
bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bits source.."
|
|
line.long 0x4 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
|
|
hexmask.long 0x4 2.--31. 1. "RESERVED3,Reserved"
|
|
bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
|
|
newline
|
|
bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
|
|
line.long 0x8 "RTICAPCTRL,Capture Control controls the capture source for the counters"
|
|
hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1. This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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line.long 0xC "RTICOMPCTRL,Compare Control controls the source for the compare registers"
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hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 9.--11. "RESERVED7,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 5.--7. "RESERVED6,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 1.--3. "RESERVED5,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
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hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
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hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
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hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
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group.long 0x20++0x7
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line.long 0x0 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0.."
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line.long 0x4 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0."
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group.long 0x30++0xB
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line.long 0x0 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
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hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x4 "RTIUC1,Up Counter 1 current value of prescale counter 1"
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hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x8 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
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hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
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group.long 0x40++0x7
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line.long 0x0 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1.."
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line.long 0x4 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1."
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group.long 0x50++0x27
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line.long 0x0 "RTICOMP0,Compare 0 compare value to be compared with the counters"
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hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x4 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
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hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x8 "RTICOMP1,Compare 1 compare value to be compared with the counters"
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hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0xC "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
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hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register. This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
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hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
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hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
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hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
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hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
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hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when.."
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line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
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hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.."
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group.long 0x80++0xB
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line.long 0x0 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,1: interrupt is enabled Privilege mode"
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bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
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hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
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hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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group.long 0x90++0x2F
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line.long 0x0 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
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hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled).."
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line.long 0x4 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
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hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts.."
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line.long 0x8 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
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hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read):.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 -> 1 threshold not exceeded 1 = AWD pin 0 -> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
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line.long 0xC "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
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hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.."
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line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
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hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved. Reads return 0 and writes have no effect"
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hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.."
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line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
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hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.."
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line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
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hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read) privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital.."
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line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
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hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled."
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|
hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved. Reads return 0 and writes have no effect"
|
|
hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled."
|
|
newline
|
|
hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved. Reads return 0 and writes have no effect"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled."
|
|
newline
|
|
hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved. Reads return 0 and writes have no effect"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled."
|
|
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
|
|
hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.."
|
|
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
|
|
hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.."
|
|
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
|
|
hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.."
|
|
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
|
|
hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.."
|
|
tree.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x401A0000 ad:0x401C0000)
|
|
tree "MPU_DSS_HWA_DMA$1"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long ($2+0x10)++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long ($2+0x24)++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long ($2+0x100)++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long ($2+0x200)++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long ($2+0x210)++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long ($2+0x220)++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long ($2+0x230)++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long ($2+0x240)++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long ($2+0x250)++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long ($2+0x260)++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long ($2+0x270)++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long ($2+0x280)++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x290)++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x2A0)++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x2B0)++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x2C0)++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x2D0)++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x2E0)++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x2F0)++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long ($2+0x300)++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long ($2+0x308)++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x401A0000
|
|
tree "MPU_DSS_HWA_PROC"
|
|
base ad:0x401E0000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_DSS_L3_BANKA"
|
|
base ad:0x40120000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_DSS_L3_BANKB"
|
|
base ad:0x40140000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_DSS_L3_BANKC"
|
|
base ad:0x40160000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_DSS_L3_BANKD"
|
|
base ad:0x40180000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_DSS_MBOX"
|
|
base ad:0x40200000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_MSS_CR5A_AXIS"
|
|
base ad:0x400E0000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_MSS_CR5B_AXIS"
|
|
base ad:0x40100000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_MSS_L2_BANKA"
|
|
base ad:0x40020000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_MSS_L2_BANKB"
|
|
base ad:0x40040000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_MSS_MBOX"
|
|
base ad:0x40080000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_MSS_PCRA"
|
|
base ad:0x400A0000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MPU_MSS_QSPI"
|
|
base ad:0x400C0000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "Revision,Revision"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "reserved,Always read a s0. Writes have no affect." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "modID,Module ID field."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL revision.Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "revmaj,Majo revision." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "revcustom,Custom revision." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor revision."
|
|
line.long 0x4 "Configuration,Configuration"
|
|
hexmask.long.byte 0x4 24.--31. 1. "address_align,Address alignment for range checking."
|
|
hexmask.long.byte 0x4 20.--23. 1. "num_fixed,Number of fixed address ranges Configurable as 0 or 1."
|
|
hexmask.long.byte 0x4 16.--19. 1. "num_prog,Number of programmable address ranges.Value is determined by configuration"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "num_fixed_aids,Number of supported AIDs. 0 = no specific AIDs supported (all treated equally) N = PrivIDs from 0 to N-1 supported others use AIDX"
|
|
hexmask.long.word 0x4 1.--11. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 0. "assumed_allowed,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
|
|
hexmask.long 0x0 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 1. "addr_err,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x0 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x4 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
|
|
hexmask.long 0x4 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x4 1. "enabled_addr_err,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x4 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x8 "Interrupt Enable,Interrupt Enable"
|
|
hexmask.long 0x8 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x8 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "Interrupt Enable Clear,Interrupt Enable Clear"
|
|
hexmask.long 0xC 2.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0xC 1. "addr_err_en_clr,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "prot_err_en_clr,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "EOI,EOI"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "Interrupt Vector,Interrupt Vector"
|
|
hexmask.long 0x0 0.--31. 1. "intr_vec,Interrupt vector. Reads mpu_intr_vector input signal."
|
|
rgroup.long 0x100++0xB
|
|
line.long 0x0 "Fixed Start Address,Fixed Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Fixed End Address,Fixed End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Fixed MPPA,Fixed MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "Programmable 1 Start Address,Programmable 1 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 1 End Address,Programmable 1 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 1 MPPA,Programmable 1 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x210++0xB
|
|
line.long 0x0 "Programmable 2 Start Address,Programmable 2 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 2 End Address,Programmable 2 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 2 MPPA,Programmable 2 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "Programmable 3 Start Address,Programmable 3 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 3 End Address,Programmable 3 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 3 MPPA,Programmable 3 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x230++0xB
|
|
line.long 0x0 "Programmable 4 Start Address,Programmable 4 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 4 End Address,Programmable 4 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 4 MPPA,Programmable 4 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x240++0xB
|
|
line.long 0x0 "Programmable 5 Start Address,Programmable 5 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 5 End Address,Programmable 5 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 5 MPPA,Programmable 5 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x250++0xB
|
|
line.long 0x0 "Programmable 6 Start Address,Programmable 6 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 6 End Address,Programmable 6 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 6 MPPA,Programmable 6 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "Programmable 7 Start Address,Programmable 7 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 7 End Address,Programmable 7 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 7 MPPA,Programmable 7 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
group.long 0x270++0xB
|
|
line.long 0x0 "Programmable 8 Start Address,Programmable 8 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Start address for range N. Defaults to input signal value."
|
|
line.long 0x4 "Programmable 8 End Address,Programmable 8 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,End address for range N. Defaults to input signal value."
|
|
line.long 0x8 "Programmable 8 MPPA,Programmable 8 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Always read as 0."
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions."
|
|
bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1"
|
|
newline
|
|
rbitfld.long 0x8 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x8 7. "ns,Non-secure permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 6. "emu,Debug permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Supervisor read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 4. "sw,Supervisor write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 3. "sx,Supervisor executable permission. Defaults to input value." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,User read permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 1. "uw,User write permission. Defaults to input value." "0,1"
|
|
bitfld.long 0x8 0. "ux,User executable permission. Defaults to input value." "0,1"
|
|
rgroup.long 0x280++0xB
|
|
line.long 0x0 "Programmable 9 Start Address,Programmable 9 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 9 End Address,Programmable 9 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 9 MPPA,Programmable 9 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x290++0xB
|
|
line.long 0x0 "Programmable 10 Start Address,Programmable 10 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 10 End Address,Programmable 10 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 10 MPPA,Programmable 10 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2A0++0xB
|
|
line.long 0x0 "Programmable 11 Start Address,Programmable 11 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 11 End Address,Programmable 11 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 11 MPPA,Programmable 11 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2B0++0xB
|
|
line.long 0x0 "Programmable 12 Start Address,Programmable 12 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 12 End Address,Programmable 12 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 12 MPPA,Programmable 12 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2C0++0xB
|
|
line.long 0x0 "Programmable 13 Start Address,Programmable 13 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 13 End Address,Programmable 13 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 13 MPPA,Programmable 13 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2D0++0xB
|
|
line.long 0x0 "Programmable 14 Start Address,Programmable 14 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 14 End Address,Programmable 14 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 14 MPPA,Programmable 14 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2E0++0xB
|
|
line.long 0x0 "Programmable 15 Start Address,Programmable 15 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 15 End Address,Programmable 15 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 15 MPPA,Programmable 15 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x2F0++0xB
|
|
line.long 0x0 "Programmable 16 Start Address,Programmable 16 Start Address"
|
|
hexmask.long 0x0 0.--31. 1. "start_addr,Reserved not used in Design"
|
|
line.long 0x4 "Programmable 16 End Address,Programmable 16 End Address"
|
|
hexmask.long 0x4 0.--31. 1. "end_addr,Reserved not used in Design"
|
|
line.long 0x8 "Programmable 16 MPPA,Programmable 16 MPPA"
|
|
hexmask.long.byte 0x8 26.--31. 1. "reserved,Reserved not used in Design"
|
|
hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design"
|
|
bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "reserved1,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 7. "ns,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 6. "emu,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "sr,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 4. "sw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 3. "sx,Reserved not used in Design" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ur,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 1. "uw,Reserved not used in Design" "0,1"
|
|
bitfld.long 0x8 0. "ux,Reserved not used in Design" "0,1"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "Fault Address,Fault Address"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault address."
|
|
line.long 0x4 "Fault Status,Fault Status"
|
|
hexmask.long.byte 0x4 24.--31. 1. "id,Transfer ID"
|
|
hexmask.long.byte 0x4 16.--23. 1. "mstid,Master ID."
|
|
bitfld.long 0x4 13.--15. "reserved,Always read as 0." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--12. 1. "privid,Privilege ID."
|
|
bitfld.long 0x4 8. "reserved1,Always read as 0." "0,1"
|
|
bitfld.long 0x4 7. "ns,Non-secure access." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "reserved2,Always read as 0." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault type. 100000 = supervisor read fault 010000 = supervisor write fault 001000 = supervisor execute fault 000100 = user read fault 000010 = user write fault 000001 = user execute fault 111111 = relaxed cache linefill fault 010010 = relaxed.."
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "Fault Clear,Fault Clear"
|
|
hexmask.long 0x0 1.--31. 1. "reserved,Always read as 0."
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MSS_CCMR"
|
|
base ad:0x2F7AC00
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CCMSR1,CPU Compare Status Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "NU2,Reserved"
|
|
bitfld.long 0x0 16. "CMPE1,Compare Error 0 = CPU signals are identical 1= CPU signal compare mismatch Writes '1' to clear this bit" "0: CPU signals are identical,1: CPU signal compare mismatch Writes '1' to clear.."
|
|
newline
|
|
hexmask.long.byte 0x0 9.--15. 1. "NU1,Reserved"
|
|
bitfld.long 0x0 8. "STC1,Self Test Complete 0 = self test on-going if self test mode asserted 1 = self test is complete Writes have no effect" "0: self test on-going if self test mode asserted,1: self test is complete Writes have no effect"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--7. 1. "NU0,Reserved"
|
|
bitfld.long 0x0 1. "STET1,Self Test Error Type 0 = self test failed during Compare Match test 1 = self test failed during Compare mismatch test Writes have no effect" "0: self test failed during Compare Match test,1: self test failed during Compare mismatch test.."
|
|
newline
|
|
rbitfld.long 0x0 0. "STE1,Self Test Error 0 = self test passed 1 = self test failed Writes have no effect" "0: self test passed,1: self test failed Writes have no effect"
|
|
line.long 0x4 "CCMKEYR1,CPU Compare Key Register"
|
|
hexmask.long 0x4 4.--31. 1. "NU3,Reserved"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MKEY1,Mode Key 0000 = lock step mode 0110 = self test mode 1001 = error forcing mode 1111 = self test error forcing mode"
|
|
line.long 0x8 "CCMSR2,VIM Compare Status Register"
|
|
hexmask.long.word 0x8 17.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0x8 16. "CMPE2,Compare Error 0 = VIM signals are identical 1= VIM signal compare mismatch Writes '1' to clear this bit" "0: VIM signals are identical,1: VIM signal compare mismatch Writes '1' to clear.."
|
|
newline
|
|
hexmask.long.byte 0x8 9.--15. 1. "NU5,Reserved"
|
|
bitfld.long 0x8 8. "STC2,Self Test Complete 0 = self test on-going if self test mode asserted 1 = self test is complete Writes have no effect" "0: self test on-going if self test mode asserted,1: self test is complete Writes have no effect"
|
|
newline
|
|
hexmask.long.byte 0x8 2.--7. 1. "NU4,Reserved"
|
|
bitfld.long 0x8 1. "STET2,Self Test Error Type 0 = self test failed during Compare Match test 1 = self test failed during Compare mismatch test Writes have no effect" "0: self test failed during Compare Match test,1: self test failed during Compare mismatch test.."
|
|
newline
|
|
bitfld.long 0x8 0. "STE2,Self Test Error 0 = self test passed 1 = self test failed Writes have no effect" "0: self test passed,1: self test failed Writes have no effect"
|
|
line.long 0xC "CCMKEYR2,VIM Compare Key Register"
|
|
hexmask.long 0xC 4.--31. 1. "NU7,Reserved"
|
|
hexmask.long.byte 0xC 0.--3. 1. "MKEY2,Mode Key 0000 = lock step mode 0110 = self test mode 1001 = error forcing mode 1111 = self test error forcing mode"
|
|
line.long 0x10 "CCMSR3,Inactivity Monitor Status Register"
|
|
hexmask.long.word 0x10 17.--31. 1. "NU10,Reserved"
|
|
bitfld.long 0x10 16. "CMPE3,Compare Error 0 = Inactivity monitor signals are identical 1= Inactivity monitor signal compare mismatch Writes '1' to clear this bit" "0: Inactivity monitor signals are identical,1: Inactivity monitor signal compare mismatch.."
|
|
newline
|
|
hexmask.long.byte 0x10 9.--15. 1. "NU9,Reserved"
|
|
bitfld.long 0x10 8. "STC3,Self Test Complete 0 = self test on-going if self test mode asserted 1 = self test is complete Writes have no effect" "0: self test on-going if self test mode asserted,1: self test is complete Writes have no effect"
|
|
newline
|
|
hexmask.long.byte 0x10 2.--7. 1. "NU8,Reserved"
|
|
bitfld.long 0x10 1. "STET3,Self Test Error Type 0 = self test failed during Compare Match test 1 = self test failed during Compare mismatch test Writes have no effect" "0: self test failed during Compare Match test,1: self test failed during Compare mismatch test.."
|
|
newline
|
|
rbitfld.long 0x10 0. "STE3,Self Test Error 0 = self test passed 1 = self test failed Writes have no effect" "0: self test passed,1: self test failed Writes have no effect"
|
|
line.long 0x14 "CCMKEYR3,Inactivity Monitor Key Register"
|
|
hexmask.long 0x14 4.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x14 0.--3. 1. "MKEY3,Mode Key 0000 = lock step mode 0110 = self test mode 1001 = error forcing mode 1111 = self test error forcing mode"
|
|
line.long 0x18 "CCMPOLCNTRL,CPU Compare Polarity Control Register"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "NU12,Reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode. User and privilege mode read = Returns current value of the POL INV Privilege mode write = Update the values of POL INV"
|
|
tree.end
|
|
tree "MSS_CPSW"
|
|
base ad:0x7000000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SS_IDVER_REG,SS ID Version Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "SS_SYNCE_COUNT_REG,SS SYNCE Count Register"
|
|
hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value"
|
|
line.long 0x4 "SS_SYNCE_MUX_REG,SS Synce Mux Register"
|
|
hexmask.long.byte 0x4 0.--5. 1. "SYNCE_SEL,Sync E Select Value"
|
|
line.long 0x8 "SS_CONTROL_REG,SS Control Register"
|
|
bitfld.long 0x8 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW 1=The low power indicate state does not gate the clock to the CPSW" "0: The low power indicate state includes gating off..,1: The low power indicate state does not gate the.."
|
|
newline
|
|
bitfld.long 0x8 0. "EEE_EN,Energy Efficient Ethernet Enable: 0=EEE is disabled 1=EEE is enabled" "0: EEE is disabled,1: EEE is enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SS_INT_CONTROL_REG,SS Interrupt Control Register"
|
|
bitfld.long 0x0 31. "INT_TEST,Interrupt Test" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "INT_BYPASS,Interrupt Bypass Value"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "INT_PRESCALE,Interrupt Prescale Value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SS_STATUS_REG,SS Status Register"
|
|
bitfld.long 0x0 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "SS_RGMII1_STATUS_REG,RGMII1 Status Register"
|
|
bitfld.long 0x0 3. "FULLDUPLEX,Rgmii full dulex: 0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "SPEED,Rgmii1 speed: 00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0. "LINK,Rgmii1 link indicator: 0=Link is down 1=Link is up" "0: Link is down,1: Link is up"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "SS_TH_THRESH_PULSE_EN_REG,THost Threshold Pulse Interrupt Enable Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_EN,THost Threshold Pulse Interrupt Enable Register"
|
|
line.long 0x4 "SS_TH_PULSE_EN_REG,THost Pulse Interrupt Enable Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_EN,THost Pulse Interrupt Enable Register"
|
|
line.long 0x8 "SS_FH_PULSE_EN_REG,FHost Pulse Interrupt Enable Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_EN,FHost Pulse Interrupt Enable Register"
|
|
line.long 0xC "SS_MISC_EN_REG,Misc Interrupt Enable Register"
|
|
bitfld.long 0xC 6. "DED_PEND_EN,MISC DED Memory Protect Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SEC_PEND_EN,MISC SEC Memory Protect Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "EVNT_PEND_EN,MISC CPTS Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "STAT_PEND_EN,MISC Statistics Interrupt Enable - OR of bits n downto 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "HOST_PEND_EN,MISC Host Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "MDIO_LINKINT_EN,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "MDIO_USERINT_EN,MISC_MDIO userint interrupt enable - OR of bits 1 and 0" "0,1"
|
|
rgroup.long 0xB0++0xB
|
|
line.long 0x0 "SS_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TH_THRESH_PULSE_ST,THost Threshold Pulse Interrupt Status Register"
|
|
line.long 0x4 "SS_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TH_PULSE_STATUS,THost Pulse Interrupt Status Register"
|
|
line.long 0x8 "SS_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "FH_PULSE_STATUS,FHost Pulse Interrupt Status Register"
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "SS_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted"
|
|
bitfld.long 0x0 6. "DED_PEND,MISC DED Memory Protect Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SEC_PEND,MISC SEC Memory Protect Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EVNT_PEND,MISC CPTS Event Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STAT_PEND,MISC Statistics Interrupt - OR of bits n downto 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HOST_PEND,MISC Host Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MDIO_LINKINT,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MDIO_USERINT,MISC_MDIO userint interrupt - OR of bits 1 and 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "SS_TH_IMAX_REG,THost Interrupt Max Register Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TH_IMAX,THost Interrupt Max Register Register"
|
|
line.long 0x4 "SS_FH_IMAX_REG,FHost Interrupt Max Register Register"
|
|
hexmask.long.byte 0x4 0.--5. 1. "FH_IMAX,FHost Interrupt Max Register Register"
|
|
rgroup.long 0xF00++0x3
|
|
line.long 0x0 "MDIO_VERSION_REG,MDIO Version Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
|
|
group.long 0xF04++0x7
|
|
line.long 0x0 "MDIO_CONTROL_REG,MDIO Control Register"
|
|
rbitfld.long 0x0 31. "IDLE,MDIO state machine idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "ENABLE,Enable control" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "HIGHEST_USER_CHANNEL,Highest user channel"
|
|
newline
|
|
bitfld.long 0x0 20. "PREAMBLE,Preamble disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "FAULT,Fault indicator" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CLKDIV,Clock divider"
|
|
line.long 0x4 "MDIO_ALIVE_REG,MDIO Alive Register"
|
|
hexmask.long 0x4 0.--31. 1. "ALIVE,MDIO alive"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "MDIO_LINK_REG,MDIO Link Register"
|
|
hexmask.long 0x0 0.--31. 1. "LINK,MDIO link state"
|
|
group.long 0xF10++0x37
|
|
line.long 0x0 "MDIO_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
|
|
bitfld.long 0x0 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
|
|
line.long 0x4 "LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
|
|
bitfld.long 0x4 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
|
|
line.long 0x8 "LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
|
|
bitfld.long 0x8 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
|
|
line.long 0xC "LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
|
|
bitfld.long 0xC 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
|
|
line.long 0x10 "USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
|
|
bitfld.long 0x10 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
|
|
line.long 0x14 "USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
|
|
bitfld.long 0x14 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
|
|
line.long 0x18 "USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
|
|
bitfld.long 0x18 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
|
|
line.long 0x1C "USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
|
|
bitfld.long 0x1C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
|
|
line.long 0x20 "MANUAL_IF_REG,MDIO Manual Interface Register"
|
|
bitfld.long 0x20 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "MDIO_OE,MDIO Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x20 0. "MDIO_PIN,MDIO Pin" "0,1"
|
|
line.long 0x24 "POLL_REG,MDIO Poll Register"
|
|
bitfld.long 0x24 31. "MANUALMODE,MDIO Manual Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x24 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--7. 1. "IPG,MDIO IPG"
|
|
line.long 0x28 "POLL_EN_REG,MDIO Poll Enable Register"
|
|
hexmask.long 0x28 0.--31. 1. "POLL_EN,MDIO Poll Enable"
|
|
line.long 0x2C "CLAUS45_REG,MDIO Clause45 Register"
|
|
hexmask.long 0x2C 0.--31. 1. "CLAUSE45,MDIO Clause 45"
|
|
line.long 0x30 "USER_ADDR0_REG,MDIO Address 0 Register"
|
|
hexmask.long.word 0x30 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
|
|
line.long 0x34 "USER_ADDR1_REG,MDIO Address 1 Register"
|
|
hexmask.long.word 0x34 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
|
|
group.long 0xF80++0x7
|
|
line.long 0x0 "USER_ACCESS_REG,MDIO User Access Register"
|
|
bitfld.long 0x0 31. "GO,Go" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "WRITE,Write" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ACK,Acknowledge" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "REGADR,Register address"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "PHYADR,PHY address"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,User data"
|
|
line.long 0x4 "USER_PHY_SEL_REG,MDIO User PHY Select Register"
|
|
bitfld.long 0x4 7. "LINKSEL,Link status determination select" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "PHYADR_MON,PHY address whose link status is monitored"
|
|
rgroup.long 0x20000++0x3
|
|
line.long 0x0 "CPSW_ID_VER_REG,CPSW ID Version"
|
|
hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification Value"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL Version Value"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR_VER,Minor Version Value"
|
|
group.long 0x20004++0x3
|
|
line.long 0x0 "CPSW_CONTROL_REG,CPSW Switch Control"
|
|
bitfld.long 0x0 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "UNUSED,Unused" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "P0_ENABLE,Port 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1"
|
|
group.long 0x20010++0x37
|
|
line.long 0x0 "EM_CONTROL_REG,CPSW Emulation Control"
|
|
bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1"
|
|
line.long 0x4 "STAT_PORT_EN_REG,CPSW Statistics Port Enable"
|
|
bitfld.long 0x4 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
|
|
line.long 0x8 "PTYPE_REG,CPSW Transmit Priority Type"
|
|
bitfld.long 0x8 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "ESC_PRI_LD_VAL,Escalate Priority Load Value"
|
|
line.long 0xC "SOFT_IDLE_REG,CPSW Software Idle"
|
|
bitfld.long 0xC 0. "SOFT_IDLE,Software Idle" "0,1"
|
|
line.long 0x10 "THRU_RATE_REG,CPSW Thru Rate"
|
|
hexmask.long.byte 0x10 12.--15. 1. "SL_RX_THRU_RATE,Switch FIFO receive through rate"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "P0_RX_THRU_RATE,CPPI FIFO receive through rate"
|
|
line.long 0x14 "GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold"
|
|
hexmask.long.byte 0x14 0.--4. 1. "GAP_THRESH,Short Gap Threshold"
|
|
line.long 0x18 "TX_START_WDS_REG,CPSW Transmit FIFO Start Words"
|
|
hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit Start Words"
|
|
line.long 0x1C "EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value"
|
|
hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
|
|
line.long 0x20 "TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
|
|
hexmask.long.byte 0x20 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7"
|
|
newline
|
|
hexmask.long.byte 0x20 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6"
|
|
newline
|
|
hexmask.long.byte 0x20 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5"
|
|
newline
|
|
hexmask.long.byte 0x20 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4"
|
|
newline
|
|
hexmask.long.byte 0x20 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2"
|
|
newline
|
|
hexmask.long.byte 0x20 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0"
|
|
line.long 0x24 "TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear"
|
|
hexmask.long.byte 0x24 28.--31. 1. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7"
|
|
newline
|
|
hexmask.long.byte 0x24 24.--27. 1. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6"
|
|
newline
|
|
hexmask.long.byte 0x24 20.--23. 1. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5"
|
|
newline
|
|
hexmask.long.byte 0x24 16.--19. 1. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4"
|
|
newline
|
|
hexmask.long.byte 0x24 12.--15. 1. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--11. 1. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2"
|
|
newline
|
|
hexmask.long.byte 0x24 4.--7. 1. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--3. 1. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0"
|
|
line.long 0x28 "TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low"
|
|
hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
|
|
line.long 0x2C "TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
|
|
line.long 0x30 "TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low"
|
|
hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
|
|
line.long 0x34 "TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High"
|
|
hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
|
|
group.long 0x20050++0x7
|
|
line.long 0x0 "VLAN_LTYPE_REG,VLAN Length/type"
|
|
hexmask.long.word 0x0 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType"
|
|
line.long 0x4 "EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain"
|
|
hexmask.long.byte 0x4 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
|
|
group.long 0x20100++0x1F
|
|
line.long 0x0 "TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length"
|
|
hexmask.long.word 0x0 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length"
|
|
line.long 0x4 "TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length"
|
|
hexmask.long.word 0x4 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length"
|
|
line.long 0x8 "TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length"
|
|
hexmask.long.word 0x8 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length"
|
|
line.long 0xC "TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length"
|
|
hexmask.long.word 0xC 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length"
|
|
line.long 0x10 "TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length"
|
|
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length"
|
|
line.long 0x14 "TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length"
|
|
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length"
|
|
line.long 0x18 "TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length"
|
|
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length"
|
|
line.long 0x1C "TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length"
|
|
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length"
|
|
group.long 0x21004++0x7
|
|
line.long 0x0 "CPPI_P0_CONTROL_REG,CPPI Port 0 Control"
|
|
bitfld.long 0x0 18. "RX_REMAP_DSCP_V6,Port 0 Remap DSCP_V6 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RX_REMAP_DSCP_V4,Port 0 Remap DSCP_V4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RX_REMAP_VLAN,Port 0 Remap VLAN Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DSCP_IPV4_EN,Port 0 IPv4 DSCP enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RX_CHECKSUM_EN,Port 0 Receive Checksum Enable" "0,1"
|
|
line.long 0x4 "P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset"
|
|
hexmask.long.word 0x4 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
|
|
rgroup.long 0x21010++0x3
|
|
line.long 0x0 "P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count"
|
|
hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Port 0 Transmit Block Count Usage"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT,Port 0 Receive Block Count Usage"
|
|
group.long 0x21014++0x17
|
|
line.long 0x0 "P0_PORT_VLAN_REG,CPPI Port 0 VLAN"
|
|
bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID"
|
|
line.long 0x4 "P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping"
|
|
bitfld.long 0x4 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "PRI5,Priority 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "PRI3,Priority 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "PRI1,Priority 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "PRI6,Priority 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "PRI4,Priority 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "PRI2,Priority 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "P0_PRI_CTL_REG,CPPI Port 0 Priority Control"
|
|
hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
|
|
newline
|
|
bitfld.long 0x8 8. "RX_PTYPE,Receive Priority Type" "0,1"
|
|
line.long 0xC "P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map"
|
|
bitfld.long 0xC 28.--30. "22-20,Priority 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 24.--26. "14-12,Priority 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 20.--22. "6-4,Priority 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 16.--18. "2-0,Priority 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 12.--14. "PRI7,Priority 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 8.--10. "PRI6,Priority 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 4.--6. "PRI5,Priority 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 0.--2. "PRI4,Priority 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length"
|
|
hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
|
|
line.long 0x14 "P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority"
|
|
hexmask.long.byte 0x14 28.--31. 1. "PRI7,Priority 7 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 24.--27. 1. "PRI6,Priority 6 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 20.--23. 1. "PRI5,Priority 5 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--19. 1. "PRI4,Priority 4 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 12.--15. 1. "PRI3,Priority 3 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "PRI2,Priority 2 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "PRI1,Priority 1 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "PRI0,Priority 0 Port Transmit Blocks"
|
|
group.long 0x21030++0x7
|
|
line.long 0x0 "P0_IDLE2LPI_REG,Port 0 EEE Idle to LPI counter"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value"
|
|
line.long 0x4 "P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value"
|
|
rgroup.long 0x21038++0x3
|
|
line.long 0x0 "P0_EEE_STATUS_REG,Port 0 EEE status"
|
|
bitfld.long 0x0 6. "TX_FIFO_EMPTY,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RX_FIFO_EMPTY,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_FIFO_HOLD,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TX_WAKE,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX_LPI,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RX_LPI,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
|
|
group.long 0x2103C++0x3
|
|
line.long 0x0 "P0_RX_PKTS_PRI_REG,CPPI Port Receive Packets per priority"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRI7,Priority 7 Port Port 0 Receive Packets"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PRI6,Priority 6 Port Port 0 Receive Packets"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRI5,Priority 5 Port Port 0 Receive Packets"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRI4,Priority 4 Port Port 0 Receive Packets"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRI3,Priority 3 Port Port 0 Receive Packets"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRI2,Priority 2 Port Port 0 Receive Packets"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRI1,Priority 1 Port Port 0 Receive Packets"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI0,Priority 0 Port Port 0 Receive Packets"
|
|
group.long 0x2104C++0x3
|
|
line.long 0x0 "P0_RX_GAP_REG,Port 0 Receive Gap Register"
|
|
hexmask.long.word 0x0 16.--25. 1. "RX_GAP_CNT,Port 0 Receive Gap Count"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RX_GAP_EN,Port 0 Receive Gap Enable"
|
|
rgroup.long 0x21050++0x3
|
|
line.long 0x0 "P0_FIFO_STATUS_REG,Port 0 FIFO Status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,Port 0 FIFO Status"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x21120)++0x3
|
|
line.long 0x0 "P0_RX_DSCP_MAP_REG_$1,CPPI Port 0 Receive IPV4/IPV6 DSCP Map N"
|
|
bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x21140)++0x3
|
|
line.long 0x0 "P0_PRI_CIR_REG_$1,CPPI Port 0 Rx Priority P Committed Information Rate"
|
|
hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority N CIR"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x21160)++0x3
|
|
line.long 0x0 "P0_PRI_EIR_REG_$1,CPPI Port 0 Rx Priority P Excess Information Rate"
|
|
hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N EIR"
|
|
repeat.end
|
|
group.long 0x21180++0x1F
|
|
line.long 0x0 "P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0"
|
|
line.long 0x4 "P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High"
|
|
hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4"
|
|
line.long 0x8 "P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low"
|
|
hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0"
|
|
line.long 0xC "P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High"
|
|
hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4"
|
|
line.long 0x10 "P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low"
|
|
hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0"
|
|
line.long 0x14 "P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High"
|
|
hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4"
|
|
line.long 0x18 "P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low"
|
|
hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0"
|
|
line.long 0x1C "P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High"
|
|
hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4"
|
|
group.long 0x21300++0x7
|
|
line.long 0x0 "P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value"
|
|
line.long 0x4 "P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B"
|
|
hexmask.long.byte 0x4 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value"
|
|
group.long 0x21320++0x3
|
|
line.long 0x0 "P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRI7,Priority 7 Host Blocks"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PRI6,Priority 6 Host Blocks"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRI5,Priority 5 Host Blocks"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRI4,Priority 4 Host Blocks"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRI3,Priority 3 Host Blocks"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRI2,Priority 2 Host Blocks"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRI1,Priority 1 Host Blocks"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI0,Priority 0 Host Blocks"
|
|
rgroup.long 0x22000++0x3
|
|
line.long 0x0 "PN_RESERVED_REG,Reserved"
|
|
hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved register for memory map alignment"
|
|
group.long 0x22004++0x7
|
|
line.long 0x0 "PN_CONTROL_REG,Enet Port N Control"
|
|
bitfld.long 0x0 17. "EST_PORT_EN,EST Port Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_LPI_CLKSTOP_EN,Transmit LPI clockstop enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DSCP_IPV6_EN,IPv6 DSCP enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DSCP_IPV4_EN,IPv4 DSCP enable" "0,1"
|
|
line.long 0x4 "PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks"
|
|
hexmask.long.byte 0x4 8.--15. 1. "TX_MAX_BLKS,Transmit FIFO maximum blocks"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RX_MAX_BLKS,Receive FIFO maximum blocks"
|
|
rgroup.long 0x22010++0x3
|
|
line.long 0x0 "PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RX_BLK_CNT_P,Receive Prempt Queue Block Count Usage"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TX_BLK_CNT,Transmit Block Count Usage"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "RX_BLK_CNT_E,Receive Block Count Usage"
|
|
group.long 0x22014++0x23
|
|
line.long 0x0 "PN_PORT_VLAN_REG,Enet Port N VLAN"
|
|
bitfld.long 0x0 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12. "PORT_CFI,Port CFI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "PORT_VID,Port VLAN ID"
|
|
line.long 0x4 "PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping"
|
|
bitfld.long 0x4 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "PN_PRI_CTL_REG,Enet Port N Priority Control"
|
|
hexmask.long.byte 0x8 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet"
|
|
line.long 0xC "PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map"
|
|
bitfld.long 0xC 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length"
|
|
hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
|
|
line.long 0x14 "PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority"
|
|
hexmask.long.byte 0x14 28.--31. 1. "PRI7,Priority 7 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 24.--27. 1. "PRI6,Priority 6 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 20.--23. 1. "PRI5,Priority 5 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--19. 1. "PRI4,Priority 4 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 12.--15. 1. "PRI3,Priority 3 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "PRI2,Priority 2 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "PRI1,Priority 1 Port Transmit Blocks"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "PRI0,Priority 0 Port Transmit Blocks"
|
|
line.long 0x18 "PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words"
|
|
hexmask.long.word 0x18 0.--8. 1. "COUNT,Receive Flow Threshold in Words"
|
|
line.long 0x1C "PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "COUNT,EEE Idle to LPI counter load value"
|
|
line.long 0x20 "PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "COUNT,EEE LPI to wake counter load value"
|
|
rgroup.long 0x22038++0x3
|
|
line.long 0x0 "PN_EEE_STATUS_REG,Enet Port N EEE status"
|
|
bitfld.long 0x0 6. "TX_FIFO_EMPTY,Transmit FIFO (switch egress) is empty - contains no packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RX_FIFO_EMPTY,Receive FIFO (switch ingress) is empty - contains no packets" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_FIFO_HOLD,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TX_WAKE,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TX_LPI,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RX_LPI,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
|
|
rgroup.long 0x22050++0x3
|
|
line.long 0x0 "PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS"
|
|
bitfld.long 0x0 18. "EST_BUFACT,Transmit FIFO EST Buffer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EST_ADD_ERR,Transmit FIFO EST Address Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "EST_CNT_ERR,Transmit FIFO EST Count Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TX_E_MAC_ALLOW,Transmit FIFO Express Queue Priority Allow"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TX_PRI_ACTIVE,Transmit FIFO Priority Active"
|
|
group.long 0x22060++0x3
|
|
line.long 0x0 "PN_EST_CONTROL_REG,Enet Port N EST CONTROL"
|
|
hexmask.long.word 0x0 16.--25. 1. "EST_FILL_MARGIN,Transmit FIFO EST Fill Margin"
|
|
newline
|
|
hexmask.long.byte 0x0 9.--15. 1. "EST_PREMPT_COMP,Transmit FIFO EST Prempt Comparision Value"
|
|
newline
|
|
bitfld.long 0x0 8. "EST_FILL_EN,Transmit FIFO EST Fill Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "EST_TS_PRI,Transmit FIFO EST TimeStamp Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4. "EST_TS_ONEPRI,Transmit FIFO EST TimeStamp One Priority" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EST_TS_FIRST,Transmit FIFO EST TimeStamp First Express Packet" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EST_TS_EN,Transmit FIFO EST TimeStamp Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EST_BUFSEL,Transmit FIFO EST Buffer Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EST_ONEBUF,Transmit FIFO EST One Buffer" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x22120)++0x3
|
|
line.long 0x0 "PN_RX_DSCP_MAP_REG_$1,Enet Port N Receive IPV4/IPV6 DSCP Map M"
|
|
bitfld.long 0x0 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x22140)++0x3
|
|
line.long 0x0 "PN_PRI_CIR_REG_$1,Enet Port N Rx Priority P Committed Information Rate Value"
|
|
hexmask.long 0x0 0.--27. 1. "PRI_CIR,Priority N committed information rate"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x22160)++0x3
|
|
line.long 0x0 "PN_PRI_EIR_REG_$1,Enet Port N Rx Priority P Excess Informatoin Rate Value"
|
|
hexmask.long 0x0 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count"
|
|
repeat.end
|
|
group.long 0x22180++0x1F
|
|
line.long 0x0 "PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0"
|
|
line.long 0x4 "PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High"
|
|
hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4"
|
|
line.long 0x8 "PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low"
|
|
hexmask.long.byte 0x8 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0"
|
|
line.long 0xC "PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High"
|
|
hexmask.long.byte 0xC 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4"
|
|
line.long 0x10 "PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low"
|
|
hexmask.long.byte 0x10 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0"
|
|
line.long 0x14 "PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High"
|
|
hexmask.long.byte 0x14 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4"
|
|
line.long 0x18 "PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low"
|
|
hexmask.long.byte 0x18 24.--28. 1. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--20. 1. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--12. 1. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--4. 1. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0"
|
|
line.long 0x1C "PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High"
|
|
hexmask.long.byte 0x1C 24.--28. 1. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--20. 1. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--12. 1. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--4. 1. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4"
|
|
group.long 0x22300++0x23
|
|
line.long 0x0 "PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "23-21,Port PFC Destination Based Out Flow Add Value for Priority 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "15-13,Port PFC Destination Based Out Flow Add Value for Priority 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "12-8,Port PFC Destination Based Out Flow Add Value for Priority 0"
|
|
line.long 0x4 "PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High"
|
|
hexmask.long.byte 0x4 24.--28. 1. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4"
|
|
line.long 0x8 "PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8"
|
|
line.long 0xC "PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High"
|
|
hexmask.long.byte 0xC 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40"
|
|
line.long 0x10 "PN_TS_CTL_REG,Enet Port N Time Sync Control"
|
|
hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable"
|
|
newline
|
|
bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Synce Transmit Annex E Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Synce Receive Annex E Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable transmit and receive" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Synce Transmit Annex D Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_E,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_E,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Synce Transmit Annex F Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Synce Receive Annex D Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_E,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_E,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Synce Receive Annex F Enable" "0,1"
|
|
line.long 0x14 "PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)"
|
|
hexmask.long.byte 0x14 16.--21. 1. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1"
|
|
line.long 0x18 "PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2"
|
|
hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1"
|
|
line.long 0x1C "PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2"
|
|
bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2"
|
|
line.long 0x20 "PN_TS_CTL2_REG,Enet Port N Time Sync Control 2"
|
|
hexmask.long.byte 0x20 16.--21. 1. "TS_DOMAIN_OFFSET,Time Sync Domain Offset"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable"
|
|
group.long 0x22330++0x3
|
|
line.long 0x0 "PN_MAC_CONTROL_REG,Enet Port N Mac Control"
|
|
bitfld.long 0x0 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RX_CSF_EN,RX Copy Short Frames Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "RX_CEF_EN,RX Copy Error Frames Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EXT_EN,External Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GIG_FORCE,Gigabit Mode Force" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "IFCTL_B,Interface Control B" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "IFCTL_A,Interface Control A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CRC_TYPE,Port CRC Type" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMD_IDLE,Command Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GIG,Gigabit Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TX_PACE,Transmit Pacing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GMII_EN,GMII Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_FLOW_EN,Transmit Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MTEST,Manufacturing Test Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOOPBACK,Loop Back Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FULLDUPLEX,Full Duplex mode" "0,1"
|
|
rgroup.long 0x22334++0x3
|
|
line.long 0x0 "PN_MAC_STATUS_REG,Enet Port N Mac Status"
|
|
bitfld.long 0x0 31. "IDLE,cpxmac_sl IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "E_IDLE,Express cpxmac_sl IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MAC_TX_IDLE,Prempt and Express cpxmac_sl Transmit IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TORF,Top of receive FIFO flow control trigger occurred. This bit is write one to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear. This field is write 0x7 to clear." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)"
|
|
newline
|
|
bitfld.long 0x0 6. "EXT_RX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EXT_TX_FLOW_EN,External Receive Flow Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EXT_GIG,External GIG mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EXT_FULLDUPLEX,External Fullduplex" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RX_FLOW_ACT,Receive Flow Control Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_FLOW_ACT,Transmit Flow Control Active" "0,1"
|
|
group.long 0x22338++0xB
|
|
line.long 0x0 "PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset"
|
|
bitfld.long 0x0 0. "SOFT_RESET,Software reset" "0,1"
|
|
line.long 0x4 "PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test"
|
|
hexmask.long.byte 0x4 26.--30. 1. "PACEVAL,Pacing Register Current Value"
|
|
newline
|
|
hexmask.long.word 0x4 16.--25. 1. "RNDNUM,Backoff Random Number Generator"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "COLL_COUNT,Collision Count"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "TX_BACKOFF,Backoff Count"
|
|
line.long 0x8 "PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer"
|
|
hexmask.long.word 0x8 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x22350)++0x3
|
|
line.long 0x0 "PN_MAC_RXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Rx Pause Timer"
|
|
hexmask.long.word 0x0 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
|
|
repeat.end
|
|
group.long 0x22370++0x3
|
|
line.long 0x0 "PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer"
|
|
hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x22380)++0x3
|
|
line.long 0x0 "PN_MAC_TXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Tx Pause Timer"
|
|
hexmask.long.word 0x0 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
|
|
repeat.end
|
|
group.long 0x223A0++0x7
|
|
line.long 0x0 "PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control"
|
|
bitfld.long 0x0 1. "SOFT,Emulation Soft Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FREE,Emulation Free Bit" "0,1"
|
|
line.long 0x4 "PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap"
|
|
hexmask.long.word 0x4 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap"
|
|
group.long 0x223AC++0x13
|
|
line.long 0x0 "PN_INTERVLAN_OPX_POINTER_REG,Enet Port N Tx Egress InterVLAN Operation Pointer"
|
|
bitfld.long 0x0 0.--2. "INTERVLAN_OPX_POINT,Egress InterVLAN Operation Pointer" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "PN_INTERVLAN_OPX_A_REG,Enet Port N Tx Egress InterVLAN A"
|
|
hexmask.long 0x4 0.--31. 1. "INTERVLAN_OPX_A,Egress InterVLAN A"
|
|
line.long 0x8 "PN_INTERVLAN_OPX_B_REG,Enet Port N Tx Egress InterVLAN B"
|
|
hexmask.long 0x8 0.--31. 1. "INTERVLAN_OPX_B,Egress InterVLAN B"
|
|
line.long 0xC "PN_INTERVLAN_OPX_C_REG,Enet Port N Tx Egress InterVLAN C"
|
|
hexmask.long 0xC 0.--31. 1. "INTERVLAN_OPX_C,Egress InterVLAN C"
|
|
line.long 0x10 "PN_INTERVLAN_OPX_D_REG,Enet Port N Tx Egress InterVLAN D"
|
|
hexmask.long.word 0x10 0.--15. 1. "INTERVLAN_OPX_D,Egress InterVLAN D"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC)
|
|
group.long ($2+0x32000)++0x3
|
|
line.long 0x0 "FETCH_LOC_$1,The Revision Register contains the ID and revision information."
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "LOC,RAM Location"
|
|
repeat.end
|
|
rgroup.long 0x34000++0x3
|
|
line.long 0x0 "CPDMA_FH_IDVER_REG,CPDMA Transmit IDVER"
|
|
hexmask.long 0x0 0.--31. 1. "FH_IDVER,CPDMA Transmit IDVER"
|
|
group.long 0x34004++0x7
|
|
line.long 0x0 "CPDMA_FH_CONTROL_REG,CPDMA Transmit Control Register"
|
|
bitfld.long 0x0 0. "FH_EN,CPDMA Transmit DMA Enable" "0,1"
|
|
line.long 0x4 "CPDMA_FH_TEARDOWN_REG,CPDMA Transmit Teardown Register"
|
|
bitfld.long 0x4 31. "FH_TDN_RDY,CPDMA Transmit Teardown Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "FH_TDN_CH,CPDMA Transmit Teardown Channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x34010++0x3
|
|
line.long 0x0 "CPDMA_TH_IDVER_REG,CPDMA Receive IDVER"
|
|
hexmask.long 0x0 0.--31. 1. "TH_IDVER,CPDMA Receive IDVER"
|
|
group.long 0x34014++0xF
|
|
line.long 0x0 "CPDMA_TH_CONTROL_REG,CPDMA Receive Control Register"
|
|
bitfld.long 0x0 0. "TH_EN,CPDMA Receive DMA Enable" "0,1"
|
|
line.long 0x4 "CPDMA_TH_TEARDOWN_REG,CPDMA Receive Teardown Register"
|
|
bitfld.long 0x4 31. "TH_TDN_RDY,CPDMA Receive Teardown Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "TH_TDN_CH,CPDMA Receive Teardown Channel" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CPDMA_SOFT_RESET_REG,CPDMA Soft Reset Register"
|
|
bitfld.long 0x8 0. "SOFT_RESET,CPDMA and CPSW Soft Reset Enable" "0,1"
|
|
line.long 0xC "CPDMA_CONTROL_REG,CPDMA Control Register"
|
|
bitfld.long 0xC 6. "TH_TS_ENCAP,CPDMA Receive TimeStamp Encapsulated" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "TH_VLAN_ENCAP,CPDMA Receive VLAN Encapsulated" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "TH_CEF,CPDMA Receive Copy Error Frames" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CMD_IDLE,CPDMA Command Idle" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "TH_OFFLEN_BLOCK,CPDMA Receive Offset/Length Word Write Block" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TH_OWNERSHIP,CPDMA Receive Ownership Write Bit Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "FH_PTYPE,CPDMA Transmit Queue Priority Type" "0,1"
|
|
rgroup.long 0x34024++0x3
|
|
line.long 0x0 "CPDMA_STATUS_REG,CPDMA Status Register"
|
|
bitfld.long 0x0 31. "IDLE,CPDMA Transmit Host Error Code" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "FH_HOST_ERROR_CODE,CPDMA Transmit Host Error Code"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "FH_ERR_CH,CPDMA Transmit Error Channel Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "TH_HOST_ERROR_CODE,CPDMA Receive Host Error Code"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "TH_ERR_CH,CPDMA Receive Error Channel Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x34028++0x7
|
|
line.long 0x0 "CPDMA_TH_BUFFER_OFFSET_REG,CPDMA Receive Buffer Offset Register"
|
|
hexmask.long.word 0x0 0.--10. 1. "TH_BUFFER_OFFSET,CPDMA Receive Buffer Offset Register"
|
|
line.long 0x4 "CPDMA_EMULATION_CONTROL_REG,CPDMA Receive Buffer Offset Register"
|
|
bitfld.long 0x4 1. "FREE,CPDMA Receive Buffer Offset Register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SOFT,CPDMA Receive Buffer Offset Register" "0,1"
|
|
rgroup.long 0x34080++0x7
|
|
line.long 0x0 "CPDMA_FH_INTSTAT_RAW_REG,CPDMA FHost Interrupt Status RAW"
|
|
bitfld.long 0x0 7. "FH7_PEND_RAW,CPDMA FHost Channel 7 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FH6_PEND_RAW,CPDMA FHost Channel 6 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FH5_PEND_RAW,CPDMA FHost Channel 5 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FH4_PEND_RAW,CPDMA FHost Channel 4 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FH3_PEND_RAW,CPDMA FHost Channel 3 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FH2_PEND_RAW,CPDMA FHost Channel 2 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FH1_PEND_RAW,CPDMA FHost Channel 1 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FH0_PEND_RAW,CPDMA FHost Channel 0 Interrupt Pending RAW" "0,1"
|
|
line.long 0x4 "CPDMA_FH_INTSTAT_MASKED_REG,CPDMA FHost Interrupt Status MASKED"
|
|
bitfld.long 0x4 7. "FH7_PEND_MASKED,CPDMA FHost Channel 7 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FH6_PEND_MASKED,CPDMA FHost Channel 6 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FH5_PEND_MASKED,CPDMA FHost Channel 5 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FH4_PEND_MASKED,CPDMA FHost Channel 4 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FH3_PEND_MASKED,CPDMA FHost Channel 3 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FH2_PEND_MASKED,CPDMA FHost Channel 2 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FH1_PEND_MASKED,CPDMA FHost Channel 1 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FH0_PEND_MASKED,CPDMA FHost Channel 0 Interrupt Pending MASKED" "0,1"
|
|
group.long 0x34088++0x7
|
|
line.long 0x0 "CPDMA_FH_INTSTAT_MASKED_SET_REG,CPDMA FHost Interrupt Masked SET"
|
|
bitfld.long 0x0 7. "FH7_PEND_MASKED_SET,CPDMA FHost Channel 7 Interrupt Pending MASKED Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FH6_PEND_MASKED_SET,CPDMA FHost Channel 6 Interrupt Pending MASKED Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FH5_PEND_MASKED_SET,CPDMA FHost Channel 5 Interrupt Pending MASKED Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FH4_PEND_MASKED_SET,CPDMA FHost Channel 4 Interrupt Pending MASKED Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FH3_PEND_MASKED_SET,CPDMA FHost Channel 3 Interrupt Pending MASKED Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FH2_PEND_MASKED_SET,CPDMA FHost Channel 2 Interrupt Pending MASKED Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FH1_PEND_MASKED_SET,CPDMA FHost Channel 1 Interrupt Pending MASKED Set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FH0_PEND_MASKED_SET,CPDMA FHost Channel 0 Interrupt Pending MASKED Set" "0,1"
|
|
line.long 0x4 "CPDMA_FH_INTSTAT_MASKED_CLR_REG,CPDMA FHost Interrupt Masked CLR"
|
|
bitfld.long 0x4 7. "FH7_PEND_MASKED_CLR,CPDMA FHost Channel 7 Interrupt Pending MASKED Clr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FH6_PEND_MASKED_CLR,CPDMA FHost Channel 6 Interrupt Pending MASKED Clr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FH5_PEND_MASKED_CLR,CPDMA FHost Channel 5 Interrupt Pending MASKED Clr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FH4_PEND_MASKED_CLR,CPDMA FHost Channel 4 Interrupt Pending MASKED Clr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FH3_PEND_MASKED_CLR,CPDMA FHost Channel 3 Interrupt Pending MASKED Clr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FH2_PEND_MASKED_CLR,CPDMA FHost Channel 2 Interrupt Pending MASKED Clr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FH1_PEND_MASKED_CLR,CPDMA FHost Channel 1 Interrupt Pending MASKED Clr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FH0_PEND_MASKED_CLR,CPDMA FHost Channel 0 Interrupt Pending MASKED Clr" "0,1"
|
|
rgroup.long 0x34090++0x3
|
|
line.long 0x0 "CPDMA_IN_VECTOR_REG,CPDMA DMA IN Vector"
|
|
hexmask.long 0x0 0.--31. 1. "DMA_IN_VECTOR,CPDMA DMA IN Vector"
|
|
group.long 0x34094++0x3
|
|
line.long 0x0 "CPDMA_EOI_VECTOR_REG,CPDMA DMA EOI Vector"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DMA_EOI_VECTOR,CPDMA DMA EOI Vector"
|
|
rgroup.long 0x340A0++0x7
|
|
line.long 0x0 "CPDMA_TH_INTSTAT_RAW_REG,CPDMA Receive Interrupt Status RAW"
|
|
bitfld.long 0x0 15. "TH7_THRESH_PEND_RAW,CPDMA Receive Channel 7 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TH6_THRESH_PEND_RAW,CPDMA Receive Channel 6 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TH5_THRESH_PEND_RAW,CPDMA Receive Channel 5 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TH4_THRESH_PEND_RAW,CPDMA Receive Channel 4 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TH3_THRESH_PEND_RAW,CPDMA Receive Channel 3 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TH2_THRESH_PEND_RAW,CPDMA Receive Channel 2 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TH1_THRESH_PEND_RAW,CPDMA Receive Channel 1 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TH0_THRESH_PEND_RAW,CPDMA Receive Channel 0 Threshold Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TH7_PEND_RAW,CPDMA Receive Channel 7 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TH6_PEND_RAW,CPDMA Receive Channel 6 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TH5_PEND_RAW,CPDMA Receive Channel 5 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TH4_PEND_RAW,CPDMA Receive Channel 4 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TH3_PEND_RAW,CPDMA Receive Channel 3 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TH2_PEND_RAW,CPDMA Receive Channel 2 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TH1_PEND_RAW,CPDMA Receive Channel 1 Interrupt Pending RAW" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TH0_PEND_RAW,CPDMA Receive Channel 0 Interrupt Pending RAW" "0,1"
|
|
line.long 0x4 "CPDMA_TH_INTSTAT_MASKED_REG,CPDMA Receive Interrupt Status MASKED"
|
|
bitfld.long 0x4 15. "TH7_THRESH_PEND_MASKED,CPDMA Receive Channel 7 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "TH6_THRESH_PEND_MASKED,CPDMA Receive Channel 6 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TH5_THRESH_PEND_MASKED,CPDMA Receive Channel 5 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TH4_THRESH_PEND_MASKED,CPDMA Receive Channel 4 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TH3_THRESH_PEND_MASKED,CPDMA Receive Channel 3 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TH2_THRESH_PEND_MASKED,CPDMA Receive Channel 2 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TH1_THRESH_PEND_MASKED,CPDMA Receive Channel 1 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TH0_THRESH_PEND_MASKED,CPDMA Receive Channel 0 Threshold Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TH7_PEND_MASKED,CPDMA Receive Channel 7 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TH6_PEND_MASKED,CPDMA Receive Channel 6 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TH5_PEND_MASKED,CPDMA Receive Channel 5 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TH4_PEND_MASKED,CPDMA Receive Channel 4 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TH3_PEND_MASKED,CPDMA Receive Channel 3 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TH2_PEND_MASKED,CPDMA Receive Channel 2 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TH1_PEND_MASKED,CPDMA Receive Channel 1 Interrupt Pending MASKED" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TH0_PEND_MASKED,CPDMA Receive Channel 0 Interrupt Pending MASKED" "0,1"
|
|
group.long 0x340A8++0x7
|
|
line.long 0x0 "CPDMA_TH_INTSTAT_SET_REG,CPDMA THost Interrupt Masked SET"
|
|
bitfld.long 0x0 15. "TH7_THRESH_PEND_MASKED_SET,CPDMA THost Channel 7 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TH6_THRESH_PEND_MASKED_SET,CPDMA THost Channel 6 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TH5_THRESH_PEND_MASKED_SET,CPDMA THost Channel 5 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TH4_THRESH_PEND_MASKED_SET,CPDMA THost Channel 4 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TH3_THRESH_PEND_MASKED_SET,CPDMA THost Channel 3 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TH2_THRESH_PEND_MASKED_SET,CPDMA THost Channel 2 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TH1_THRESH_PEND_MASKED_SET,CPDMA THost Channel 1 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TH0_THRESH_PEND_MASKED_SET,CPDMA THost Channel 0 Threshold Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TH7_PEND_MASKED_SET,CPDMA THost Channel 7 Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TH6_PEND_MASKED_SET,CPDMA THost Channel 6 Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TH5_PEND_MASKED_SET,CPDMA THost Channel 5 Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TH4_PEND_MASKED_SET,CPDMA THost Channel 4 Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TH3_PEND_MASKED_SET,CPDMA THost Channel 3 Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TH2_PEND_MASKED_SET,CPDMA THost Channel 2 Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TH1_PEND_MASKED_SET,CPDMA THost Channel 1 Interrupt Pending SET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TH0_PEND_MASKED_SET,CPDMA THost Channel 0 Interrupt Pending SET" "0,1"
|
|
line.long 0x4 "CPDMA_TH_INTSTAT_CLR_REG,CPDMA THost Interrupt Masked CLR"
|
|
bitfld.long 0x4 15. "TH7_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 7 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "TH6_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 6 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TH5_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 5 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TH4_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 4 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TH3_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 3 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TH2_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 2 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TH1_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 1 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TH0_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 0 Threshold Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TH7_PEND_MASKED_CLR,CPDMA THost Channel 7 Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TH6_PEND_MASKED_CLR,CPDMA THost Channel 6 Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TH5_PEND_MASKED_CLR,CPDMA THost Channel 5 Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TH4_PEND_MASKED_CLR,CPDMA THost Channel 4 Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TH3_PEND_MASKED_CLR,CPDMA THost Channel 3 Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TH2_PEND_MASKED_CLR,CPDMA THost Channel 2 Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TH1_PEND_MASKED_CLR,CPDMA THost Channel 1 Interrupt Pending CLR" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TH0_PEND_MASKED_CLR,CPDMA THost Channel 0 Interrupt Pending CLR" "0,1"
|
|
rgroup.long 0x340B0++0x7
|
|
line.long 0x0 "CPDMA_INTSTAT_RAW_REG,CPDMA DMA Interrupt Status RAW"
|
|
bitfld.long 0x0 1. "HOST_PEND_RAW,CPDMA HOST Interrupt Pending RAW" "0,1"
|
|
line.long 0x4 "CPDMA_INTSTAT_MASKED_REG,CPDMA DMA Interrupt Status MASKED"
|
|
bitfld.long 0x4 1. "HOST_PEND,CPDMA HOST Interrupt Pending MASKED" "0,1"
|
|
group.long 0x340B8++0x47
|
|
line.long 0x0 "CPDMA_INTSTAT_SET_REG,CPDMA DMA Interrupt Status SET"
|
|
bitfld.long 0x0 1. "HOST_PEND_MASKED_SET,CPDMA HOST Interrupt Masked SET" "0,1"
|
|
line.long 0x4 "CPDMA_INTSTAT_CLR_REG,CPDMA DMA Interrupt Status CLR"
|
|
bitfld.long 0x4 1. "HOST_PEND_MASKED_CLR,CPDMA HOST Interrupt Masked CLR" "0,1"
|
|
line.long 0x8 "CPDMA_TH0_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TH0_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0xC "CPDMA_TH1_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TH1_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0x10 "CPDMA_TH2_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "TH2_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0x14 "CPDMA_TH3_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "TH3_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0x18 "CPDMA_TH4_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TH4_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0x1C "CPDMA_TH5_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "TH5_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0x20 "CPDMA_TH6_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. "TH6_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0x24 "CPDMA_TH7_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
|
|
hexmask.long.byte 0x24 0.--7. 1. "TH7_PENDTHRESH,CPDMA THost Threshold Pending Register"
|
|
line.long 0x28 "CPDMA_TH0_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x28 0.--14. 1. "TH0_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
line.long 0x2C "CPDMA_TH1_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x2C 0.--14. 1. "TH1_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
line.long 0x30 "CPDMA_TH2_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x30 0.--14. 1. "TH2_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
line.long 0x34 "CPDMA_TH3_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x34 0.--14. 1. "TH3_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
line.long 0x38 "CPDMA_TH4_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x38 0.--14. 1. "TH4_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
line.long 0x3C "CPDMA_TH5_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x3C 0.--14. 1. "TH5_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
line.long 0x40 "CPDMA_TH6_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x40 0.--14. 1. "TH6_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
line.long 0x44 "CPDMA_TH7_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
|
|
hexmask.long.word 0x44 0.--14. 1. "TH7_FREEBUFFER,CPDMA THost Free Buffer Count Register"
|
|
group.long 0x34200++0x7F
|
|
line.long 0x0 "CPDMA_FH0_HDP_REG,CPDMA FHost Channel 0 Head Descriptor Pointer"
|
|
hexmask.long 0x0 0.--31. 1. "FH0_HDP,CPDMA FHost Channel 0 Head Descriptor Pointer"
|
|
line.long 0x4 "CPDMA_FH1_HDP_REG,CPDMA FHost Channel 1 Head Descriptor Pointer"
|
|
hexmask.long 0x4 0.--31. 1. "FH1_HDP,CPDMA FHost Channel 1 Head Descriptor Pointer"
|
|
line.long 0x8 "CPDMA_FH2_HDP_REG,CPDMA FHost Channel 2 Head Descriptor Pointer"
|
|
hexmask.long 0x8 0.--31. 1. "FH2_HDP,CPDMA FHost Channel 2 Head Descriptor Pointer"
|
|
line.long 0xC "CPDMA_FH3_HDP_REG,CPDMA FHost Channel 3 Head Descriptor Pointer"
|
|
hexmask.long 0xC 0.--31. 1. "FH3_HDP,CPDMA FHost Channel 3 Head Descriptor Pointer"
|
|
line.long 0x10 "CPDMA_FH4_HDP_REG,CPDMA FHost Channel 4 Head Descriptor Pointer"
|
|
hexmask.long 0x10 0.--31. 1. "FH4_HDP,CPDMA FHost Channel 4 Head Descriptor Pointer"
|
|
line.long 0x14 "CPDMA_FH5_HDP_REG,CPDMA FHost Channel 5 Head Descriptor Pointer"
|
|
hexmask.long 0x14 0.--31. 1. "FH5_HDP,CPDMA FHost Channel 5 Head Descriptor Pointer"
|
|
line.long 0x18 "CPDMA_FH6_HDP_REG,CPDMA FHost Channel 6 Head Descriptor Pointer"
|
|
hexmask.long 0x18 0.--31. 1. "FH6_HDP,CPDMA FHost Channel 6 Head Descriptor Pointer"
|
|
line.long 0x1C "CPDMA_FH7_HDP_REG,CPDMA FHost Channel 7 Head Descriptor Pointer"
|
|
hexmask.long 0x1C 0.--31. 1. "FH7_HDP,CPDMA FHost Channel 7 Head Descriptor Pointer"
|
|
line.long 0x20 "CPDMA_TH0_HDP_REG,CPDMA THost Channel 0 Head Descriptor Pointer"
|
|
hexmask.long 0x20 0.--31. 1. "TH0_HDP,CPDMA THost Channel 0 Head Descriptor Pointer"
|
|
line.long 0x24 "CPDMA_TH1_HDP_REG,CPDMA THost Channel 1 Head Descriptor Pointer"
|
|
hexmask.long 0x24 0.--31. 1. "TH1_HDP,CPDMA THost Channel 1 Head Descriptor Pointer"
|
|
line.long 0x28 "CPDMA_TH2_HDP_REG,CPDMA THost Channel 2 Head Descriptor Pointer"
|
|
hexmask.long 0x28 0.--31. 1. "TH2_HDP,CPDMA THost Channel 2 Head Descriptor Pointer"
|
|
line.long 0x2C "CPDMA_TH3_HDP_REG,CPDMA THost Channel 3 Head Descriptor Pointer"
|
|
hexmask.long 0x2C 0.--31. 1. "TH3_HDP,CPDMA THost Channel 3 Head Descriptor Pointer"
|
|
line.long 0x30 "CPDMA_TH4_HDP_REG,CPDMA THost Channel 4 Head Descriptor Pointer"
|
|
hexmask.long 0x30 0.--31. 1. "TH4_HDP,CPDMA THost Channel 4 Head Descriptor Pointer"
|
|
line.long 0x34 "CPDMA_TH5_HDP_REG,CPDMA THost Channel 5 Head Descriptor Pointer"
|
|
hexmask.long 0x34 0.--31. 1. "TH5_HDP,CPDMA THost Channel 5 Head Descriptor Pointer"
|
|
line.long 0x38 "CPDMA_TH6_HDP_REG,CPDMA THost Channel 6 Head Descriptor Pointer"
|
|
hexmask.long 0x38 0.--31. 1. "TH6_HDP,CPDMA THost Channel 6 Head Descriptor Pointer"
|
|
line.long 0x3C "CPDMA_TH7_HDP_REG,CPDMA THost Channel 7 Head Descriptor Pointer"
|
|
hexmask.long 0x3C 0.--31. 1. "TH7_HDP,CPDMA THost Channel 7 Head Descriptor Pointer"
|
|
line.long 0x40 "CPDMA_FH0_CP_REG,CPDMA FHost Channel 0 Completion Pointer"
|
|
hexmask.long 0x40 0.--31. 1. "FH0_CP,CPDMA FHost Channel 0 Completion Pointer"
|
|
line.long 0x44 "CPDMA_FH1_CP_REG,CPDMA FHost Channel 1 Completion Pointer"
|
|
hexmask.long 0x44 0.--31. 1. "FH1_CP,CPDMA FHost Channel 1 Completion Pointer"
|
|
line.long 0x48 "CPDMA_FH2_CP_REG,CPDMA FHost Channel 2 Completion Pointer"
|
|
hexmask.long 0x48 0.--31. 1. "FH2_CP,CPDMA FHost Channel 2 Completion Pointer"
|
|
line.long 0x4C "CPDMA_FH3_CP_REG,CPDMA FHost Channel 3 Completion Pointer"
|
|
hexmask.long 0x4C 0.--31. 1. "FH3_CP,CPDMA FHost Channel 3 Completion Pointer"
|
|
line.long 0x50 "CPDMA_FH4_CP_REG,CPDMA FHost Channel 4 Completion Pointer"
|
|
hexmask.long 0x50 0.--31. 1. "FH4_CP,CPDMA FHost Channel 4 Completion Pointer"
|
|
line.long 0x54 "CPDMA_FH5_CP_REG,CPDMA FHost Channel 5 Completion Pointer"
|
|
hexmask.long 0x54 0.--31. 1. "FH5_CP,CPDMA FHost Channel 5 Completion Pointer"
|
|
line.long 0x58 "CPDMA_FH6_CP_REG,CPDMA FHost Channel 6 Completion Pointer"
|
|
hexmask.long 0x58 0.--31. 1. "FH6_CP,CPDMA FHost Channel 6 Completion Pointer"
|
|
line.long 0x5C "CPDMA_FH7_CP_REG,CPDMA FHost Channel 7 Completion Pointer"
|
|
hexmask.long 0x5C 0.--31. 1. "FH7_CP,CPDMA FHost Channel 7 Completion Pointer"
|
|
line.long 0x60 "CPDMA_TH0_CP_REG,CPDMA THost Channel 0 Completion Pointer"
|
|
hexmask.long 0x60 0.--31. 1. "TH0_CP,CPDMA THost Channel 0 Completion Pointer"
|
|
line.long 0x64 "CPDMA_TH1_CP_REG,CPDMA THost Channel 1 Completion Pointer"
|
|
hexmask.long 0x64 0.--31. 1. "TH1_CP,CPDMA THost Channel 1 Completion Pointer"
|
|
line.long 0x68 "CPDMA_TH2_CP_REG,CPDMA THost Channel 2 Completion Pointer"
|
|
hexmask.long 0x68 0.--31. 1. "TH2_CP,CPDMA THost Channel 2 Completion Pointer"
|
|
line.long 0x6C "CPDMA_TH3_CP_REG,CPDMA THost Channel 3 Completion Pointer"
|
|
hexmask.long 0x6C 0.--31. 1. "TH3_CP,CPDMA THost Channel 3 Completion Pointer"
|
|
line.long 0x70 "CPDMA_TH4_CP_REG,CPDMA THost Channel 4 Completion Pointer"
|
|
hexmask.long 0x70 0.--31. 1. "TH4_CP,CPDMA THost Channel 4 Completion Pointer"
|
|
line.long 0x74 "CPDMA_TH5_CP_REG,CPDMA THost Channel 5 Completion Pointer"
|
|
hexmask.long 0x74 0.--31. 1. "TH5_CP,CPDMA THost Channel 5 Completion Pointer"
|
|
line.long 0x78 "CPDMA_TH6_CP_REG,CPDMA THost Channel 6 Completion Pointer"
|
|
hexmask.long 0x78 0.--31. 1. "TH6_CP,CPDMA THost Channel 6 Completion Pointer"
|
|
line.long 0x7C "CPDMA_TH7_CP_REG,CPDMA THost Channel 7 Completion Pointer"
|
|
hexmask.long 0x7C 0.--31. 1. "TH7_CP,CPDMA THost Channel 7 Completion Pointer"
|
|
group.long 0x34300++0x7F
|
|
line.long 0x0 "TEST_CPDMA_FH0_HDP_REG,Test CPDMA FHost Channel 0 Head Descriptor Pointer"
|
|
hexmask.long 0x0 0.--31. 1. "TEST_FH0_HDP,Test CPDMA FHost Channel 0 Head Descriptor Pointer"
|
|
line.long 0x4 "TEST_CPDMA_FH1_HDP_REG,Test CPDMA FHost Channel 1 Head Descriptor Pointer"
|
|
hexmask.long 0x4 0.--31. 1. "TEST_FH1_HDP,Test CPDMA FHost Channel 1 Head Descriptor Pointer"
|
|
line.long 0x8 "TEST_CPDMA_FH2_HDP_REG,Test CPDMA FHost Channel 2 Head Descriptor Pointer"
|
|
hexmask.long 0x8 0.--31. 1. "TEST_FH2_HDP,Test CPDMA FHost Channel 2 Head Descriptor Pointer"
|
|
line.long 0xC "TEST_CPDMA_FH3_HDP_REG,Test CPDMA FHost Channel 3 Head Descriptor Pointer"
|
|
hexmask.long 0xC 0.--31. 1. "TEST_FH3_HDP,Test CPDMA FHost Channel 3 Head Descriptor Pointer"
|
|
line.long 0x10 "TEST_CPDMA_FH4_HDP_REG,Test CPDMA FHost Channel 4 Head Descriptor Pointer"
|
|
hexmask.long 0x10 0.--31. 1. "TEST_FH4_HDP,Test CPDMA FHost Channel 4 Head Descriptor Pointer"
|
|
line.long 0x14 "TEST_CPDMA_FH5_HDP_REG,Test CPDMA FHost Channel 5 Head Descriptor Pointer"
|
|
hexmask.long 0x14 0.--31. 1. "TEST_FH5_HDP,Test CPDMA FHost Channel 5 Head Descriptor Pointer"
|
|
line.long 0x18 "TEST_CPDMA_FH6_HDP_REG,Test CPDMA FHost Channel 6 Head Descriptor Pointer"
|
|
hexmask.long 0x18 0.--31. 1. "TEST_FH6_HDP,Test CPDMA FHost Channel 6 Head Descriptor Pointer"
|
|
line.long 0x1C "TEST_CPDMA_FH7_HDP_REG,Test CPDMA FHost Channel 7 Head Descriptor Pointer"
|
|
hexmask.long 0x1C 0.--31. 1. "TEST_FH7_HDP,Test CPDMA FHost Channel 7 Head Descriptor Pointer"
|
|
line.long 0x20 "TEST_CPDMA_TH0_HDP_REG,Test CPDMA THost Channel 0 Head Descriptor Pointer"
|
|
hexmask.long 0x20 0.--31. 1. "TEST_TH0_HDP,Test CPDMA THost Channel 0 Head Descriptor Pointer"
|
|
line.long 0x24 "TEST_CPDMA_TH1_HDP_REG,Test CPDMA THost Channel 1 Head Descriptor Pointer"
|
|
hexmask.long 0x24 0.--31. 1. "TEST_TH1_HDP,Test CPDMA THost Channel 1 Head Descriptor Pointer"
|
|
line.long 0x28 "TEST_CPDMA_TH2_HDP_REG,Test CPDMA THost Channel 2 Head Descriptor Pointer"
|
|
hexmask.long 0x28 0.--31. 1. "TEST_TH2_HDP,Test CPDMA THost Channel 2 Head Descriptor Pointer"
|
|
line.long 0x2C "TEST_CPDMA_TH3_HDP_REG,Test CPDMA THost Channel 3 Head Descriptor Pointer"
|
|
hexmask.long 0x2C 0.--31. 1. "TEST_TH3_HDP,Test CPDMA THost Channel 3 Head Descriptor Pointer"
|
|
line.long 0x30 "TEST_CPDMA_TH4_HDP_REG,Test CPDMA THost Channel 4 Head Descriptor Pointer"
|
|
hexmask.long 0x30 0.--31. 1. "TEST_TH4_HDP,Test CPDMA THost Channel 4 Head Descriptor Pointer"
|
|
line.long 0x34 "TEST_CPDMA_TH5_HDP_REG,Test CPDMA THost Channel 5 Head Descriptor Pointer"
|
|
hexmask.long 0x34 0.--31. 1. "TEST_TH5_HDP,Test CPDMA THost Channel 5 Head Descriptor Pointer"
|
|
line.long 0x38 "TEST_CPDMA_TH6_HDP_REG,Test CPDMA THost Channel 6 Head Descriptor Pointer"
|
|
hexmask.long 0x38 0.--31. 1. "TEST_TH6_HDP,Test CPDMA THost Channel 6 Head Descriptor Pointer"
|
|
line.long 0x3C "TEST_CPDMA_TH7_HDP_REG,Test CPDMA THost Channel 7 Head Descriptor Pointer"
|
|
hexmask.long 0x3C 0.--31. 1. "TEST_TH7_HDP,Test CPDMA THost Channel 7 Head Descriptor Pointer"
|
|
line.long 0x40 "TEST_CPDMA_FH0_CP_REG,Test CPDMA FHost Channel 0 Completion Pointer"
|
|
hexmask.long 0x40 0.--31. 1. "TEST_FH0_CP,Test CPDMA FHost Channel 0 Completion Pointer"
|
|
line.long 0x44 "TEST_CPDMA_FH1_CP_REG,Test CPDMA FHost Channel 1 Completion Pointer"
|
|
hexmask.long 0x44 0.--31. 1. "TEST_FH1_CP,Test CPDMA FHost Channel 1 Completion Pointer"
|
|
line.long 0x48 "TEST_CPDMA_FH2_CP_REG,Test CPDMA FHost Channel 2 Completion Pointer"
|
|
hexmask.long 0x48 0.--31. 1. "TEST_FH2_CP,Test CPDMA FHost Channel 2 Completion Pointer"
|
|
line.long 0x4C "TEST_CPDMA_FH3_CP_REG,Test CPDMA FHost Channel 3 Completion Pointer"
|
|
hexmask.long 0x4C 0.--31. 1. "TEST_FH3_CP,Test CPDMA FHost Channel 3 Completion Pointer"
|
|
line.long 0x50 "TEST_CPDMA_FH4_CP_REG,Test CPDMA FHost Channel 4 Completion Pointer"
|
|
hexmask.long 0x50 0.--31. 1. "TEST_FH4_CP,Test CPDMA FHost Channel 4 Completion Pointer"
|
|
line.long 0x54 "TEST_CPDMA_FH5_CP_REG,Test CPDMA FHost Channel 5 Completion Pointer"
|
|
hexmask.long 0x54 0.--31. 1. "TEST_FH5_CP,Test CPDMA FHost Channel 5 Completion Pointer"
|
|
line.long 0x58 "TEST_CPDMA_FH6_CP_REG,Test CPDMA FHost Channel 6 Completion Pointer"
|
|
hexmask.long 0x58 0.--31. 1. "TEST_FH6_CP,Test CPDMA FHost Channel 6 Completion Pointer"
|
|
line.long 0x5C "TEST_CPDMA_FH7_CP_REG,Test CPDMA FHost Channel 7 Completion Pointer"
|
|
hexmask.long 0x5C 0.--31. 1. "TEST_FH7_CP,Test CPDMA FHost Channel 7 Completion Pointer"
|
|
line.long 0x60 "TEST_CPDMA_TH0_CP_REG,Test CPDMA THost Channel 0 Completion Pointer"
|
|
hexmask.long 0x60 0.--31. 1. "TEST_TH0_CP,Test CPDMA THost Channel 0 Completion Pointer"
|
|
line.long 0x64 "TEST_CPDMA_TH1_CP_REG,Test CPDMA THost Channel 1 Completion Pointer"
|
|
hexmask.long 0x64 0.--31. 1. "TEST_TH1_CP,Test CPDMA THost Channel 1 Completion Pointer"
|
|
line.long 0x68 "TEST_CPDMA_TH2_CP_REG,Test CPDMA THost Channel 2 Completion Pointer"
|
|
hexmask.long 0x68 0.--31. 1. "TEST_TH2_CP,Test CPDMA THost Channel 2 Completion Pointer"
|
|
line.long 0x6C "TEST_CPDMA_TH3_CP_REG,Test CPDMA THost Channel 3 Completion Pointer"
|
|
hexmask.long 0x6C 0.--31. 1. "TEST_TH3_CP,Test CPDMA THost Channel 3 Completion Pointer"
|
|
line.long 0x70 "TEST_CPDMA_TH4_CP_REG,Test CPDMA THost Channel 4 Completion Pointer"
|
|
hexmask.long 0x70 0.--31. 1. "TEST_TH4_CP,Test CPDMA THost Channel 4 Completion Pointer"
|
|
line.long 0x74 "TEST_CPDMA_TH5_CP_REG,Test CPDMA THost Channel 5 Completion Pointer"
|
|
hexmask.long 0x74 0.--31. 1. "TEST_TH5_CP,Test CPDMA THost Channel 5 Completion Pointer"
|
|
line.long 0x78 "TEST_CPDMA_TH6_CP_REG,Test CPDMA THost Channel 6 Completion Pointer"
|
|
hexmask.long 0x78 0.--31. 1. "TEST_TH6_CP,Test CPDMA THost Channel 6 Completion Pointer"
|
|
line.long 0x7C "TEST_CPDMA_TH7_CP_REG,Test CPDMA THost Channel 7 Completion Pointer"
|
|
hexmask.long 0x7C 0.--31. 1. "TEST_TH7_CP,Test CPDMA THost Channel 7 Completion Pointer"
|
|
group.long 0x3A000++0xB
|
|
line.long 0x0 "RXGOODFRAMES,Total number of good frames received"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received"
|
|
line.long 0x4 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received"
|
|
line.long 0x8 "RXMULTICASTFRAMES,Total number of good multicast frames received"
|
|
hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received"
|
|
group.long 0x3A010++0x3
|
|
line.long 0x0 "RXCRCERRORS,Total number of CRC errors frames received"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of CRC errors frames received"
|
|
group.long 0x3A018++0x3
|
|
line.long 0x0 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of oversized frames received"
|
|
group.long 0x3A020++0x1F
|
|
line.long 0x0 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of undersized frames received"
|
|
line.long 0x4 "RXFRAGMENTS,Total number of fragmented frames received"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,Total number of fragmented frames received"
|
|
line.long 0x8 "ALE_DROP,Total number of frames dropped by the ALE"
|
|
hexmask.long 0x8 0.--31. 1. "COUNT,Total number of frames dropped by the ALE"
|
|
line.long 0xC "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
|
|
hexmask.long 0xC 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE"
|
|
line.long 0x10 "RXOCTETS,Total number of received bytes in good frames"
|
|
hexmask.long 0x10 0.--31. 1. "COUNT,Total number of received bytes in good frames"
|
|
line.long 0x14 "TXGOODFRAMES,Total number of good frames transmitted"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Total number of good frames transmitted"
|
|
line.long 0x18 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
|
|
hexmask.long 0x18 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted"
|
|
line.long 0x1C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
|
|
hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted"
|
|
group.long 0x3A04C++0x7
|
|
line.long 0x0 "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a single collision"
|
|
line.long 0x4 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,Total number of transmitted frames experiencing multiple collisions"
|
|
group.long 0x3A064++0x3
|
|
line.long 0x0 "TXOCTETS,Total number of bytes in all good frames transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted"
|
|
repeat 2. (list 0x40 0x40)(list 0x0 0x200)
|
|
group.long ($2+0x3A068)++0x3
|
|
line.long 0x0 "OCTETFRAMES$1,Total number of 64-byte frames received and transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of 64-byte frames received and transmitted"
|
|
repeat.end
|
|
repeat 2. (list 0x7F 0x7F)(list 0x0 0x200)
|
|
group.long ($2+0x3A06C)++0x3
|
|
line.long 0x0 "OCTETFRAMES65T$1,Total number of frames of size 65 to 127 bytes received and transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of frames of size 65 to 127 bytes received and transmitted"
|
|
repeat.end
|
|
repeat 2. (list 0xFF 0xFF)(list 0x0 0x200)
|
|
group.long ($2+0x3A070)++0x3
|
|
line.long 0x0 "OCTETFRAMES128T$1,Total number of frames of size 128 to 255 bytes received and transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of frames of size 128 to 255 bytes received and transmitted"
|
|
repeat.end
|
|
repeat 2. (list 0x1FF 0x1FF)(list 0x0 0x200)
|
|
group.long ($2+0x3A074)++0x3
|
|
line.long 0x0 "OCTETFRAMES256T$1,Total number of frames of size 256 to 511 bytes received and transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of frames of size 256 to 511 bytes received and transmitted"
|
|
repeat.end
|
|
repeat 2. (list 0x3FF 0x3FF)(list 0x0 0x200)
|
|
group.long ($2+0x3A078)++0x3
|
|
line.long 0x0 "OCTETFRAMES512T$1,Total number of frames of size 512 to 1023 bytes received and transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of frames of size 512 to 1023 bytes received and transmitted"
|
|
repeat.end
|
|
group.long 0x3A07C++0x3
|
|
line.long 0x0 "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A080)++0x3
|
|
line.long 0x0 "NETOCTETS_$1,Total number of bytes received and transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of bytes received and transmitted"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A084)++0x3
|
|
line.long 0x0 "RX_BOTTOM_OF_FIFO_DROP_$1,Receive Bottom of FIFO Drop"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Receive Bottom of FIFO Drop"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A088)++0x3
|
|
line.long 0x0 "PORTMASK_DROP_$1,Total number of dropped frames received due to portmask"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of dropped frames received due to portmask"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A08C)++0x3
|
|
line.long 0x0 "RX_TOP_OF_FIFO_DROP_$1,Receive Top of FIFO Drop"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Receive Top of FIFO Drop"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A090)++0x3
|
|
line.long 0x0 "ALE_RATE_LIMIT_DROP_$1,Total number of dropped frames due to ALE Rate Limiting"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Rate Limiting"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A094)++0x3
|
|
line.long 0x0 "ALE_VID_INGRESS_DROP_$1,Total number of dropped frames due to ALE VID Ingress"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE VID Ingress"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A098)++0x3
|
|
line.long 0x0 "ALE_DA_EQ_SA_DROP_$1,Total number of dropped frames due to DA=SA"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of dropped frames due to DA=SA"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A09C)++0x3
|
|
line.long 0x0 "ALE_BLOCK_DROP_$1,Total number of dropped frames due to ALE Block Mode"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Block Mode"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0A0)++0x3
|
|
line.long 0x0 "ALE_SECURE_DROP_$1,Total number of dropped frames due to ALE Secure Mode"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Secure Mode"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0A4)++0x3
|
|
line.long 0x0 "ALE_AUTH_DROP_$1,Total number of dropped frames due to ALE Authentication"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of dropped frames due to ALE Authentication"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0A8)++0x3
|
|
line.long 0x0 "ALE_UNKN_UNI_$1,ALE Receive Unknown Unicast"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Receive Unknown Unicast"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0AC)++0x3
|
|
line.long 0x0 "ALE_UNKN_UNI_BCNT_$1,ALE Receive Unknown Unicast Bytecount"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Receive Unknown Unicast Bytecount"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0B0)++0x3
|
|
line.long 0x0 "ALE_UNKN_MLT_$1,ALE Receive Unknown Multicast"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Receive Unknown Multicast"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0B4)++0x3
|
|
line.long 0x0 "ALE_UNKN_MLT_BCNT_$1,ALE Receive Unknown Multicast Bytecount"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Receive Unknown Multicast Bytecount"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0B8)++0x3
|
|
line.long 0x0 "ALE_UNKN_BRD_$1,ALE Receive Unknown Broadcast"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0BC)++0x3
|
|
line.long 0x0 "ALE_UNKN_BRD_BCNT_$1,ALE Receive Unknown Broadcast Bytecount"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Receive Unknown Broadcast Bytecount"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0C0)++0x3
|
|
line.long 0x0 "ALE_POL_MATCH_$1,ALE Policer Matched"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Policer Matched"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0C4)++0x3
|
|
line.long 0x0 "ALE_POL_MATCH_RED_$1,ALE Policer Matched and Condition Red"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Policer Matched and Condition Red"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0C8)++0x3
|
|
line.long 0x0 "ALE_POL_MATCH_YELLOW_$1,ALE Policer Matched and Condition Yellow"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Policer Matched and Condition Yellow"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0CC)++0x3
|
|
line.long 0x0 "ALE_MULT_SA_DROP_$1,ALE Multicast Source Address Drop"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Multicast Source Address drop"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x1)(list 0x0 0x200)
|
|
group.long ($2+0x3A0D0)++0x3
|
|
line.long 0x0 "ALE_DUAL_VLAN_DROP_$1,ALE Dual VLAN Drop"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Dual VLAN drop"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0D4)++0x3
|
|
line.long 0x0 "ALE_LEN_ERROR_DROP_$1,ALE Length Error Drop"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Length Error drop"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0D8)++0x3
|
|
line.long 0x0 "ALE_IP_NEXT_HDR_DROP_$1,ALE IP Next Header Drop"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE Next Header drop"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A0DC)++0x3
|
|
line.long 0x0 "ALE_IPV4_FRAG_DROP_$1,ALE IPV4 Frag Drop"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,ALE IPV4 Fragment drop"
|
|
repeat.end
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x200)
|
|
group.long ($2+0x3A17C)++0x3
|
|
line.long 0x0 "TX_MEMORY_PROTECT_ERROR_$1,Transmit Memory Protect CRC Error"
|
|
hexmask.long.byte 0x0 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
|
|
repeat.end
|
|
group.long 0x3A200++0x67
|
|
line.long 0x0 "RXGOODFRAMES,Total number of good frames received"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of good frames received"
|
|
line.long 0x4 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT,Total number of good broadcast frames received"
|
|
line.long 0x8 "RXMULTICASTFRAMES,Total number of good multicast frames received"
|
|
hexmask.long 0x8 0.--31. 1. "COUNT,Total number of good multicast frames received"
|
|
line.long 0xC "RXPAUSEFRAMES,Total number of pause frames received"
|
|
hexmask.long 0xC 0.--31. 1. "COUNT,Total number of pause frames received"
|
|
line.long 0x10 "RXCRCERRORS,Total number of CRC errors frames received"
|
|
hexmask.long 0x10 0.--31. 1. "COUNT,Total number of CRC errors frames received"
|
|
line.long 0x14 "RXALIGNCODEERRORS,Total number of alignment/code errors received"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Total number of alignment/code errors received"
|
|
line.long 0x18 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
|
|
hexmask.long 0x18 0.--31. 1. "COUNT,Total number of oversized frames received"
|
|
line.long 0x1C "RXJABBERFRAMES,Total number of jabber frames received"
|
|
hexmask.long 0x1C 0.--31. 1. "COUNT,Total number of jabber frames received"
|
|
line.long 0x20 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
|
|
hexmask.long 0x20 0.--31. 1. "COUNT,Total number of undersized frames received"
|
|
line.long 0x24 "RXFRAGMENTS,Total number of fragmented frames received"
|
|
hexmask.long 0x24 0.--31. 1. "COUNT,Total number of fragmented frames received"
|
|
line.long 0x28 "ALE_DROP,Total number of frames dropped by the ALE"
|
|
hexmask.long 0x28 0.--31. 1. "COUNT,Total number of frames dropped by the ALE"
|
|
line.long 0x2C "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
|
|
hexmask.long 0x2C 0.--31. 1. "COUNT,Total number of overrun frames dropped by the ALE"
|
|
line.long 0x30 "RXOCTETS,Total number of received bytes in good frames"
|
|
hexmask.long 0x30 0.--31. 1. "COUNT,Total number of received bytes in good frames"
|
|
line.long 0x34 "TXGOODFRAMES,Total number of good frames transmitted"
|
|
hexmask.long 0x34 0.--31. 1. "COUNT,Total number of good frames transmitted"
|
|
line.long 0x38 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
|
|
hexmask.long 0x38 0.--31. 1. "COUNT,Total number of good broadcast frames transmitted"
|
|
line.long 0x3C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
|
|
hexmask.long 0x3C 0.--31. 1. "COUNT,Total number of good multicast frames transmitted"
|
|
line.long 0x40 "TXPAUSEFRAMES,Total number of pause frames transmitted"
|
|
hexmask.long 0x40 0.--31. 1. "COUNT,Total number of pause frames transmitted"
|
|
line.long 0x44 "TXDEFERREDFRAMES,Total number of deferred frames transmitted"
|
|
hexmask.long 0x44 0.--31. 1. "COUNT,Total number of deferred frames transmitted"
|
|
line.long 0x48 "TXCOLLISIONFRAMES,Total number of transmitted frames experiencing a collision"
|
|
hexmask.long 0x48 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a collision"
|
|
line.long 0x4C "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
|
|
hexmask.long 0x4C 0.--31. 1. "COUNT,Total number of transmitted frames experiencing a single collision"
|
|
line.long 0x50 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
|
|
hexmask.long 0x50 0.--31. 1. "COUNT,Total number of transmitted frames experiencing multiple collisions"
|
|
line.long 0x54 "TXEXCESSIVECOLLISIONS,Total number of transmitted frames abandoned due to excessive collisions"
|
|
hexmask.long 0x54 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to excessive collisions"
|
|
line.long 0x58 "TXLATECOLLISIONS,Total number of transmitted frames abandoned due to a late collision"
|
|
hexmask.long 0x58 0.--31. 1. "COUNT,Total number of transmitted frames abandoned due to a late collision"
|
|
line.long 0x5C "RXIPGERROR,Total number of receive inter-packet gap errors (10G only)"
|
|
hexmask.long 0x5C 0.--31. 1. "COUNT,Total number of receive inter-packet gap errors (10G only)"
|
|
line.long 0x60 "TXCARRIERSENSEERRORS,Total number of transmitted frames that experienced a carrier loss"
|
|
hexmask.long 0x60 0.--31. 1. "COUNT,Total number of transmitted frames that experienced a carrier loss"
|
|
line.long 0x64 "TXOCTETS,Total number of bytes in all good frames transmitted"
|
|
hexmask.long 0x64 0.--31. 1. "COUNT,Total number of bytes in all good frames transmitted"
|
|
group.long 0x3A27C++0x3
|
|
line.long 0x0 "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x3A380)++0x3
|
|
line.long 0x0 "ENET_PN_TX_PRI_REG_$1,ENET Port n PRIORITY N Packet Count"
|
|
hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN,ENET TX Priority Packet Count"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x3A3A0)++0x3
|
|
line.long 0x0 "ENET_PN_TX_PRI_BCNT_REG_$1,ENET Port n PRIORITY N Packet Byte Count"
|
|
hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_BCNT,ENET Port n PRIORITY N Packet Byte Count"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x3A3C0)++0x3
|
|
line.long 0x0 "ENET_PN_TX_PRI_DROP_REG_$1,ENET Port n PRIORITY N Packet Drop Count"
|
|
hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP,ENET Port n PRIORITY N Packet Drop Count"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x3A3E0)++0x3
|
|
line.long 0x0 "ENET_PN_TX_PRI_DROP_BCNT_REG_$1,ENET Port n PRIORITY N Packet Drop Byte Count"
|
|
hexmask.long 0x0 0.--31. 1. "PN_TX_PRIN_DROP_BC,ENET Port n PRIORITY N Packet Drop Byte Count"
|
|
repeat.end
|
|
rgroup.long 0x3D000++0x3
|
|
line.long 0x0 "IDVER_REG,Identification and Version Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TX_IDENT,Identification value"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value"
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group.long 0x3D004++0x7
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line.long 0x0 "CPTS_CONTROL_REG,Time Sync Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select"
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bitfld.long 0x0 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1"
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bitfld.long 0x0 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
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bitfld.long 0x0 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
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bitfld.long 0x0 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
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bitfld.long 0x0 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
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bitfld.long 0x0 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
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bitfld.long 0x0 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
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bitfld.long 0x0 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
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bitfld.long 0x0 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
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bitfld.long 0x0 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
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bitfld.long 0x0 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
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bitfld.long 0x0 6. "TS_COMP_TOG,Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode" "0: TS_COMP is in non-toggle mode,1: TS_COMP is in toggle mode"
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bitfld.long 0x0 5. "MODE,Timestamp mode" "0,1"
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bitfld.long 0x0 4. "SEQUENCE_EN,Sequence Enable" "0,1"
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bitfld.long 0x0 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
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bitfld.long 0x0 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
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bitfld.long 0x0 1. "INT_TEST,Interrupt test" "0,1"
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bitfld.long 0x0 0. "CPTS_EN,Time sync enable" "0,1"
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line.long 0x4 "RFTCLK_SEL_REG,RFTCLK Select Register"
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hexmask.long.byte 0x4 0.--4. 1. "RFTCLK_SEL,Reference clock select"
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wgroup.long 0x3D00C++0x3
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line.long 0x0 "TS_PUSH_REG,Time Stamp Event Push Register"
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bitfld.long 0x0 0. "TS_PUSH,Time stamp event push" "0,1"
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group.long 0x3D010++0x3
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line.long 0x0 "TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
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hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load low value"
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wgroup.long 0x3D014++0x3
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line.long 0x0 "TS_LOAD_EN_REG,Time Stamp Load Enable Register"
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bitfld.long 0x0 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
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group.long 0x3D018++0xB
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line.long 0x0 "TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
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hexmask.long 0x0 0.--31. 1. "TS_COMP_VAL,Time stamp comparison low value"
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line.long 0x4 "TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
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hexmask.long 0x4 0.--31. 1. "TS_COMP_LENGTH,Time stamp comparison length"
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line.long 0x8 "INTSTAT_RAW_REG,Interrupt Status Register Raw"
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bitfld.long 0x8 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
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rgroup.long 0x3D024++0x3
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line.long 0x0 "INTSTAT_MASKED_REG,Interrupt Status Register Masked"
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bitfld.long 0x0 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
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group.long 0x3D028++0x7
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line.long 0x0 "INT_ENABLE_REG,Interrupt Enable Register"
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bitfld.long 0x0 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
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line.long 0x4 "TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
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hexmask.long.byte 0x4 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
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wgroup.long 0x3D030++0x3
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line.long 0x0 "EVENT_POP_REG,Event Pop Register"
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bitfld.long 0x0 0. "EVENT_POP,Event pop" "0,1"
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rgroup.long 0x3D034++0xF
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line.long 0x0 "EVENT_0_REG,Event 0 Register"
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hexmask.long 0x0 0.--31. 1. "TIME_STAMP,Time Stamp"
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line.long 0x4 "EVENT_1_REG,Event 1 Register"
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bitfld.long 0x4 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
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hexmask.long.byte 0x4 24.--28. 1. "PORT_NUMBER,Port number"
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hexmask.long.byte 0x4 20.--23. 1. "EVENT_TYPE,Event type"
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hexmask.long.byte 0x4 16.--19. 1. "MESSAGE_TYPE,Message type"
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hexmask.long.word 0x4 0.--15. 1. "SEQUENCE_ID,Sequence ID"
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line.long 0x8 "EVENT_2_REG,Event 2 Register"
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hexmask.long.byte 0x8 0.--7. 1. "DOMAIN,Domain"
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line.long 0xC "EVENT_3_REG,Event 3 Register"
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hexmask.long 0xC 0.--31. 1. "TIME_STAMP,Time Stamp"
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group.long 0x3D044++0x17
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line.long 0x0 "TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
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hexmask.long 0x0 0.--31. 1. "TS_LOAD_VAL,Time stamp load high value"
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line.long 0x4 "TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
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hexmask.long 0x4 0.--31. 1. "TS_COMP_HIGH_VAL,Time stamp comparison high value"
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line.long 0x8 "TS_ADD_VAL_REG,TS Add Value Register"
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bitfld.long 0x8 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
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line.long 0xC "TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
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hexmask.long 0xC 0.--31. 1. "TS_PPM_LOW_VAL,Time stamp PPM Low value"
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line.long 0x10 "TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
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hexmask.long.word 0x10 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
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line.long 0x14 "TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
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hexmask.long.byte 0x14 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
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group.long 0x3D0E0++0x1B
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line.long 0x0 "TS_GENF_COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
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hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp Generate Function Comparison Low Value"
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line.long 0x4 "TS_GENF_COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
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hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp Generate Function Comparison High Value"
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line.long 0x8 "TS_GENF_CONTROL_REG,Time Stamp Generate Function Control"
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bitfld.long 0x8 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1"
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bitfld.long 0x8 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1"
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line.long 0xC "LENGTH_REG,Time Stamp Generate Function Length Value"
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hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp Generate Function Length Value"
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line.long 0x10 "PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
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hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp Generate Function PPM Low Value"
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line.long 0x14 "PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
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hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
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line.long 0x18 "NUDGE_REG,Time Stamp Generate Function Nudge Value"
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hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
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group.long 0x3D200++0x1B
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line.long 0x0 "TS_ESTF_COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value"
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hexmask.long 0x0 0.--31. 1. "COMP_LOW,Time Stamp ESTF Generate Function Comparison Low Value"
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line.long 0x4 "TS_ESTF_COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value"
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hexmask.long 0x4 0.--31. 1. "COMP_HIGH,Time Stamp ESTF Generate Function Comparison High Value"
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line.long 0x8 "TS_ESTF_CONTROL_REG,Time Stamp ESTF Generate Function Control"
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bitfld.long 0x8 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1"
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bitfld.long 0x8 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1"
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line.long 0xC "TS_ESTF_LENGTH_REG,Time Stamp ESTF Generate Function Length Value"
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hexmask.long 0xC 0.--31. 1. "LENGTH,Time Stamp ESTF Generate Function Length Value"
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line.long 0x10 "TS_ESTF_PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value"
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hexmask.long 0x10 0.--31. 1. "PPM_LOW,Time Stamp ESTF Generate Function PPM Low Value"
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line.long 0x14 "TS_ESTF_PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value"
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hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value"
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line.long 0x18 "TS_ESTF_NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value"
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hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value"
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rgroup.long 0x3E000++0x7
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line.long 0x0 "ALE_MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE_2g32 module."
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hexmask.long.word 0x0 16.--31. 1. "MODULE_ID,ALE_2g32 module ID."
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hexmask.long.byte 0x0 11.--15. 1. "RTL_VERSION,RTL Version."
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bitfld.long 0x0 8.--10. "MAJOR_REVISION,Major Revision." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM_REVISION,Custom Revision." "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "MINOR_REVISION,Minor Revision."
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line.long 0x4 "ALE_STATUS,The ALE status provides information on the ALE configuration and state. The ~iramdepth is used to determine how IPv6 entries are stored in the table. IPv6 entries are stored in two entries where IPv6 Entry hi is designated by the odd slice.."
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bitfld.long 0x4 31. "UREGANDREGMSK12,When set the unregistered multicast field is a mask versus an index on 12 bit boundary in the ALE table." "0,1"
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bitfld.long 0x4 30. "UREGANDREGMSK08,When set the unregistered multicast field is a mask versus an index on 8 bit boundary in the ALE table." "0,1"
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hexmask.long.byte 0x4 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8. A value of 4 indicates 32 policer engines total."
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bitfld.long 0x4 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1"
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bitfld.long 0x4 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64." "0,1"
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hexmask.long.byte 0x4 0.--4. 1. "KLUENTRIES,This is the number of table entries total divided by 1024. A value of 1 indicates 1024 table entries. A value of 8 indicates 8192 table entries."
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group.long 0x3E008++0xF
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line.long 0x0 "ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports."
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bitfld.long 0x0 31. "ENABLE_ALE,Enable ALE 0 - Drop all packets 1 - Enable ALE packet processing" "0: Drop all packets 1,?"
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bitfld.long 0x0 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero. Software must perform a clear table operation as part of the ALE setup/configuration process. Setting this bit causes all ALE accesses.." "0,1"
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bitfld.long 0x0 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit. This bit is cleared when the age out process has completed. This bit may be read. The age out.." "0,1"
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bitfld.long 0x0 24. "MIRROR_DP,Mirror Destination Port - This field defines the port to which destination traffic destined will be duplicated. That is all traffic that is forwarded to this port will also be mirrored to the ~imirror_top port." "0,1"
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bitfld.long 0x0 21.--23. "UPD_BW_CTRL,The ~iupd_bw_ctrl field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur. At frequencies of 350Mhz the table update rate should be at it lowest or 5 Million updates per second. When.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 16. "MIRROR_TOP,Mirror To Port - This field defines the destination port for the mirror traffic. If the traffic is received or transmitted on the mirror destination port it will not be duplicated. Traffic defined as mirror traffic only may be dropped by the.." "0,1"
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bitfld.long 0x0 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable. When clear this bit will prevent any static entry (agable bit clear) from being updated due to port change. When set it allows static entries (agable bit clear) to update.." "0,1"
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bitfld.long 0x0 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn - This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled." "0,1"
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bitfld.long 0x0 12. "MIRROR_MEN,Mirror Match Entry Enable - This field enables the match mirror option. When this bit is set any traffic whose destination source VLAN or OUI matches the ~imirror_midx entry index will have that traffic also sent to the ~imirror_top port." "0,1"
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bitfld.long 0x0 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option. When this bit is set any traffic destined for the ~imirror_dp port will have its transmit traffic also sent to the ~imirror_top port." "0,1"
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bitfld.long 0x0 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option. When this bit is set any port with the ~ipX_mirror_sp set in the ALE Port Control registers set will have its received traffic also sent to the ~imirror_top port." "0,1"
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bitfld.long 0x0 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host 0 - unknown unicast packets are not sent to the host 1 - unknown unicast packets flood to host port as well as other ports" "0: unknown unicast packets are not sent to the host..,?"
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bitfld.long 0x0 7. "LEARN_NO_VLANID,Learn No VID - 0 - VID is learned with the source address 1 - VID is not learned with the source address (source address is not tied to VID). Determines the entry type." "0: VID is learned with the source address 1,?"
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bitfld.long 0x0 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode 0 - Process the priority tagged packet with VID = PORT_VLAN[11:0]. 1 - Process the priority tagged packet with VID = 0." "0: Process the priority tagged packet with VID =..,1: Process the priority tagged packet with VID = 0"
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bitfld.long 0x0 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry. When cleared any packet source.." "0,1"
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bitfld.long 0x0 4. "ENABLE_BYPASS,ALE Bypass - When set packets received on non-host ports are sent to the host. It is expected that packets from the host are directed to the particular port. 0 - no bypass 1 - bypass the ALE" "0: no bypass 1,?"
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bitfld.long 0x0 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode 0 - Broadcast and multicast rate limit counters are received port based 1 - Broadcast and multicast rate limit counters are transmit port based" "0: Broadcast and multicast rate limit counters are..,?"
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bitfld.long 0x0 2. "ALE_VLAN_AWARE,ALE VLAN Aware - Determines how traffic is forwarded using VLAN rules. 0 - Simple switch rules packets forwarded to all ports for unknown destinations. 1 - VLAN Aware rules packets forwarded based on VLAN members" "0: Simple switch rules,1: VLAN Aware rules"
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bitfld.long 0x0 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software. There is no auto learning of addresses in authorization mode and the packet will be dropped if the source address is not.." "0: The ALE is not in MAC authorization mode 1,?"
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bitfld.long 0x0 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit 0 - Broadcast/Multicast rates not limited 1 - Broadcast/Multicast packet reception limited to the port control register rate limit fields." "0: Broadcast/Multicast rates not limited 1,?"
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line.long 0x4 "ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports."
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bitfld.long 0x4 31. "TRK_EN_DST,Trunk Enable Destination Address - This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1"
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bitfld.long 0x4 30. "TRK_EN_SRC,Trunk Enable Source Address - This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1"
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bitfld.long 0x4 29. "TRK_EN_PRI,Trunk Enable Priority - This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. In the event that DSCP mapping is enabled and there is no VLAN the.." "0,1"
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bitfld.long 0x4 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN - This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination." "0,1"
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bitfld.long 0x4 25. "TRK_EN_SIP,Trunk Enable Source IP Address - This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN.." "0,1"
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bitfld.long 0x4 24. "TRK_EN_DIP,Trunk Enable Destination IP Address - This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged .." "0,1"
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|
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bitfld.long 0x4 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet. Ethertypes 0-1500 are 802.3 lengths all others are Ether types." "0,1"
|
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|
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bitfld.long 0x4 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set." "0,1"
|
|
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|
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bitfld.long 0x4 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found." "0,1"
|
|
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|
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bitfld.long 0x4 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the ~iALE_NXT_HDR register values." "0,1"
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bitfld.long 0x4 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value. Changing this value will cause the packet distribution on trunk ports to be changed. If all the ~itrk_en_dst ~itrk_en_src ~itrk_en_pri and ~itrk_en_vlan are '0' this value is used as.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 0.--4. 1. "MIRROR_MIDX,Mirror Index - This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the ~imirror_top port. That is any VLAN ONU or address with or withou VLAN can be selected for traffic mirroring."
|
|
line.long 0x8 "ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "ALE_PRESCALE,ALE Prescale - The input clock is divided by this value for use in the multicast/broadcast rate limiters. The minimum operating value is 0x10. The prescaler is off when the value is zero."
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|
line.long 0xC "ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur. This value specifies the minimum time between aging starts."
|
|
bitfld.long 0xC 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable - When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1"
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bitfld.long 0xC 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable - When set will divide the aging interval by 1000. This bit is designed for device verification and should not be used in production software. Combination of PreScale1Disable and PreScale2Disable will divide the.." "0,1"
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hexmask.long.tbyte 0xC 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer - This field specifies the number of clock cycles times 1 000 000 between aging operations."
|
|
group.long 0x3E01C++0x7
|
|
line.long 0x0 "ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header. It is enabled via the ~iLmtNxtHdr bit in the VLAN entry. All four ~iip_nxt_hdr0-3 are compared when enabled. so if only one is required..."
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hexmask.long.byte 0x0 24.--31. 1. "IP_NXT_HDR3,The ~iip_nxt_hdr3 is the forth protocol or next header compared when enabled."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "IP_NXT_HDR2,The ~iip_nxt_hdr2 is the third protocol or next header compared when enabled."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "IP_NXT_HDR1,The ~iip_nxt_hdr1 is the second protocol or next header compared when enabled."
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hexmask.long.byte 0x0 0.--7. 1. "IP_NXT_HDR0,The ~iip_nxt_hdr0 is the first protocol or next header compared when enabled."
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line.long 0x4 "ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries. After writing to this register any read or write to any ALE register will be stalled until the read or write operation completes."
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bitfld.long 0x4 31. "TABLEWR,Table Write - This bit is used to write the table words to the lookup table. 0 - Table Read Operation is performed. The contents of the ~b TABLEIDX entry will be read into the ~b ALE_TBLWx registers 1 - Table write operation is performed." "0: Table Read Operation is performed,1: Table write operation is performed"
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hexmask.long.byte 0x4 0.--4. 1. "TABLEIDX,The table index is used to determine which lookup table entry is read or written."
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group.long 0x3E034++0xB
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line.long 0x0 "ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry."
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hexmask.long.byte 0x0 0.--6. 1. "TABLEWRD2,Table Entry bits [71:64]"
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line.long 0x4 "ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry."
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hexmask.long 0x4 0.--31. 1. "TABLEWRD1,Table Entry bits [63:32]"
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line.long 0x8 "ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry."
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hexmask.long 0x8 0.--31. 1. "TABLEWRD0,Table Entry bits [31:0]"
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repeat 2. (list 0x0 0x1)(list 0x0 0x4)
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group.long ($2+0x3E040)++0x3
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line.long 0x0 "I0_ALE_PORTCTL0_$1,The ALE Port Control Register sets the port specific modes of operation."
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hexmask.long.byte 0x0 24.--31. 1. "I0_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.."
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hexmask.long.byte 0x0 16.--23. 1. "I0_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or.."
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bitfld.long 0x0 15. "I0_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN - When set cause any received packet with double VLANs to be dropped. That is if there are two ctag or two stag fields in the packet it will be dropped." "0,1"
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bitfld.long 0x0 14. "I0_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN - When set will cause any received packet with dual VLAN stag followed by ctag to be dropped." "0,1"
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bitfld.long 0x0 13. "I0_REG_P0_MACONLY_CAF,Mac Only Copy All Frames - When set a Mac Only port will transfer all received good frames to the host. When clear a Mac Only port will transfer packets to the host based on ALE destination address lookup operation (which operates.." "0,1"
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bitfld.long 0x0 12. "I0_REG_P0_DIS_PAUTHMOD,Disable Port authorization - When set will allow unknown addresses to arrive on a switch in authorization mode. It is intended for device to device network connection on ports which do not require MACSEC encryption." "0,1"
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bitfld.long 0x0 11. "I0_REG_P0_MACONLY,MAC Only - When set enables this port be treated like a MAC port for the host. All traffic received is only sent to the host. The host must direct traffic to this port as the lookup engine will not send traffic to the ports with the.." "0,1"
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bitfld.long 0x0 10. "I0_REG_P0_TRUNKEN,Trunk Enable - This field is used to enable a port into a trunk. Any port can be used as a trunk port any two or more ports with the ~ip0_trunken its set and having the same ~ip0_trunknum will be placed in the same trunk. There is no.." "0,1"
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bitfld.long 0x0 8.--9. "I0_REG_P0_TRUNKNUM,Trunk Number - This field is used as the trunk number when the ~ip0_trunken is also set. Ports with the same trunk number that have the ~ip0_trunken also set will have traffic distributed within the trunk based on the result of the.." "0,1,2,3"
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bitfld.long 0x0 7. "I0_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option. When this bit is set any traffic received on the port with the reg_p0_mirror_sp bit set will have its received traffic also sent to the ~imirror_top port." "0,1"
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bitfld.long 0x0 5. "I0_REG_P0_NO_SA_UPDATE,No Source Address Update - When set will not update the source addresses for this port." "0,1"
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bitfld.long 0x0 4. "I0_REG_P0_NO_LEARN,No Learn - When set will not learn the source addresses for this port." "0,1"
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bitfld.long 0x0 3. "I0_REG_P0_VID_INGRESS_CHECK,VLAN Ingress Check - When set if a packet received is not a member of the VLAN the packet will be dropped." "0,1"
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bitfld.long 0x0 2. "I0_REG_P0_DROP_UN_TAGGED,If Drop Untagged - When set will drop packets without a VLAN tag." "0,1"
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bitfld.long 0x0 0.--1. "I0_REG_P0_PORTSTATE,Port State - Defins the current port state used for lookup operations. 0 - Disabled 1 - Blocked 2 - Learning 3 - Forwarding" "0: Disabled 1,?,2: Learning 3,?"
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repeat.end
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group.long 0x3E090++0xF
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line.long 0x0 "ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID."
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bitfld.long 0x0 0.--1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List - Each bit represents the port member status for unknown VLANs." "0,1,2,3"
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line.long 0x4 "ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID."
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bitfld.long 0x4 0.--1. "UVLAN_UNREG_MCAST,Unknown VLAN Unregister Multicast Flood Mask - Each bit represents the port to which unregistered multicast are sent for unregistered VLANs." "0,1,2,3"
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line.long 0x8 "ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID."
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bitfld.long 0x8 0.--1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask - Each bit represents the port to which registered multicast are sent for unregistered VLANs. This field is ANDed with the registered multicast mask to determine the destinations for.." "0,1,2,3"
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line.long 0xC "ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed."
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bitfld.long 0xC 0.--1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask - Each bit represents the port where the VLAN will be removed for unregistered VLANs." "0,1,2,3"
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group.long 0x3E0B8++0x7
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line.long 0x0 "ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters. This register is for diagnostice only."
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bitfld.long 0x0 15. "PBCAST_DIAG,When set and the ~iport_diag is set to zero will allow all ports to see the same stat diagnostic increment." "0,1"
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bitfld.long 0x0 8. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received. For the selected Port. 0: Disabled 1: Destination Equal Source Drop Stat will count 2: VLAN Ingress Check Drop Stat will count 3: Source.."
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line.long 0x4 "ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port."
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bitfld.long 0x4 0.--1. "OAM_LB_CTRL,The ~ioam_lb_ctrl allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an egressop of 0xFF which swaps the source and destination address. BPDUs will still flow through as normal so.." "0,1,2,3"
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rgroup.long 0x3E0C0++0x3
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line.long 0x0 "ALE_MSK_MUX0,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively."
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bitfld.long 0x0 0.--1. "VLAN_MASK_MUX_0,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets. The Value of vlan_mask_mux_0.." "0,1,2,3"
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repeat 3. (list 0x0 0x1 0x2)(list 0x0 0x4 0x8)
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group.long ($2+0x3E0C4)++0x3
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line.long 0x0 "I1_ALE_MSK_MUX1_$1,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively."
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bitfld.long 0x0 0.--1. "I1_REG_VLAN_MASK_MUX_1,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets. The Value of.." "0,1,2,3"
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repeat.end
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group.long 0x3E0FC++0x17
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line.long 0x0 "EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions. If the packet was destined for the host. but matches a clasifier that has a programmed.."
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hexmask.long.byte 0x0 24.--31. 1. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations 0: NOP : 1-n: Defines which egress Operation will be performed. This allows Inter VLAN routing to be configured for high bandwidth traffic .."
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bitfld.long 0x0 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well. The DA SA and VLAN are ignored for trunk generation on InterVLAN Routing so that this field is the.." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions. The packet will be routed to the host it was destined to." "0,1"
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bitfld.long 0x0 0.--1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to. If a destination is a Trunk all the port bits for that trunck must be set." "0,1,2,3"
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line.long 0x4 "POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching."
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bitfld.long 0x4 31. "PORT_MEN,Port Match Enable - Enabled port match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x4 30. "TRUNKID,Trunk ID - When set indicates the port number is a trunk group." "0,1"
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bitfld.long 0x4 25. "PORT_NUM,Port Number - Specifies the port address to match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x4 19. "PRI_MEN,Priority Match Enable - Enables frame priority match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x4 16.--18. "PRI_VAL,Priority Value - Specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 15. "ONU_MEN,OUI Match Enable - Enables frame ONU address match for the selected policing/classifier entry" "0,1"
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newline
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hexmask.long.byte 0x4 0.--4. 1. "ONU_INDEX,OUI Table Entry Index - Specifies the ALE ONU address lookup table index to match for the selected policing/classifier entry"
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line.long 0x8 "POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses"
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bitfld.long 0x8 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1"
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newline
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hexmask.long.byte 0x8 16.--20. 1. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry"
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newline
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bitfld.long 0x8 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1"
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hexmask.long.byte 0x8 0.--4. 1. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry"
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line.long 0xC "POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses"
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bitfld.long 0xC 31. "OVLAN_MEN,Outer VLAN Match Enable - Enables frame Outer VLAN address match for the selected policing/classifier entry" "0,1"
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hexmask.long.byte 0xC 16.--20. 1. "OVLAN_INDEX,Outer VLAN Table Entry Index - Specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry"
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newline
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bitfld.long 0xC 15. "IVLAN_MEN,Inner VLAN Match Enable - Enables frame Inner VLAN address match for the selected policing/classifier entry" "0,1"
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|
newline
|
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hexmask.long.byte 0xC 0.--4. 1. "IVLAN_INDEX,Inner VLAN Table Entry Index - Specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry"
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line.long 0x10 "POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address"
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bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable - Enables frame Ether Type match for the selected policing/classifier entry" "0,1"
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newline
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hexmask.long.byte 0x10 16.--20. 1. "ETHERTYPE_INDEX,EtherType Table Entry Index - Specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry"
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newline
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bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable - Enables frame IP Source address match for the selected policing/classifier entry" "0,1"
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|
newline
|
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hexmask.long.byte 0x10 0.--4. 1. "IPSRC_INDEX,IP Source Address Table Entry Index - Specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry"
|
|
line.long 0x14 "POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address"
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bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable - Enables frame IP Destination address match for the selected policing/classifier entry" "0,1"
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newline
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hexmask.long.byte 0x14 16.--20. 1. "IPDST_INDEX,IP Destination Address Table Entry Index - Specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry"
|
|
group.long 0x3E118++0x13
|
|
line.long 0x0 "POLICECFG6,The PIR counter is a 37 bit internal counter where ~ipir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time. If the counter is negative the packet will be marked RED. else it can be YELLOW or.."
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hexmask.long 0x0 0.--31. 1. "PIR_IDLE_INC_VAL,Peak Information Rate Idle Increment Value - The number added to the PIR counter every clock cycle. If zero the PIR counter is disabled and packets will never be marked or processed as RED."
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line.long 0x4 "POLICECFG7,The CIR counter is a 37 bit internal counter where ~icir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time. If the counter is positive the packet will be marked GREEN. else it can.."
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hexmask.long 0x4 0.--31. 1. "CIR_IDLE_INC_VAL,Committed Information Idle Increment Value - The number added to the CIR counter every clock cycle. If zero the CIR counter is disabled and packets will never be marked or processed as YELLOW."
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line.long 0x8 "POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry. The selected policing/classifier entry is only read or written after this register is written based on the value of the ~iwrite_enable bit."
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bitfld.long 0x8 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the POLICECFG0-7 to the ~ipol_tbl_idx selected policing/classifier entry. Clearing this bit will read the ~ipol_tbl_idx selected policing/classifier entry into the POLICECFG0-7 registers." "0,1"
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newline
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bitfld.long 0x8 0.--1. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written. When writing to this field without setting the ~iwrite_enable=1 will cause the selected policing/classifier entry to be loaded into the.." "0,1,2,3"
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|
line.long 0xC "POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules."
|
|
bitfld.long 0xC 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities." "0,1"
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|
newline
|
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bitfld.long 0xC 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets." "0,1"
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|
newline
|
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bitfld.long 0xC 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the ~iyellowthresh value. This field would normally not be used as to let the switch drop packets at a buffer threshold instead. In the event that the switch does not.." "0,1"
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newline
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bitfld.long 0xC 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the ~iyellow_drop_en enable. 0-100% 1=50% 2-33% 3-25% 4=20% 5-17% 6-14% 7-13%" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0xC 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry. 0 - No Hit packets are marked GREEN 1 - No Hit packets are marked YELLOW 2 - No Hit packets are marked RED 3 -.." "0: No Hit packets are marked GREEN 1,?,2: No Hit packets are marked RED 3,?"
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newline
|
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bitfld.long 0xC 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled." "0,1"
|
|
newline
|
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bitfld.long 0xC 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports. That is the default thread will be {port priority}. If the traffic matches a classifier with a thread mapping the classifier thread mapping.." "0,1"
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|
line.long 0x10 "POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition."
|
|
bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit." "0,1"
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newline
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bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a RED condition." "0,1"
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newline
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bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits. This bit is self clearing. This can be used to test the fact that a policing/classifier entry has been hit during a YELLOW condition." "0,1"
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newline
|
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bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits. This bit is self clearing." "0,1"
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|
newline
|
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bitfld.long 0x10 0.--1. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written." "0,1,2,3"
|
|
rgroup.long 0x3E12C++0x3
|
|
line.long 0x0 "POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier."
|
|
bitfld.long 0x0 31. "POL_HIT,Policer Hit - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit by a packet seen on any port that matches the policing/classifier entry match." "0,1"
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|
newline
|
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bitfld.long 0x0 30. "POL_REDHIT,Policer Hit RED - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a RED condition by a packet seen on any port that matches the policing/classifier entry match." "0,1"
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|
newline
|
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bitfld.long 0x0 29. "POL_YELLOWHIT,Policer Hit YELLOW - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a YELLOW condition by a packet seen on any port that matches the policing/classifier entry match." "0,1"
|
|
group.long 0x3E134++0xB
|
|
line.long 0x0 "THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched."
|
|
bitfld.long 0x0 15. "DEFTHREAD_EN,Default Tread Enable - When set the switch will use the ~idefthreadval for the host interface thread ID if no classifier is matched. If clear the switch will generate its own thread ID based on port and priority if there is no classifier.." "0,1"
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|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "DEFTHREADVAL,Default Thread Value - This field specifies the default thread ID value."
|
|
line.long 0x4 "THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host. This allows particular classifier matched traffic to be placed an a particular hosts queue."
|
|
bitfld.long 0x4 0.--1. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the ~bTHREADMAPVAL register." "0,1,2,3"
|
|
line.long 0x8 "THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry."
|
|
bitfld.long 0x8 15. "THREAD_EN,Thread Enable - When set the switch will use the ~ithreadval for the selected classifier match. If clear the the thread ID will be determined by the ~bTHREADMAPDEF register settings." "0,1"
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|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "THREADVAL,Thread Value - This field is the thread ID value that is used to map a classifier hit to thread ID for host traffic."
|
|
rgroup.long 0x3F000++0x3
|
|
line.long 0x0 "rev,Revision parameters"
|
|
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
|
|
newline
|
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hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
|
|
group.long 0x3F008++0x3
|
|
line.long 0x0 "vector,ECC Vector Register"
|
|
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
|
|
newline
|
|
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0x3F00C++0x3
|
|
line.long 0x0 "stat,Misc Status"
|
|
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x3F010)++0x3
|
|
line.long 0x0 "reserved_svbus_$1,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Serial VBUS register data"
|
|
repeat.end
|
|
group.long 0x3F03C++0x7
|
|
line.long 0x0 "sec_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
|
|
line.long 0x4 "sec_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
|
|
group.long 0x3F080++0x3
|
|
line.long 0x0 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
|
|
group.long 0x3F0C0++0x3
|
|
line.long 0x0 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
|
|
group.long 0x3F13C++0x7
|
|
line.long 0x0 "ded_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1"
|
|
line.long 0x4 "ded_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
|
|
group.long 0x3F180++0x3
|
|
line.long 0x0 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
|
|
group.long 0x3F1C0++0x3
|
|
line.long 0x0 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
|
|
group.long 0x3F200++0xF
|
|
line.long 0x0 "aggr_enable_set,AGGR interrupt enable set Register"
|
|
bitfld.long 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1"
|
|
line.long 0x4 "aggr_enable_clr,AGGR interrupt enable clear Register"
|
|
bitfld.long 0x4 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PARITY,interrupt enable clear for parity errors" "0,1"
|
|
line.long 0x8 "aggr_status_set,AGGR interrupt status set Register"
|
|
bitfld.long 0x8 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
|
|
line.long 0xC "aggr_status_clr,AGGR interrupt status clear Register"
|
|
bitfld.long 0xC 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
|
|
tree.end
|
|
tree "MSS_CTRL"
|
|
base ad:0x2120000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
group.long 0x4++0x1F
|
|
line.long 0x0 "MSS_SW_INT,"
|
|
hexmask.long.byte 0x0 0.--4. 1. "pulse,Write_pulse bit field: writing 1'b1 to each bit will trigger MSS_SW_INT<0-4> respectively to CR5A/B."
|
|
line.long 0x4 "MSS_CAPEVNT_SEL,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "src1,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT1 to all MSS_RTIs. Example: writing 8'h0A will select 10th interrupt to trigger CAP-EVENT1 to all MSS_RTIs. (which is MSS_RTIB_INT1)"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "src0,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT0 to all MSS_RTIs. Example: writing 8'h0A will select 10th interrupt to trigger CAP-EVENT0 to all MSS_RTIs. (which is MSS_RTIB_INT1)"
|
|
line.long 0x8 "MSS_DMA_REQ_SEL,"
|
|
hexmask.long 0x8 0.--31. 1. "select,Reserved for R&D. Do not touch"
|
|
line.long 0xC "MSS_DMA1_REQ_SEL,"
|
|
hexmask.long 0xC 0.--31. 1. "select,Reserved for R&D. Do not touch"
|
|
line.long 0x10 "MSS_IRQ_REQ_SEL,"
|
|
hexmask.long 0x10 0.--31. 1. "select,Reserved for R&D. Do not touch"
|
|
line.long 0x14 "MSS_SPI_TRIG_SRC,"
|
|
hexmask.long.word 0x14 16.--26. 1. "trig_spib,Writing 1'b1 to each bit will trigger MSS_SPIB Trigger<0-10> respectively"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "trig_spia,Writing 1'b1 to each bit will trigger MSS_SPIA Trigger<0-1> respectively" "?,1: respectively,?,?"
|
|
line.long 0x18 "MSS_ATCM_MEM_INIT,"
|
|
bitfld.long 0x18 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the ATCM banks of CR5A/B. Value in each row is initialized to 0x0C_0000_0000" "0,1"
|
|
line.long 0x1C "MSS_ATCM_MEM_INIT_DONE,"
|
|
bitfld.long 0x1C 0. "mem_init_done,This field will be high once initialization of ATCM banks is finished. Writing '1' would clear the bit." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "MSS_ATCM_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 0. "mem_status,1'b0: No initialization is happening for ATCM banks of CR5A/B 1'b1: Initialization is in progress for ATCM banks of CR5A/B" "0: No initialization is happening for ATCM banks of..,?"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "MSS_BTCM_MEM_INIT,"
|
|
bitfld.long 0x0 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1"
|
|
line.long 0x4 "MSS_BTCM_MEM_INIT_DONE,"
|
|
bitfld.long 0x4 0. "mem_init_done,This field will be high once initialization of B0/1TCM banks is finished. Writing '1' would clear the bit." "0,1"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "MSS_BTCM_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 0. "mem_status,1'b0: No initialization is happening for B0/1TCM banks of CR5A/B 1'b1: Initialization is in progress for B0/1TCM banks of CR5A/B" "0: No initialization is happening for B0/1TCM banks..,?"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "MSS_L2_MEM_INIT,"
|
|
bitfld.long 0x0 1. "partition1,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank1. Value in each row is initialized to 0x0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "partition0,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank0. Value in each row is initialized to 0x0" "0,1"
|
|
line.long 0x4 "MSS_L2_MEM_INIT_DONE,"
|
|
bitfld.long 0x4 1. "partition1,This field will be high once intialization of L2 bank1 is finished. Writing '1' would clear the bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "partition0,This field will be high once intialization of L2 bank0 is finished. Writing '1' would clear the bit" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "MSS_L2_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 1. "partition1,1'b0: No initialization is happening for L2 bank1 1'b1: Initialization is in progress for L2 bank1" "0: No initialization is happening for L2 bank1..,?"
|
|
newline
|
|
bitfld.long 0x0 0. "partition0,1'b0: No initialization is happening for L2 bank0 1'b1: Initialization is in progress for L2 bank0" "0: No initialization is happening for L2 bank0..,?"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "MSS_MAILBOX_MEM_INIT,"
|
|
bitfld.long 0x0 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_MBOX. Value in each row is initialized to 0x0" "0,1"
|
|
line.long 0x4 "MSS_MAIlBOX_MEM_INIT_DONE,"
|
|
bitfld.long 0x4 0. "mem0_done,This field will be high once intialization of MSS_MBOX is finished. Writing '1' would clear the bit" "0,1"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "MSS_MAILBOX_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 0. "mem0_status,1'b0: No initialization is happening for MSS_MBOX 1'b1: Initialization is in progress for MSS_MBOX" "0: No initialization is happening for MSS_MBOX..,?"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "MSS_RETRAM_MEM_INIT,"
|
|
bitfld.long 0x0 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_RETRAM. Value in each row is initialized to 0x0" "0,1"
|
|
line.long 0x4 "MSS_RETRAM_MEM_INIT_DONE,"
|
|
bitfld.long 0x4 0. "mem0_done,This field will be high once intialization of MSS_RETRAM is finished. Writing '1' would clear the bit" "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "MSS_RETRAM_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 0. "mem0_status,1'b0: No initialization is happening for MSS_RETRAM 1'b1: Initialization is in progress for MSS_RETRAM" "0: No initialization is happening for MSS_RETRAM..,?"
|
|
group.long 0x58++0x7
|
|
line.long 0x0 "MSS_SPIA_MEM_INIT,"
|
|
bitfld.long 0x0 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIA. Value in each row is initialized to 0x0" "0,1"
|
|
line.long 0x4 "MSS_SPIA_MEM_INIT_DONE,"
|
|
bitfld.long 0x4 0. "mem0_done,This field will be high once intialization of MSS_SPIA is finished. Writing '1' would clear the bit" "0,1"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "MSS_SPIA_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 0. "mem0_status,1'b0: No initialization is happening for MSS_SPIA 1'b1: Initialization is in progress for MSS_SPIA" "0: No initialization is happening for MSS_SPIA..,?"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "MSS_SPIB_MEM_INIT,"
|
|
bitfld.long 0x0 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIB. Value in each row is initialized to 0x0" "0,1"
|
|
line.long 0x4 "MSS_SPIB_MEM_INIT_DONE,"
|
|
bitfld.long 0x4 0. "mem0_done,This field will be high once intialization of MSS_SPIB is finished. Writing '1' would clear the bit" "0,1"
|
|
rgroup.long 0x6C++0x3
|
|
line.long 0x0 "MSS_SPIB_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 0. "mem0_status,1'b0: No initialization is happening for MSS_SPIB 1'b1: Initialization is in progress for MSS_SPIB" "0: No initialization is happening for MSS_SPIB..,?"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "MSS_TPCC_MEMINIT_START,"
|
|
bitfld.long 0x0 16. "tpcc_b_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "tpcc_a_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCA" "0,1"
|
|
line.long 0x4 "MSS_TPCC_MEMINIT_DONE,"
|
|
bitfld.long 0x4 16. "tpcc_b_meminit_done,This field will be high once intialization of MSS_TPCCB is finished. Writing '1' would clear the bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "tpcc_a_meminit_done,This field will be high once intialization of MSS_TPCCA is finished. Writing '1' would clear the bit" "0,1"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "MSS_TPCC_MEMINIT_STATUS,"
|
|
bitfld.long 0x0 16. "tpcc_b_meminit_status,1'b0: No initialization is happening for MSS_TPCCA 1'b1: Initialization is in progress for MSS_TPCCB" "0: No initialization is happening for MSS_TPCCA..,?"
|
|
newline
|
|
bitfld.long 0x0 0. "tpcc_a_meminit_status,1'b0: No initialization is happening for MSS_TPCCA 1'b1: Initialization is in progress for MSS_TPCCB" "0: No initialization is happening for MSS_TPCCA..,?"
|
|
group.long 0x7C++0x7
|
|
line.long 0x0 "MSS_GPADC_MEM_INIT,"
|
|
bitfld.long 0x0 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_GPADC_DATA_MEM. Value in each row is initialized to 0x00_0000_03FF" "0,1"
|
|
line.long 0x4 "MSS_GPADC_MEM_INIT_DONE,"
|
|
bitfld.long 0x4 0. "mem0_done,This field will be high once intialization of MSS_GPADC_DATA_MEM is finished. Writing '1' would clear the bit" "0,1"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x0 "MSS_GPADC_MEM_INIT_STATUS,"
|
|
bitfld.long 0x0 0. "mem0_status,1'b0: No initialization is happening for MSS_GPADC_DATA_MEM 1'b1: Initialization is in progress for MSS_GPADC_DATA_MEM" "0: No initialization is happening for..,?"
|
|
group.long 0x88++0x13
|
|
line.long 0x0 "MSS_SPIA_CFG,"
|
|
bitfld.long 0x0 24. "spia_int_trig_polarity,SPIA trigger source polarity select. 0 - Polarity 0 1 -Polarity 1" "0: Polarity 0,1: Polarity 1"
|
|
newline
|
|
bitfld.long 0x0 16. "spia_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "spia_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source" "?,1: Use CS as trigger source"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "spiasync2sen,Donot touch the field. Used as Tie-off for IP-config." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_SPIB_CFG,"
|
|
bitfld.long 0x4 24. "spib_int_trig_polarity,SPIB trigger source polarity select. 0 - Polarity 0 1 -Polarity 1" "0: Polarity 0,1: Polarity 1"
|
|
newline
|
|
bitfld.long 0x4 16. "spib_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "spib_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source" "?,1: Use CS as trigger source"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "spibsync2sen,Donot touch the field. Used as Tie-off for IP-config." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "MSS_EPWM_CFG,"
|
|
hexmask.long 0x8 0.--31. 1. "epwm_config,bit0: SW syncin for EPWM1 bit1: SW syncin for EPWM2 bit2: SW syncin for EPWM3 bit8:9 : select bits for EPWM1 '0' : external syncin '1' : reserved '2' : sw syncin '3' : reserved bit10:11 : select bits for EPWM2.."
|
|
line.long 0xC "MSS_GIO_CFG,"
|
|
hexmask.long 0xC 0.--31. 1. "gio_config,bit0 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT0 to IRQ bit1 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT1to IRQ bit2: writing '1' will slect negedge for pulse generation of GIO_PAD_INT2 to.."
|
|
line.long 0x10 "MSS_MCAN_FE_SELECT,"
|
|
bitfld.long 0x10 16.--18. "mcanb_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> selects MSS_MCANB_FE_INT<1-7> respectively" "?,?,?,?,?,?,?,7: selects MSS_MCANB_FE_INT<1-7> respectively"
|
|
newline
|
|
bitfld.long 0x10 0.--2. "mcana_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> would select MSS_MCANA_FE_INT<1-7> respectively" "?,?,?,?,?,?,?,7: would select MSS_MCANA_FE_INT<1-7> respectively"
|
|
repeat 3. (list 0x1 0x2 0x3)(list 0x0 0x10 0xAC)
|
|
group.long ($2+0x9C)++0x3
|
|
line.long 0x0 "HW_SPARE_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "NU,Resereved for R&D"
|
|
repeat.end
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "MSS_MCANA_INT_CLR,"
|
|
hexmask.long 0x0 0.--31. 1. "mcan_int_clr,Interrupt Clear for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit<0-31> clears interrupt source <0-31> respectively in MCANA"
|
|
line.long 0x4 "MSS_MCANA_INT_MASK,"
|
|
hexmask.long 0x4 0.--31. 1. "mcan_int_mask,Interrupt Mask for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit<0-31> masks interrupt source <0-31> respectively in MCANA"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "MSS_MCANA_INT_STAT,"
|
|
hexmask.long 0x0 0.--31. 1. "mcan_int_status,Interrupt status for 32 MCANSS TX DMA interrupts. 1'b1 in bit<0-31> gives pending status for interrupt <0-31> respectively in MCANA"
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x0 "CCC_ERR_STATUS,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "cccb_errot_status,CCCB Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ccca_errot_status,CCCA Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
|
|
group.long 0xB4++0xF
|
|
line.long 0x0 "CCCA_CFG0,"
|
|
hexmask.long.word 0x0 16.--31. 1. "ccca_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
|
|
newline
|
|
hexmask.long.byte 0x0 9.--15. 1. "Reserved,Not used"
|
|
newline
|
|
bitfld.long 0x0 8. "ccca_single_shot_mode,1: Single shot mode 0: Continuous mode" "0: Continuous mode,1: Single shot mode"
|
|
newline
|
|
bitfld.long 0x0 7. "ccca_enable_module,1'b1: Enables CCCA 1'b0: Disables CCCA" "?,1: Enables CCCA 1'b0: Disables CCCA"
|
|
newline
|
|
bitfld.long 0x0 6. "ccca_disable_clocks,1: Clock gated to counter0 and counter1 0: Normal mode" "?,1: Clock gated to counter0 and counter1 0: Normal.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "ccca_clk1_sel,Selection for Clock 1 0: Select clock0_src0 as source for counter1 1: Select clock0_src1 as source for counter1 2: Select clock0_src2 as source for counter1 ... 7: Select clock0_src7 as source for counter1" "0: Select clock0_src0 as source for counter1,1: Select clock0_src1 as source for counter1,2: Select clock0_src2 as source for counter1,?,?,?,?,7: Select clock0_src7 as source for counter1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "ccca_clk0_sel,Selection for Clock 0 0: Select clock0_src0 as source for counter0 1: Select clock0_src1 as source for counter0 2: Select clock0_src2 as source for counter0 ... 7: Select clock0_src7 as source for counter0" "0: Select clock0_src0 as source for counter0,1: Select clock0_src1 as source for counter0,2: Select clock0_src2 as source for counter0,?,?,?,?,7: Select clock0_src7 as source for counter0"
|
|
line.long 0x4 "CCCA_CFG1,"
|
|
hexmask.long 0x4 0.--31. 1. "ccca_cfg,count0_expiry_val Counter 1 is compared for count1_expected_val +/- MARGIN_COUNT when counter0 expires after counting down from count0_expiry_val to 0"
|
|
line.long 0x8 "CCCA_CFG2,"
|
|
hexmask.long 0x8 0.--31. 1. "ccca_cfg,count1_expected_val Expected value of counter 1 when counter 0 expires after counting down from count0_expiry value"
|
|
line.long 0xC "CCCA_CFG3,"
|
|
hexmask.long 0xC 0.--31. 1. "ccca_cfg,Timeout Error Counter value in counter1 clock"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "CCCA_CNTVAL,"
|
|
hexmask.long 0x0 0.--31. 1. "ccca_cfg,count1_val_out Real time value of counter1"
|
|
group.long 0xC8++0xF
|
|
line.long 0x0 "CCCB_CFG0,"
|
|
hexmask.long.word 0x0 16.--31. 1. "cccb_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
|
|
newline
|
|
hexmask.long.byte 0x0 9.--15. 1. "Reserved,Not used"
|
|
newline
|
|
bitfld.long 0x0 8. "cccb_single_shot_mode,1: Single shot mode 0: Continuous mode" "0: Continuous mode,1: Single shot mode"
|
|
newline
|
|
bitfld.long 0x0 7. "cccb_enable_module,1'b1: Enables CCCB 1'b0: Disables CCCB" "?,1: Enables CCCB 1'b0: Disables CCCB"
|
|
newline
|
|
bitfld.long 0x0 6. "cccb_disable_clocks,1: Clock gated to counter0 and counter1 0: Normal mode" "?,1: Clock gated to counter0 and counter1 0: Normal.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "CCCB_clk1_sel,Selection for Clock 1 0: Select clock0_src0 as source for counter1 1: Select clock0_src1 as source for counter1 2: Select clock0_src2 as source for counter1 ... 7: Select clock0_src7 as source for counter1" "0: Select clock0_src0 as source for counter1,1: Select clock0_src1 as source for counter1,2: Select clock0_src2 as source for counter1,?,?,?,?,7: Select clock0_src7 as source for counter1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CCCB_clk0_sel,Selection for Clock 0 0: Select clock0_src0 as source for counter0 1: Select clock0_src1 as source for counter0 2: Select clock0_src2 as source for counter0 ... 7: Select clock0_src7 as source for counter0" "0: Select clock0_src0 as source for counter0,1: Select clock0_src1 as source for counter0,2: Select clock0_src2 as source for counter0,?,?,?,?,7: Select clock0_src7 as source for counter0"
|
|
line.long 0x4 "CCCB_CFG1,"
|
|
hexmask.long 0x4 0.--31. 1. "cccb_cfg,count0_expiry_val Counter 1 is compared for count1_expected_val +/- MARGIN_COUNT when counter0 expires after counting down from count0_expiry_val to 0"
|
|
line.long 0x8 "CCCB_CFG2,"
|
|
hexmask.long 0x8 0.--31. 1. "cccb_cfg,count1_expected_val Expected value of counter 1 when counter 0 expires after counting down from count0_expiry value"
|
|
line.long 0xC "CCCB_CFG3,"
|
|
hexmask.long 0xC 0.--31. 1. "cccb_cfg,Timeout Error Counter value in counter1 clock"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "CCCB_CNTVAL,"
|
|
hexmask.long 0x0 0.--31. 1. "cccb_cfg,count1_val_out Real time value of counter1"
|
|
group.long 0xDC++0x4B
|
|
line.long 0x0 "CCC_DCC_COMMON,"
|
|
bitfld.long 0x0 12. "enable_cccb_err_nmi,1'b0:Enable CCCB error to generate NMI. 1'b1:disables CCCB error to generate NMI." "0: Enable CCCB error to generate NMI,1: disables CCCB error to generate NMI"
|
|
newline
|
|
bitfld.long 0x0 8. "enable_cccb_err_rstn,1'b0: Enable CCCB error to generate WD restn. 1'b1: disables CCCB error to generate WD restn." "0: Enable CCCB error to generate WD restn,1: disables CCCB error to generate WD restn"
|
|
line.long 0x4 "R5_GLOBAL_CONFIG,"
|
|
bitfld.long 0x4 0. "teinit,Exception handling state at reset. 0-ARM 1-Thumb" "0: ARM 1-Thumb,?"
|
|
line.long 0x8 "R5_AHB_EN,"
|
|
bitfld.long 0x8 16.--18. "cpu1_ahb_init,Ti internal Register. Modifying this register is not recommended Signal decides whehter ahb interface is enabled or not." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0.--2. "cpu0_ahb_init,Ti internal Register. Modifying this register is not recommended Signal decides whehter ahb interface is enabled or not." "0,1,2,3,4,5,6,7"
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line.long 0xC "R5A_AHB_BASE,"
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hexmask.long.tbyte 0xC 0.--19. 1. "ahb_base,Ti internal Register. Modifying this register is not recommended Decides the base address of ahb region"
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line.long 0x10 "R5A_AHB_SIZE,"
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hexmask.long.byte 0x10 0.--4. 1. "ahb_size,Ti internal Register. Modifying this register is not recommended Code for selecting size for ahb. b00011 4KB b00100 8KB b00101 16KB b00110 32KB b00111 64KB b01000 128KB b01001 256KB b01010 512KB b01011 1MB b01100.."
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line.long 0x14 "R5B_AHB_BASE,"
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hexmask.long.tbyte 0x14 0.--19. 1. "ahb_base,Ti internal Register. Modifying this register is not recommended Decides the base address of ahb region"
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line.long 0x18 "R5B_AHB_SIZE,"
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hexmask.long.byte 0x18 0.--4. 1. "ahb_size,Ti internal Register. Modifying this register is not recommended Code for selecting size for ahb. b00011 4KB b00100 8KB b00101 16KB b00110 32KB b00111 64KB b01000 128KB b01001 256KB b01010 512KB b01011 1MB b01100.."
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line.long 0x1C "R5_TCM_EXT_ERR_EN,"
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bitfld.long 0x1C 16.--18. "cpu1_tcm,Ti internal Register. Modifying this register is not recommended TCMs external error enable. Tie each bit high to enable the external error signal for each TCM at reset" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "cpu0_tcm,Ti internal Register. Modifying this register is not recommended TCMs external error enable. Tie each bit high to enable the external error signal for each TCM at reset" "0,1,2,3,4,5,6,7"
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line.long 0x20 "R5_TCM_ERR_EN,"
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bitfld.long 0x20 16.--18. "cpu1_tcm,Ti internal Register. Modifying this register is not recommended TCMs ECC check enable. Tie each bit high to enable ECC checking on appropraite TCM" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 0.--2. "cpu0_tcm,Ti internal Register. Modifying this register is not recommended TCMs ECC check enable. Tie each bit high to enable ECC checking on appropraite TCM" "0,1,2,3,4,5,6,7"
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line.long 0x24 "R5_INIT_TCM,"
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bitfld.long 0x24 20.--22. "lockzram_cpu1,Ti internal Register. Modifying this register is not recommended When HIGH ATCM base address at reset is 0x0 when LOW BTCM base address at reset is 0x0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "tcmb_cpu1,Ti internal Register. Modifying this register is not recommended When HIGH enables BTCM interface out of reset" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 12.--14. "tcma_cpu1,Ti internal Register. Modifying this register is not recommended When HIGH enables ATCM interface out of reset" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 8.--10. "lockzram_cpu0,Ti internal Register. Modifying this register is not recommended When HIGH ATCM base address at reset is 0x0 when LOW BTCM base address at reset is 0x0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 4.--6. "tcmb_cpu0,Ti internal Register. Modifying this register is not recommended When HIGH enables BTCM interface out of reset" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 0.--2. "tcma_cpu0,Ti internal Register. Modifying this register is not recommended When HIGH enables ATCM interface out of reset" "0,1,2,3,4,5,6,7"
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line.long 0x28 "R5_TCM_ECC_WRENZ_EN,"
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bitfld.long 0x28 20.--22. "cpu1_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B. Writing '111' unblocks the writes to ECC-bits of TCMB1-RAM of CR5B" "0: RAM of CR5B,1: RAM of CR5B,?,?,?,?,?,?"
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bitfld.long 0x28 16.--18. "cpu1_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B. Writing '111' unblocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0: RAM of CR5B,?,?,?,?,?,?,?"
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bitfld.long 0x28 12.--14. "cpu1_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5B. Writing '111' unblocks the writes to ECC-bits of TCMA-RAM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 8.--10. "cpu0_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A. Writing '111' unblocks the writes to ECC-bits of TCMB1-RAM of CR5A" "0: RAM of CR5A,1: RAM of CR5A,?,?,?,?,?,?"
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bitfld.long 0x28 4.--6. "cpu0_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A. Writing '111' unblocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0: RAM of CR5A,?,?,?,?,?,?,?"
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bitfld.long 0x28 0.--2. "cpu0_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5A. Writing '111' unblocks the writes to ECC-bits of TCMA-RAM of CR5A" "0,1,2,3,4,5,6,7"
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line.long 0x2C "ESM_GATING0,"
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hexmask.long 0x2C 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_7"
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line.long 0x30 "ESM_GATING1,"
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hexmask.long 0x30 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_15"
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line.long 0x34 "ESM_GATING2,"
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hexmask.long 0x34 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_23"
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line.long 0x38 "ESM_GATING3,"
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hexmask.long 0x38 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_31"
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line.long 0x3C "ESM_GATING4,"
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hexmask.long 0x3C 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_7"
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line.long 0x40 "ESM_GATING5,"
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hexmask.long 0x40 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_15"
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line.long 0x44 "ESM_GATING6,"
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hexmask.long 0x44 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_23"
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line.long 0x48 "ESM_GATING7,"
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hexmask.long 0x48 0.--31. 1. "esm_gating,bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_31"
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rgroup.long 0x128++0x17
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line.long 0x0 "ERR_PARITY_ATCM0,"
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hexmask.long.tbyte 0x0 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5A"
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line.long 0x4 "ERR_PARITY_ATCM1,"
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hexmask.long.tbyte 0x4 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5B"
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line.long 0x8 "ERR_PARITY_B0TCM0,"
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hexmask.long.tbyte 0x8 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5A"
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line.long 0xC "ERR_PARITY_B0TCM1,"
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hexmask.long.tbyte 0xC 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5B"
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line.long 0x10 "ERR_PARITY_B1TCM0,"
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hexmask.long.tbyte 0x10 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5A"
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line.long 0x14 "ERR_PARITY_B1TCM1,"
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hexmask.long.tbyte 0x14 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5B"
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group.long 0x140++0x7
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line.long 0x0 "TCM_PARITY_CTRL,"
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bitfld.long 0x0 20.--22. "b1tcm1_erraddr_clr,Write pulse bit field: writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 16.--18. "b1tcm0_erraddr_clr,Write pulse bit field: writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 12.--14. "b0cm1_erraddr_clr,Write pulse bit field: writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "b0tcm0_erraddr_clr,Write pulse bit field: writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "atcm1_erraddr_clr,Write pulse bit field: writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "atcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
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line.long 0x4 "TCM_PARITY_ERRFRC,"
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bitfld.long 0x4 20.--22. "b1tcm1,Write pulse bit field: writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 16.--18. "b1tcm0,Write pulse bit field: writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 12.--14. "b0tcm1,Write pulse bit field: writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 8.--10. "b0tcm0,Write pulse bit field: writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 4.--6. "atcm1,Write pulse bit field: writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "atcm0,Write pulse bit field: writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
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group.long 0x14C++0x13
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line.long 0x0 "SPIA_IO_CFG,"
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bitfld.long 0x0 16.--18. "miso_oen_by_cs,MIBSPIA MISO OE_N Control based on Chip selectCS-applicable in slave mode 1:MISO OEN controlled based on CS.When CS is inactive OE_N=1 0:MISO OEN controlled by IP" "0: MISO OEN controlled by IP,1: MISO OEN controlled based on CS,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "cs_pol,MIBSPIA CS polarity-slave mode 1: Active high 0:Active low" "?,1: Active high 0:Active low,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "cs_deact,1 : MIBSPIA External chip select is overridden with the value of MIBSPIA CS polarity-slave mode" "?,1: MIBSPIA External chip select is overridden with..,?,?,?,?,?,?"
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line.long 0x4 "SPIB_IO_CFG,"
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bitfld.long 0x4 16.--18. "miso_oen_by_cs,MIBSPIB MISO OE_N Control based on Chip selectCS-applicable in slave mode 1:MISO OEN controlled based on CS.When CS is inactive OE_N=1 0:MISO OEN controlled by IP" "0: MISO OEN controlled by IP,1: MISO OEN controlled based on CS,?,?,?,?,?,?"
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bitfld.long 0x4 8.--10. "cs_pol,MIBSPIB CS polarity-slave mode 1: Active high 0:Active low" "?,1: Active high 0:Active low,?,?,?,?,?,?"
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bitfld.long 0x4 0.--2. "cs_deact,1 : MIBSPIB External chip select is overridden with the value of MIBSPIB CS polarity-slave mode" "?,1: MIBSPIB External chip select is overridden with..,?,?,?,?,?,?"
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line.long 0x8 "SPI_HOST_IRQ,"
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bitfld.long 0x8 0.--2. "host_irq,HOST IRQ" "0,1,2,3,4,5,6,7"
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line.long 0xC "TPTC_DBS_CONFIG,"
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bitfld.long 0xC 8.--9. "tptc_b0,Default burst size tieoff value for TPTC_B0" "0,1,2,3"
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bitfld.long 0xC 4.--5. "tptc_a1,Default burst size tieoff value for TPTC_A1" "0,1,2,3"
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bitfld.long 0xC 0.--1. "tptc_a0,Default burst size tieoff value for TPTC_A0" "0,1,2,3"
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line.long 0x10 "TPCC_PARITY_CTRL,"
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bitfld.long 0x10 20. "tpcc_b_parity_err_clr,Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_b_parity_addr" "0,1"
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bitfld.long 0x10 16. "tpcc_a_parity_err_clr,Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr" "0,1"
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bitfld.long 0x10 12. "tpcc_b_parity_testen,parity test enable for tpcc b" "0,1"
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bitfld.long 0x10 8. "tpcc_b_parity_en,parity en for tpcc b" "0,1"
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bitfld.long 0x10 4. "tpcc_a_parity_testen,parity test enable for tpcc a" "0,1"
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bitfld.long 0x10 0. "tpcc_a_parity_en,writing 1'b1 enables parity for TPCC_A" "0,1"
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rgroup.long 0x160++0x3
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line.long 0x0 "TPCC_PARITY_STATUS,"
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hexmask.long.byte 0x0 16.--23. 1. "tpcc_b_parity_addr,address where parity error happened for tpccb"
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hexmask.long.byte 0x0 0.--7. 1. "tpcc_a_parity_addr,address where parity error happened for tpcca"
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group.long 0x164++0x47
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line.long 0x0 "MSS_DBG_ACK_CTL0,"
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bitfld.long 0x0 24.--26. "cpsw,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "dccd,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x0 16.--18. "dccc,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x0 12.--14. "dccb,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "dcca,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x0 4.--6. "cccb,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "ccca,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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line.long 0x4 "MSS_DBG_ACK_CTL1,"
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bitfld.long 0x4 24.--26. "scib,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x4 20.--22. "scia,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x4 16.--18. "i2c,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x4 12.--14. "mcrc,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x4 8.--10. "wdt,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x4 4.--6. "rti,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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bitfld.long 0x4 0.--2. "dcan,Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor" "0: Peripheral not suspended along with processor,1: Peripehal Suspended along with procesor,?,?,?,?,?,?"
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line.long 0x8 "CPSW_CONTROL,"
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bitfld.long 0x8 16. "rgmii1_id_mode,writing 1'b1 would disable the internal clock delays. And those delays need to be handled on board." "0,1"
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bitfld.long 0x8 8. "rmii_ref_clk_oe_n,To select the rmii_ref_clk from PAD or from MSS_RCM. 0: clock will be from mss_rcm through IO internal loopback 1: will be from" "0: clock will be from mss_rcm through IO internal..,1: will be from"
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bitfld.long 0x8 0.--2. "port1_mode_sel,Port 1 Interface 00 = GMII/MII 01 = RMII 10 = RGMII 11 = Not Supported" "0: GMII/MII,1: RMII,?,?,?,?,?,?"
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line.long 0xC "MSS_TPCC_A_ERRAGG_MASK,"
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bitfld.long 0xC 26. "tptc_a1_read_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 25. "tptc_a0_read_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 24. "tpcc_a_read_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 18. "tptc_a1_write_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 17. "tptc_a0_write_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 16. "tpcc_a_write_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 4. "tpcc_a_par_err,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 3. "tptc_a1_err,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 2. "tptc_a0_err,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 1. "tpcc_a_mpint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0xC 0. "tpcc_a_errint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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line.long 0x10 "MSS_TPCC_A_ERRAGG_STATUS,"
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bitfld.long 0x10 26. "tptc_a1_read_access_error,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 25. "tptc_a0_read_access_error,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 24. "tpcc_a_read_access_error,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 18. "tptc_a1_write_access_error,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 17. "tptc_a0_write_access_error,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 16. "tpcc_a_write_access_error,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 4. "tpcc_a_par_err,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 3. "tptc_a1_err,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 2. "tptc_a0_err,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 1. "tpcc_a_mpint,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x10 0. "tpcc_a_errint,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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line.long 0x14 "MSS_TPCC_A_ERRAGG_STATUS_RAW,"
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bitfld.long 0x14 26. "tptc_a1_read_access_error,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 25. "tptc_a0_read_access_error,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 24. "tpcc_a_read_access_error,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 18. "tptc_a1_write_access_error,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 17. "tptc_a0_write_access_error,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 16. "tpcc_a_write_access_error,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 4. "tpcc_a_par_err,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 3. "tptc_a1_err,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 2. "tptc_a0_err,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 1. "tpcc_a_mpint,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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bitfld.long 0x14 0. "tpcc_a_errint,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1"
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line.long 0x18 "MSS_TPCC_A_INTAGG_MASK,"
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bitfld.long 0x18 17. "tptc_a1,Mask Interrupt from TPTC A1 to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 8. "tpcc_a_int7,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 7. "tpcc_a_int6,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 6. "tpcc_a_int5,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 5. "tpcc_a_int4,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 4. "tpcc_a_int3,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 3. "tpcc_a_int2,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 2. "tpcc_a_int1,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 1. "tpcc_a_int0,Mask Interrupt from TPCC A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x18 0. "tpcc_a_intg,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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line.long 0x1C "MSS_TPCC_A_INTAGG_STATUS,"
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bitfld.long 0x1C 17. "tptc_a1,Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 16. "tptc_a0,Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 8. "tpcc_a_int7,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 7. "tpcc_a_int6,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 6. "tpcc_a_int5,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 5. "tpcc_a_int4,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 4. "tpcc_a_int3,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 3. "tpcc_a_int2,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 2. "tpcc_a_int1,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 1. "tpcc_a_int0,Status of Interrupt from TPCC A Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x1C 0. "tpcc_a_intg,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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line.long 0x20 "MSS_TPCC_A_INTAGG_STATUS_RAW,"
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bitfld.long 0x20 17. "tptc_a1,Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x20 16. "tptc_a0,Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x20 8. "tpcc_a_int7,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0x20 7. "tpcc_a_int6,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0x20 6. "tpcc_a_int5,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0x20 5. "tpcc_a_int4,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0x20 4. "tpcc_a_int3,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0x20 3. "tpcc_a_int2,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0x20 2. "tpcc_a_int1,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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bitfld.long 0x20 1. "tpcc_a_int0,Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_INTAGG_MASK" "0,1"
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bitfld.long 0x20 0. "tpcc_a_intg,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
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line.long 0x24 "MSS_TPCC_B_ERRAGG_MASK,"
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bitfld.long 0x24 25. "tptc_b0_read_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x24 24. "tpcc_b_read_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x24 17. "tptc_b0_write_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x24 16. "tpcc_b_write_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x24 4. "tpcc_b_par_err,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x24 2. "tptc_b0_err,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x24 1. "tpcc_b_mpint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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bitfld.long 0x24 0. "tpcc_b_errint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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line.long 0x28 "MSS_TPCC_B_ERRAGG_STATUS,"
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bitfld.long 0x28 25. "tptc_b0_read_access_error,Status of Error from MSS_TPTC_B0. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x28 24. "tpcc_b_read_access_error,Status of Error from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x28 17. "tptc_b0_write_access_error,Status of Error from MSS_TPTC_B0. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x28 16. "tpcc_b_write_access_error,Status of Error from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x28 4. "tpcc_b_par_err,Status of Error from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x28 2. "tptc_b0_err,Status of Error from MSS_TPTC_B0. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x28 1. "tpcc_b_mpint,Status of Error from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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bitfld.long 0x28 0. "tpcc_b_errint,Status of Error from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error." "0,1"
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line.long 0x2C "MSS_TPCC_B_ERRAGG_STATUS_RAW,"
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bitfld.long 0x2C 25. "tptc_b0_read_access_error,Raw Status of Error from MSS_TPTC_B0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x2C 24. "tpcc_b_read_access_error,Raw Status of Error from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x2C 17. "tptc_b0_write_access_error,Raw Status of Error from MSS_TPTC_B0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x2C 16. "tpcc_b_write_access_error,Raw Status of Error from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x2C 4. "tpcc_b_par_err,Raw Status of Error from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x2C 2. "tptc_b0_err,Raw Status of Error from MSS_TPTC_B0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x2C 1. "tpcc_b_mpint,Raw Status of Error from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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bitfld.long 0x2C 0. "tpcc_b_errint,Raw Status of Error from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_B_ERRAGG_MASK" "0,1"
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line.long 0x30 "MSS_TPCC_B_INTAGG_MASK,"
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bitfld.long 0x30 16. "tptc_b0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 8. "tpcc_b_int7,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 7. "tpcc_b_int6,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 6. "tpcc_b_int5,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 5. "tpcc_b_int4,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 4. "tpcc_b_int3,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 3. "tpcc_b_int2,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 2. "tpcc_b_int1,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x30 1. "tpcc_b_int0,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x30 0. "tpcc_b_intg,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
line.long 0x34 "MSS_TPCC_B_INTAGG_STATUS,"
|
|
bitfld.long 0x34 16. "tptc_b0,Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 8. "tpcc_b_int7,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "tpcc_b_int6,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 6. "tpcc_b_int5,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "tpcc_b_int4,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 4. "tpcc_b_int3,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
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|
newline
|
|
bitfld.long 0x34 3. "tpcc_b_int2,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 2. "tpcc_b_int1,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "tpcc_b_int0,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x34 0. "tpcc_b_intg,Status of Interrupt from MSS_TPCC_B. Set only if Interupt is unmasked in MSS_TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
line.long 0x38 "MSS_TPCC_B_INTAGG_STATUS_RAW,"
|
|
bitfld.long 0x38 16. "tptc_b0,Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 8. "tpcc_b_int7,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 7. "tpcc_b_int6,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 6. "tpcc_b_int5,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 5. "tpcc_b_int4,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 4. "tpcc_b_int3,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 3. "tpcc_b_int2,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 2. "tpcc_b_int1,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 1. "tpcc_b_int0,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x38 0. "tpcc_b_intg,Raw Status of Interrupt from MSS_TPCC_B. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1"
|
|
line.long 0x3C "MSS_BUS_SAFETY_CTRL,"
|
|
bitfld.long 0x3C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x40 "MSS_CR5A_AXI_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x40 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x40 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x40 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x44 "MSS_CR5A_AXI_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x44 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x44 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x44 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x44 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x44 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x44 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x44 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x44 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x1AC++0xF
|
|
line.long 0x0 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x1BC++0x7
|
|
line.long 0x0 "MSS_CR5B_AXI_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5B_AXI_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x1C4++0xF
|
|
line.long 0x0 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x1D4++0x7
|
|
line.long 0x0 "MSS_CR5A_AXI_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5A_AXI_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x1DC++0x13
|
|
line.long 0x0 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x1F0++0x7
|
|
line.long 0x0 "MSS_CR5B_AXI_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5B_AXI_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x1F8++0x13
|
|
line.long 0x0 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x20C++0x7
|
|
line.long 0x0 "MSS_CR5A_AXI_S_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5A_AXI_S_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x214++0x17
|
|
line.long 0x0 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x22C++0x7
|
|
line.long 0x0 "MSS_CR5B_AXI_S_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5B_AXI_S_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x234++0x17
|
|
line.long 0x0 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x24C++0x7
|
|
line.long 0x0 "MSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_TPTC_A0_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x254++0xF
|
|
line.long 0x0 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x264++0x7
|
|
line.long 0x0 "MSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_TPTC_A1_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x26C++0xF
|
|
line.long 0x0 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x27C++0x7
|
|
line.long 0x0 "MSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_TPTC_B0_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x284++0xF
|
|
line.long 0x0 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x294++0x7
|
|
line.long 0x0 "MSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_TPTC_A0_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x29C++0x13
|
|
line.long 0x0 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "MSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_TPTC_A1_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x2B8++0x13
|
|
line.long 0x0 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x2CC++0x7
|
|
line.long 0x0 "MSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_TPTC_B0_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x2D4++0x13
|
|
line.long 0x0 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x2E8++0x7
|
|
line.long 0x0 "HSM_TPTC_A0_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HSM_TPTC_A0_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x2F0++0xF
|
|
line.long 0x0 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "HSM_TPTC_A1_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HSM_TPTC_A1_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x308++0xF
|
|
line.long 0x0 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x318++0x7
|
|
line.long 0x0 "HSM_TPTC_A0_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HSM_TPTC_A0_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x320++0x13
|
|
line.long 0x0 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x334++0x7
|
|
line.long 0x0 "HSM_TPTC_A1_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HSM_TPTC_A1_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x33C++0x13
|
|
line.long 0x0 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x350++0x7
|
|
line.long 0x0 "MSS_QSPI_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_QSPI_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x358++0x17
|
|
line.long 0x0 "MSS_QSPI_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_QSPI_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_QSPI_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_QSPI_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x370++0x7
|
|
line.long 0x0 "HSM_DTHE_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HSM_DTHE_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x378++0x17
|
|
line.long 0x0 "HSM_DTHE_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "HSM_DTHE_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "HSM_DTHE_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "HSM_DTHE_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x390++0x7
|
|
line.long 0x0 "MSS_CPSW_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CPSW_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x398++0x17
|
|
line.long 0x0 "MSS_CPSW_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CPSW_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CPSW_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_CPSW_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x3B0++0x7
|
|
line.long 0x0 "MSS_MCRC_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_MCRC_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x3B8++0x17
|
|
line.long 0x0 "MSS_MCRC_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x3D0++0x7
|
|
line.long 0x0 "MSS_PCR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_PCR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x3D8++0x17
|
|
line.long 0x0 "MSS_PCR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x3F0++0x7
|
|
line.long 0x0 "MSS_PCR2_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_PCR2_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x3F8++0x17
|
|
line.long 0x0 "MSS_PCR2_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_PCR2_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_PCR2_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_PCR2_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x410++0x7
|
|
line.long 0x0 "HSM_M_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HSM_M_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x418++0x17
|
|
line.long 0x0 "HSM_M_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "HSM_M_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "HSM_M_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "HSM_M_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "HSM_M_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "HSM_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x430++0x7
|
|
line.long 0x0 "HSM_S_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "HSM_S_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x438++0x17
|
|
line.long 0x0 "HSM_S_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "HSM_S_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "HSM_S_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "HSM_S_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "HSM_S_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "HSM_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x450++0x7
|
|
line.long 0x0 "DAP_R232_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "DAP_R232_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x458++0x17
|
|
line.long 0x0 "DAP_R232_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "DAP_R232_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "DAP_R232_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "DAP_R232_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "DAP_R232_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "DAP_R232_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x470++0x7
|
|
line.long 0x0 "MSS_L2_A_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_L2_A_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x478++0x17
|
|
line.long 0x0 "MSS_L2_A_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_L2_A_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_L2_A_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_L2_A_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x490++0x7
|
|
line.long 0x0 "MSS_L2_B_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_L2_B_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x498++0x17
|
|
line.long 0x0 "MSS_L2_B_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_L2_B_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_L2_B_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_L2_B_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x4B0++0x7
|
|
line.long 0x0 "MSS_MBOX_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_MBOX_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x4B8++0x17
|
|
line.long 0x0 "MSS_MBOX_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x4D0++0x7
|
|
line.long 0x0 "MSS_SWBUF_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_SWBUF_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x4D8++0x17
|
|
line.long 0x0 "MSS_SWBUF_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x4F0++0x7
|
|
line.long 0x0 "MSS_GPADC_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_GPADC_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x4F8++0x1F
|
|
line.long 0x0 "MSS_GPADC_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_GPADC_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_GPADC_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_GPADC_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x18 "MSS_BUS_SAFETY_SEC_ERR_STAT0,"
|
|
bitfld.long 0x18 31. "mss_dmmslv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 30. "mss_dmm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "gpadc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 28. "mss_swbuf,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 27. "mss_mbox,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 26. "l2ram1,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "l2ram0,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "dthe,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 23. "hsm_s,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 22. "per_pcr2,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 21. "per_pcr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 20. "mcrc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "qspi,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 18. "hsm_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 17. "hsm_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "hsm_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "hsm_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 14. "mss_tptc_B1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "mss_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "mss_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "mss_tptc_B1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10. "mss_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "mss_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "cpsw,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "hsm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "dap_rs232,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "cr5b_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "cr5a_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "cr5b_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "cr5a_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "cr5b_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "cr5a_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
line.long 0x1C "MSS_BUS_SAFETY_SEC_ERR_STAT1,"
|
|
bitfld.long 0x1C 24. "mss_to_mdo,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "rcss2mss,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "mss2rcss,Bus safety single-bit-error of Node mentioned in the field" "0,1"
|
|
repeat 7. (list 0x0 0x1 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x518)++0x3
|
|
line.long 0x0 "HW_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg0,HW reserved Regsiter"
|
|
repeat.end
|
|
group.long 0x520++0x3
|
|
line.long 0x0 "PREVIOUS_NAME,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg2,HW reserved Regsiter"
|
|
group.long 0x538++0x7
|
|
line.long 0x0 "MSS_DMM_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_DMM_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x540++0x17
|
|
line.long 0x0 "MSS_DMM_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_DMM_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_DMM_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_DMM_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x558++0x7
|
|
line.long 0x0 "MSS_DMM_SLV_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_DMM_SLV_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x560++0x17
|
|
line.long 0x0 "MSS_DMM_SLV_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x578++0x7
|
|
line.long 0x0 "MSS_TO_MDO_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_TO_MDO_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x580++0x17
|
|
line.long 0x0 "MSS_TO_MDO_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x598++0x7
|
|
line.long 0x0 "MSS_SCRP_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_SCRP_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x5A0++0x17
|
|
line.long 0x0 "MSS_SCRP_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_SCRP_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_SCRP_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_SCRP_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x5B8++0x7
|
|
line.long 0x0 "MSS_CR5A_AHB_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5A_AHB_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x5C0++0x17
|
|
line.long 0x0 "MSS_CR5A_AHB_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x5D8++0x7
|
|
line.long 0x0 "MSS_CR5B_AHB_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5B_AHB_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x5E0++0x17
|
|
line.long 0x0 "MSS_CR5B_AHB_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x5F8++0x1F
|
|
line.long 0x0 "DMM_CTRL_REG,"
|
|
bitfld.long 0x0 0. "dmm_pad_select,0: SOC will be able to send the packet to DMMA/B 1: PAD will be able to send the packet to DMMA/B controlling from PAD" "0: SOC will be able to send the packet to DMMA/B 1:..,?"
|
|
line.long 0x4 "MSS_CR5A_MBOX_WRITE_DONE,"
|
|
bitfld.long 0x4 28. "proc_7,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "proc_6,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "proc_5,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "proc_4,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "proc_3,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "proc_2,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "proc_1,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "proc_0,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
|
|
line.long 0x8 "MSS_CR5A_MBOX_READ_REQ,"
|
|
bitfld.long 0x8 28. "proc_7,This is request from processor 7 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "proc_6,This is request from processor 6 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x8 20. "proc_5,This is request from processor 5 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "proc_4,This is request from processor 4 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "proc_3,This is request from processor 3 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "proc_2,This is request from processor 2 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "proc_1,This is request from processor 1 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "proc_0,This is request from processor 0 to mss_cr5a. Requesting it to read from mailbox." "0,1"
|
|
line.long 0xC "MSS_CR5A_MBOX_READ_DONE,"
|
|
bitfld.long 0xC 28. "proc_7,This register should be written once finishing reading from CR5A's mailbox written by proc 7" "0,1"
|
|
newline
|
|
bitfld.long 0xC 24. "proc_6,This register should be written once finishing reading from CR5A's mailbox written by proc 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "proc_5,This register should be written once finishing reading from CR5A's mailbox written by proc 5" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "proc_4,This register should be written once finishing reading from CR5A's mailbox written by proc 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "proc_3,This register should be written once finishing reading from CR5A's mailbox written by proc 3" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "proc_2,This register should be written once finishing reading from CR5A's mailbox written by proc 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "proc_1,This register should be written once finishing reading from CR5A's mailbox written by proc 1" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "proc_0,This register should be written once finishing reading from CR5A's mailbox written by proc 0" "0,1"
|
|
line.long 0x10 "MSS_CR5B_MBOX_WRITE_DONE,"
|
|
bitfld.long 0x10 28. "proc_7,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "proc_6,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. "proc_5,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "proc_4,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "proc_3,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "proc_2,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "proc_1,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "proc_0,Write pulse bit field: This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
|
|
line.long 0x14 "MSS_CR5B_MBOX_READ_REQ,"
|
|
bitfld.long 0x14 28. "proc_7,This is request from processor 7 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "proc_6,This is request from processor 6 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "proc_5,This is request from processor 5 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "proc_4,This is request from processor 4 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "proc_3,This is request from processor 3 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "proc_2,This is request from processor 2 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "proc_1,This is request from processor 1 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "proc_0,This is request from processor 0 to mss_CR5B. Requesting it to read from mailbox." "0,1"
|
|
line.long 0x18 "MSS_CR5B_MBOX_READ_DONE,"
|
|
bitfld.long 0x18 28. "proc_7,This register should be written once finishing reading from CR5B's mailbox written by proc 7" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "proc_6,This register should be written once finishing reading from CR5B's mailbox written by proc 6" "0,1"
|
|
newline
|
|
bitfld.long 0x18 20. "proc_5,This register should be written once finishing reading from CR5B's mailbox written by proc 5" "0,1"
|
|
newline
|
|
bitfld.long 0x18 16. "proc_4,This register should be written once finishing reading from CR5B's mailbox written by proc 4" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "proc_3,This register should be written once finishing reading from CR5B's mailbox written by proc 3" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "proc_2,This register should be written once finishing reading from CR5B's mailbox written by proc 2" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "proc_1,This register should be written once finishing reading from CR5B's mailbox written by proc 1" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "proc_0,This register should be written once finishing reading from CR5B's mailbox written by proc 0" "0,1"
|
|
line.long 0x1C "MSS_PBIST_KEY_RST,"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "pbist_st_rst,MSS PBIST controller will be brought out of reset when value is 0xA"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "pbist_st_key,Top PBIST Selftest Key. Valid value is 0x5"
|
|
repeat 3. (list 0x0 0x1 0x2)(list 0x0 0x4 0x8)
|
|
group.long ($2+0x618)++0x3
|
|
line.long 0x0 "MSS_PBIST_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "pbist_reg,"
|
|
repeat.end
|
|
group.long 0x624++0xF
|
|
line.long 0x0 "MSS_QSPI_CONFIG,"
|
|
bitfld.long 0x0 8.--10. "clk_loopback,Write 3'b111 to take board level loop back clock for QSPI" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "ext_clk,Write 3'b111 to external clock as QSPI baud clock source needed for DFT IO char." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_STC_CONTROL,"
|
|
bitfld.long 0x4 0.--2. "cr5_wfi_overide,writing 3'b111 will bypass the wfi signals from R5SS." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "MSS_CTI_TRIG_SEL,"
|
|
hexmask.long.byte 0x8 0.--7. 1. "trig8_sel,Used for selecting the trigger source for 8th trigger of MSS_CTI"
|
|
line.long 0xC "MSS_DBGSS_CTI_TRIG_SEL,"
|
|
hexmask.long.byte 0xC 16.--23. 1. "trig3,Used for selecting the trigger source for 3rd trigger of ONE_MCU_CTI"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "trig2,Used for selecting the trigger source for 2nd trigger of ONE_MCU_CTI"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "trig1,Used for selecting the trigger source for 1st trigger of ONE_MCU_CTI"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
|
|
group.long ($2+0x634)++0x3
|
|
line.long 0x0 "MSS_BOOT_INFO_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "config,Reserved Register for Software use"
|
|
repeat.end
|
|
group.long 0x654++0x8B
|
|
line.long 0x0 "MSS_TPTC_ECCAGGR_CLK_CNTRL,"
|
|
bitfld.long 0x0 2. "tptc_B0,Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)" "0: FIFO during ECC-AGGR interaction,?"
|
|
newline
|
|
bitfld.long 0x0 1. "tptc_A1,Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)" "?,1: FIFO during ECC-AGGR interaction"
|
|
newline
|
|
bitfld.long 0x0 0. "tptc_A0,Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)" "0: FIFO during ECC-AGGR interaction,?"
|
|
line.long 0x4 "MSS_PERIPH_ERRAGG_MASK0,"
|
|
bitfld.long 0x4 27. "top_mdo_wr,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 26. "top_mdo_rd,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 25. "rcss_rcm_wr,Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 24. "rcss_rcm_rd,Mask Interrupt from RSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 23. "rcss_ctrl_wr,Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 22. "rcss_ctrl_rd,Mask Interrupt from RSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0x4 21. "hwa_cfg_wr,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
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bitfld.long 0x4 20. "hwa_cfg_rd,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 19. "dss_cm4_ctrl_wr,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 18. "dss_cm4_ctrl_rd,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 17. "dss_rcm_wr,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 16. "dss_rcm_rd,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 15. "dss_ctrl_wr,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 14. "dss_ctrl_rd,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 13. "hsm_ctrl_wr,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 12. "hsm_ctrl_rd,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 11. "hsm_soc_ctrl_wr,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 10. "hsm_soc_ctrl_rd,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 9. "top_aurora_wr,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 8. "top_aurora_rd,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 7. "top_rcm_wr,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 6. "top_rcm_rd,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 5. "top_ctrl_wr,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 4. "top_ctrl_rd,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 3. "mss_rcm_wr,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 2. "mss_rcm_rd,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 1. "mss_ctrl_wr,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x4 0. "mss_ctrl_rd,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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line.long 0x8 "MSS_PERIPH_ERRAGG_STATUS0,"
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bitfld.long 0x8 27. "top_mdo_wr,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 26. "top_mdo_rd,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 25. "rcss_rcm_wr,Status of Interrupt from RSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 24. "rcss_rcm_rd,Status of Interrupt from RSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 23. "rcss_ctrl_wr,Status of Interrupt from RSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 22. "rcss_ctrl_rd,Status of Interrupt from RSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 21. "hwa_cfg_wr,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 20. "hwa_cfg_rd,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 19. "dss_cm4_ctrl_wr,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 18. "dss_cm4_ctrl_rd,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 17. "dss_rcm_wr,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 16. "dss_rcm_rd,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 15. "dss_ctrl_wr,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 14. "dss_ctrl_rd,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 13. "hsm_ctrl_wr,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 12. "hsm_ctrl_rd,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 11. "hsm_soc_ctrl_wr,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 10. "hsm_soc_ctrl_rd,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 9. "top_aurora_wr,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 8. "top_aurora_rd,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 7. "top_rcm_wr,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 6. "top_rcm_rd,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 5. "top_ctrl_wr,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 4. "top_ctrl_rd,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 3. "mss_rcm_wr,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 2. "mss_rcm_rd,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 1. "mss_ctrl_wr,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x8 0. "mss_ctrl_rd,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt." "0,1"
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line.long 0xC "MSS_PERIPH_ERRAGG_STATUS_RAW0,"
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bitfld.long 0xC 27. "top_mdo_wr,Raw Status of Interrupt from TOP_MDO. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 26. "top_mdo_rd,Raw Status of Interrupt from TOP_MDO. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 25. "rcss_rcm_wr,Raw Status of Interrupt from RSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 24. "rcss_rcm_rd,Raw Status of Interrupt from RSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 23. "rcss_ctrl_wr,Raw Status of Interrupt from RSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 22. "rcss_ctrl_rd,Raw Status of Interrupt from RSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 21. "hwa_cfg_wr,Raw Status of Interrupt from HWA_CFG. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 20. "hwa_cfg_rd,Raw Status of Interrupt from HWA_CFG. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 19. "dss_cm4_ctrl_wr,Raw Status of Interrupt from DSS_CM4_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 18. "dss_cm4_ctrl_rd,Raw Status of Interrupt from DSS_CM4_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 17. "dss_rcm_wr,Raw Status of Interrupt from DSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 16. "dss_rcm_rd,Raw Status of Interrupt from DSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 15. "dss_ctrl_wr,Raw Status of Interrupt from DSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 14. "dss_ctrl_rd,Raw Status of Interrupt from DSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 13. "hsm_ctrl_wr,Raw Status of Interrupt from HSM_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 12. "hsm_ctrl_rd,Raw Status of Interrupt from HSM_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 11. "hsm_soc_ctrl_wr,Raw Status of Interrupt from HSM_SOC_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 10. "hsm_soc_ctrl_rd,Raw Status of Interrupt from HSM_SOC_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 9. "top_aurora_wr,Raw Status of Interrupt from TOP_AURORA. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 8. "top_aurora_rd,Raw Status of Interrupt from TOP_AURORA. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 7. "top_rcm_wr,Raw Status of Interrupt from TOP_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 6. "top_rcm_rd,Raw Status of Interrupt from TOP_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 5. "top_ctrl_wr,Raw Status of Interrupt from TOP_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 4. "top_ctrl_rd,Raw Status of Interrupt from TOP_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 3. "mss_rcm_wr,Raw Status of Interrupt from MSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 2. "mss_rcm_rd,Raw Status of Interrupt from MSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 1. "mss_ctrl_wr,Raw Status of Interrupt from MSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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bitfld.long 0xC 0. "mss_ctrl_rd,Raw Status of Interrupt from MSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1"
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line.long 0x10 "MSS_PERIPH_ERRAGG_MASK1,"
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bitfld.long 0x10 16. "mpu_rd_hsm,Mask Interrupt from MPU_DSS_HSM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 15. "mpu_rd_dss_mbox,Mask Interrupt from MPU_DSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 14. "mpu_rd_dss_hwa_proc,Mask Interrupt from MPU_DSS_HWA_PROC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 13. "mpu_rd_dss_hwa_dma1,Mask Interrupt from MPU_DSS_HWA_DMA1 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 12. "mpu_rd_dss_hwa_dma0,Mask Interrupt from MPU_DSS_HWA_DMA0 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 11. "mpu_rd_dss_l3_bankd,Mask Interrupt from MPU_DSS_L3_BANKD to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 10. "mpu_rd_dss_l3_bankc,Mask Interrupt from MPU_DSS_L3_BANKC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 9. "mpu_rd_dss_l3_bankb,Mask Interrupt from MPU_DSS_L3_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 8. "mpu_rd_dss_l3_banka,Mask Interrupt from MPU_DSS_L3_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 7. "mpu_rd_mss_cr5b_axis,Mask Interrupt from MPU_MSS_CR5B_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 6. "mpu_rd_mss_cr5a_axis,Mask Interrupt from MPU_MSS_CR5A_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 5. "mpu_rd_mss_qspi,Mask Interrupt from MPU_MSS_QSPI to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 4. "mpu_rd_mss_pcra,Mask Interrupt from MPU_MSS_PCRA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 3. "mpu_rd_mss_mbox,Mask Interrupt from MPU_MSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 2. "mpu_rd_hsm_dthe,Mask Interrupt from MPU_HSM_DTHE to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 1. "mpu_rd_mss_l2_bankb,Mask Interrupt from MPU_MSS_L2_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x10 0. "mpu_rd_mss_l2_banka,Mask Interrupt from MPU_MSS_L2_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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line.long 0x14 "MSS_PERIPH_ERRAGG_STATUS1,"
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bitfld.long 0x14 16. "mpu_rd_hsm,Status of Interrupt from MPU_HSM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 15. "mpu_rd_dss_mbox,Status of Interrupt from MPU_DSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 14. "mpu_rd_dss_hwa_proc,Status of Interrupt from MPU_DSS_HWA_PROC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 13. "mpu_rd_dss_hwa_dma1,Status of Interrupt from MPU_DSS_HWA_DMA1 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 12. "mpu_rd_dss_hwa_dma0,Status of Interrupt from MPU_DSS_HWA_DMA0 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 11. "mpu_rd_dss_l3_bankd,Status of Interrupt from MPU_DSS_L3_BANKD Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 10. "mpu_rd_dss_l3_bankc,Status of Interrupt from MPU_DSS_L3_BANKC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 9. "mpu_rd_dss_l3_bankb,Status of Interrupt from MPU_DSS_L3_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 8. "mpu_rd_dss_l3_banka,Status of Interrupt from MPU_DSS_L3_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 7. "mpu_rd_mss_cr5b_axis,Status of Interrupt from MPU_MSS_CR5B_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 6. "mpu_rd_mss_cr5a_axis,Status of Interrupt from MPU_MSS_CR5A_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 5. "mpu_rd_mss_qspi,Status of Interrupt from MPU_MSS_QSPI Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 4. "mpu_rd_mss_pcra,Status of Interrupt from MPU_MSS_PCRA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 3. "mpu_rd_mss_mbox,Status of Interrupt from MPU_MSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 2. "mpu_rd_hsm_dthe,Status of Interrupt from MPU_HSM_DTHE Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 1. "mpu_rd_mss_l2_bankb,Status of Interrupt from MPU_MSS_L2_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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bitfld.long 0x14 0. "mpu_rd_mss_l2_banka,Status of Interrupt from MPU_MSS_L2_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt." "0,1"
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line.long 0x18 "MSS_PERIPH_ERRAGG_STATUS_RAW1,"
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bitfld.long 0x18 16. "mpu_rd_hsm,Raw Status of Interrupt from MPU_HSM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 15. "mpu_rd_dss_mbox,Raw Status of Interrupt from MPU_DSS_MBOX. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 14. "mpu_rd_dss_hwa_proc,Raw Status of Interrupt from MPU_DSS_HWA_PROC. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 13. "mpu_rd_dss_hwa_dma1,Raw Status of Interrupt from MPU_DSS_HWA_DMA1. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 12. "mpu_rd_dss_hwa_dma0,Raw Status of Interrupt from MPU_DSS_HWA_DMA0. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 11. "mpu_rd_dss_l3_bankd,Raw Status of Interrupt from MPU_DSS_L3_BANKD. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 10. "mpu_rd_dss_l3_bankc,Raw Status of Interrupt from MPU_DSS_L3_BANKC. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 9. "mpu_rd_dss_l3_bankb,Raw Status of Interrupt from MPU_DSS_L3_BANKB. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 8. "mpu_rd_dss_l3_banka,Raw Status of Interrupt from MPU_DSS_L3_BANKA. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 7. "mpu_rd_mss_cr5b_axis,Raw Status of Interrupt from MPU_MSS_CR5B_AXIS. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 6. "mpu_rd_mss_cr5a_axis,Raw Status of Interrupt from MPU_MSS_CR5A_AXIS. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 5. "mpu_rd_mss_qspi,Raw Status of Interrupt from MPU_MSS_QSPI. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 4. "mpu_rd_mss_pcra,Raw Status of Interrupt from MPU_MSS_PCRA. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 3. "mpu_rd_mss_mbox,Raw Status of Interrupt from MPU_MSS_MBOX. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 2. "mpu_rd_hsm_dthe,Raw Status of Interrupt from MPU_HSM_DTHE. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 1. "mpu_rd_mss_l2_bankb,Raw Status of Interrupt from MPU_MSS_L2_BANKB. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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bitfld.long 0x18 0. "mpu_rd_mss_l2_banka,Raw Status of Interrupt from MPU_MSS_L2_BANKA. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK1" "0,1"
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line.long 0x1C "MSS_DMM_EVENT0_REG,"
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bitfld.long 0x1C 28. "event_sel3,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x1C 24. "event_trig3,DMM trigger for RSS_CSI2A_EOL_CNTX1_INT" "0,1"
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bitfld.long 0x1C 20. "event_sel2,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x1C 16. "event_trig2,DMM trigger for RSS_CSI2A_EOL_CNTX0_INT" "0,1"
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bitfld.long 0x1C 12. "event_sel1,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x1C 8. "event_trig1,DMM trigger for RSS_CSI2A_SOF_INT1" "0,1"
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bitfld.long 0x1C 4. "event_sel0,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x1C 0. "event_trig0,DMM trigger for RSS_CSI2A_SOF_INT0" "0,1"
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line.long 0x20 "MSS_DMM_EVENT1_REG,"
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bitfld.long 0x20 28. "event_sel7,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x20 24. "event_trig7,DMM trigger for RSS_CSI2A_EOL_CNTX5_INT" "0,1"
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bitfld.long 0x20 20. "event_sel6,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x20 16. "event_trig6,DMM trigger for RSS_CSI2A_EOL_CNTX4_INT" "0,1"
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bitfld.long 0x20 12. "event_sel5,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x20 8. "event_trig5,DMM trigger for RSS_CSI2A_EOL_CNTX3_INT" "0,1"
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bitfld.long 0x20 4. "event_sel4,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x20 0. "event_trig4,DMM trigger for RSS_CSI2A_EOL_CNTX2_INT" "0,1"
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line.long 0x24 "MSS_DMM_EVENT2_REG,"
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bitfld.long 0x24 28. "event_sel11,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x24 24. "event_trig11,DMM trigger for RSS_ADC_CAPTURE_COMPLETE (to DMA)" "0,1"
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bitfld.long 0x24 20. "event_sel10,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x24 16. "event_trig10,DMM trigger for DFE_FRAME_START_TO_DSS" "0,1"
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bitfld.long 0x24 12. "event_sel9,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x24 8. "event_trig9,DMM trigger for RSS_CSI2A_EOL_CNTX7_INT" "0,1"
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bitfld.long 0x24 4. "event_sel8,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x24 0. "event_trig8,DMM trigger for RSS_CSI2A_EOL_CNTX6_INT" "0,1"
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line.long 0x28 "MSS_DMM_EVENT3_REG,"
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bitfld.long 0x28 28. "event_sel15,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x28 24. "event_trig15,DMM trigger for RSS_ADC_CAPTURE_COMPLETE (to interrupts)" "0,1"
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bitfld.long 0x28 20. "event_sel14,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x28 16. "event_trig14,DMM trigger for FRC_LOGICAL_FRAME_END" "0,1"
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bitfld.long 0x28 12. "event_sel13,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x28 8. "event_trig13,DMM trigger for FRC_LOGICAL_FRAME_START" "0,1"
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bitfld.long 0x28 4. "event_sel12,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x28 0. "event_trig12,DMM trigger for RSS_DATA_CAPTURE_ENABLE_FALL" "0,1"
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line.long 0x2C "MSS_DMM_EVENT4_REG,"
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bitfld.long 0x2C 28. "event_sel19,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x2C 24. "event_trig19,DMM trigger Reserved" "0,1"
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bitfld.long 0x2C 20. "event_sel18,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x2C 16. "event_trig18,DMM trigger Reserved" "0,1"
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bitfld.long 0x2C 12. "event_sel17,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x2C 8. "event_trig17,DMM trigger Reserved" "0,1"
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bitfld.long 0x2C 4. "event_sel16,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x2C 0. "event_trig16,DMM trigger for ADC_CLK_ENABLE_VALID" "0,1"
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line.long 0x30 "MSS_DMM_EVENT5_REG,"
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bitfld.long 0x30 28. "event_sel23,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x30 24. "event_trig23,DMM trigger Reserved" "0,1"
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bitfld.long 0x30 20. "event_sel22,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x30 16. "event_trig22,DMM trigger Reserved" "0,1"
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bitfld.long 0x30 12. "event_sel21,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x30 8. "event_trig21,DMM trigger Reserved" "0,1"
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bitfld.long 0x30 4. "event_sel20,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x30 0. "event_trig20,DMM trigger Reserved" "0,1"
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line.long 0x34 "MSS_DMM_EVENT6_REG,"
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bitfld.long 0x34 28. "event_sel27,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x34 24. "event_trig27,DMM trigger Reserved" "0,1"
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bitfld.long 0x34 20. "event_sel26,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x34 16. "event_trig26,DMM trigger Reserved" "0,1"
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bitfld.long 0x34 12. "event_sel25,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x34 8. "event_trig25,DMM trigger Reserved" "0,1"
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bitfld.long 0x34 4. "event_sel24,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x34 0. "event_trig24,DMM trigger Reserved" "0,1"
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line.long 0x38 "MSS_DMM_EVENT7_REG,"
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bitfld.long 0x38 28. "event_sel31,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x38 24. "event_trig31,DMM trigger for DSS_HWA_THREAD1_PARAM_DONE" "0,1"
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bitfld.long 0x38 20. "event_sel30,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x38 16. "event_trig30,DMM trigger for DSS_HWA_THREAD1_LOOP" "0,1"
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bitfld.long 0x38 12. "event_sel29,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x38 8. "event_trig29,DMM trigger Reserved" "0,1"
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bitfld.long 0x38 4. "event_sel28,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x38 0. "event_trig28,DMM trigger Reserved" "0,1"
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line.long 0x3C "MSS_DMM_EVENT8_REG,"
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bitfld.long 0x3C 28. "event_sel35,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x3C 24. "event_trig35,DMM trigger Reserved" "0,1"
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bitfld.long 0x3C 20. "event_sel34,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x3C 16. "event_trig34,DMM trigger for DSS_HWA_LOCAL_RAM_ERR" "0,1"
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bitfld.long 0x3C 12. "event_sel33,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x3C 8. "event_trig33,DMM trigger for DSS_HWA_THREAD2_PARAM_DONE" "0,1"
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bitfld.long 0x3C 4. "event_sel32,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x3C 0. "event_trig32,DMM trigger for DSS_HWA_THREAD2_LOOP" "0,1"
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line.long 0x40 "MSS_DMM_EVENT9_REG,"
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bitfld.long 0x40 28. "event_sel39,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x40 24. "event_trig39,DMM trigger Reserved" "0,1"
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bitfld.long 0x40 20. "event_sel38,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x40 16. "event_trig38,DMM trigger Reserved" "0,1"
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bitfld.long 0x40 12. "event_sel37,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x40 8. "event_trig37,DMM trigger Reserved" "0,1"
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bitfld.long 0x40 4. "event_sel36,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x40 0. "event_trig36,DMM trigger Reserved" "0,1"
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line.long 0x44 "MSS_DMM_EVENT10_REG,"
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bitfld.long 0x44 28. "event_sel43,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x44 24. "event_trig43,DMM trigger Reserved" "0,1"
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bitfld.long 0x44 20. "event_sel42,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x44 16. "event_trig42,DMM trigger Reserved" "0,1"
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bitfld.long 0x44 12. "event_sel41,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x44 8. "event_trig41,DMM trigger Reserved" "0,1"
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bitfld.long 0x44 4. "event_sel40,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x44 0. "event_trig40,DMM trigger Reserved" "0,1"
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line.long 0x48 "MSS_DMM_EVENT11_REG,"
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bitfld.long 0x48 28. "event_sel47,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x48 24. "event_trig47,DMM trigger For MSS_MCANA_FE_INT source 2" "0,1"
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bitfld.long 0x48 20. "event_sel46,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x48 16. "event_trig46,DMM trigger For MSS_MCANA_FE_INT source 1" "0,1"
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bitfld.long 0x48 12. "event_sel45,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x48 8. "event_trig45,DMM trigger For MSS_MCANA_FE_INT source 0" "0,1"
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bitfld.long 0x48 4. "event_sel44,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x48 0. "event_trig44,DMM trigger Reserved" "0,1"
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line.long 0x4C "MSS_DMM_EVENT12_REG,"
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bitfld.long 0x4C 28. "event_sel51,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x4C 24. "event_trig51,DMM trigger For MSS_MCANA_FE_INT source 1" "0,1"
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bitfld.long 0x4C 20. "event_sel50,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x4C 16. "event_trig50,DMM trigger For MSS_MCANA_FE_INT source 0" "0,1"
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bitfld.long 0x4C 12. "event_sel49,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x4C 8. "event_trig49,DMM trigger For MSS_MCANA_INT1" "0,1"
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bitfld.long 0x4C 4. "event_sel48,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x4C 0. "event_trig48,DMM trigger For MSS_MCANA_INT0" "0,1"
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line.long 0x50 "MSS_DMM_EVENT13_REG,"
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bitfld.long 0x50 28. "event_sel55,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x50 24. "event_trig55,DMM trigger Reserved" "0,1"
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bitfld.long 0x50 20. "event_sel54,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x50 16. "event_trig54,DMM trigger For MSS_MCANB_INT1" "0,1"
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bitfld.long 0x50 12. "event_sel53,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x50 8. "event_trig53,DMM trigger For MSS_MCANB_INT0" "0,1"
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bitfld.long 0x50 4. "event_sel52,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x50 0. "event_trig52,DMM trigger For MSS_MCANA_FE_INT source 2" "0,1"
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line.long 0x54 "MSS_DMM_EVENT14_REG,"
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bitfld.long 0x54 28. "event_sel59,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x54 24. "event_trig59,DMM trigger Reserved" "0,1"
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bitfld.long 0x54 20. "event_sel58,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x54 16. "event_trig58,DMM trigger Reserved" "0,1"
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bitfld.long 0x54 12. "event_sel57,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x54 8. "event_trig57,DMM trigger Reserved" "0,1"
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bitfld.long 0x54 4. "event_sel56,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x54 0. "event_trig56,DMM trigger Reserved" "0,1"
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line.long 0x58 "MSS_DMM_EVENT15_REG,"
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bitfld.long 0x58 28. "event_sel63,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x58 24. "event_trig63,DMM trigger Reserved" "0,1"
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bitfld.long 0x58 20. "event_sel62,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x58 16. "event_trig62,DMM trigger Reserved" "0,1"
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bitfld.long 0x58 12. "event_sel61,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x58 8. "event_trig61,DMM trigger Reserved" "0,1"
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bitfld.long 0x58 4. "event_sel60,Writing 1'b1 : Selects DMM event_trig as interrupt source. 1'b0 : Selects actual interrupt as interrupt source." "0: Selects actual interrupt as interrupt source,1: Selects DMM event_trig as interrupt source"
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bitfld.long 0x58 0. "event_trig60,DMM trigger Reserved" "0,1"
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line.long 0x5C "MSS_TPTC_BOUNDARY_CFG,"
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hexmask.long.byte 0x5C 16.--21. 1. "tptc_b0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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hexmask.long.byte 0x5C 8.--13. 1. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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hexmask.long.byte 0x5C 0.--5. 1. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB"
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line.long 0x60 "MSS_TPTC_XID_REORDER_CFG,"
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bitfld.long 0x60 16. "tptc_b0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_B0" "0,1"
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bitfld.long 0x60 8. "tptc_a1_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A1" "0,1"
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bitfld.long 0x60 0. "tptc_a0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A0" "0,1"
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line.long 0x64 "GPADC_CTRL,"
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hexmask.long.byte 0x64 8.--12. 1. "gpadc_trigin_sel,Writing below decimal values to this regiter will select corresponding interrupt as GPADC trigger source. 0: GPIO_0 1: GPIO_1 2: GPIO_2 3: GPIO_3 4: RSS_CSI2A_EOL_INT 5: RSS_CSI2A_SOF_INT0 6: RSS_CSI2A_SOF_INT1 7: RSS_CSI2A_SOF_INT 8:.."
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bitfld.long 0x64 0. "gpadc_sw_trig,Writing 1'b1 will give MMR based SW trigger to GPADC" "0,1"
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line.long 0x68 "HW_Sync_FE_CTRL,"
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bitfld.long 0x68 8. "fe2_sel,Writing 1'b0 : Selects MCANA filter event as HW_Sync_FE2 1'b1 : Selects MCANB filter event as HW_Sync_FE2" "0: Selects MCANA filter event as HW_Sync_FE2 1'b1 :..,?"
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bitfld.long 0x68 0. "fe1_sel,Writing 1'b0 : Selects MCANA filter event as HW_Sync_FE1 1'b1 : Selects MCANB filter event as HW_Sync_FE1" "0: Selects MCANA filter event as HW_Sync_FE1 1'b1 :..,?"
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line.long 0x6C "DEBUGSS_CSETB_FLUSH,"
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rbitfld.long 0x6C 10. "CSETB_FULL,When HIGH indicates that the ETB RAM has overflowed or wrapped around to address zero" "0,1"
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rbitfld.long 0x6C 9. "CSETB_ACQ_COMPLETE,When HIGH indicates that trace acquisition is complete by ETB that is the trigger counter is at zero" "0,1"
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rbitfld.long 0x6C 8. "CSETB_FLUSHINACK,Return acknowledgement to CSETBFLUSHIN" "0,1"
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bitfld.long 0x6C 0. "CSETB_FLUSHIN,External control used to assert the ATB signal AFVALIDS and drain any historical FIFO information on the bus" "0,1"
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line.long 0x70 "ANALOG_WU_STATUS_REG_POLARITY_INV,"
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hexmask.long 0x70 0.--31. 1. "inv_ctrl,This register decides the polarity of each status bit before providing to the MSS_ESM. Each bit controls the respective status bit."
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line.long 0x74 "ANALOG_CLK_STATUS_REG_POLARITY_INV,"
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hexmask.long 0x74 0.--31. 1. "inv_ctrl,This register decides the polarity of each status bit before providing to the MSS_ESM. Each bit controls the respective status bit."
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line.long 0x78 "ANALOG_WU_STATUS_REG_GRP1_MASK,"
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hexmask.long 0x78 0.--31. 1. "mask,Writing 1'b1 : Masks the corresponding status bit before generating a group 1 ESM error. 1'b0 : Unmasks the corresponding status bit before generating a group 1 ESM error."
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line.long 0x7C "ANALOG_CLK_STATUS_REG_GRP1_MASK,"
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hexmask.long 0x7C 0.--31. 1. "mask,Writing 1'b1 : Masks the corresponding status bit before generating a group 1 ESM error. 1'b0 : Unmasks the corresponding status bit before generating a group 1 ESM error."
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line.long 0x80 "ANALOG_WU_STATUS_REG_GRP2_MASK,"
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hexmask.long 0x80 0.--31. 1. "mask,Writing 1'b1 : Masks the corresponding status bit before generating a group 2 ESM error. 1'b0 : Unmasks the corresponding status bit before generating a group 2 ESM error."
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line.long 0x84 "ANALOG_CLK_STATUS_REG_GRP2_MASK,"
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hexmask.long 0x84 0.--31. 1. "mask,Writing 1'b1 : Masks the corresponding status bit before generating a group 2 ESM error. 1'b0 : Unmasks the corresponding status bit before generating a group 2 ESM error."
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line.long 0x88 "NERROR_MASK,"
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bitfld.long 0x88 0.--2. "mask,writing 3'b111 will mask the Nerror propagation to pad Writing 3'b000 will unmask the Nerror propagation to pad" "0,1,2,3,4,5,6,7"
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group.long 0x720++0x3
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line.long 0x0 "MSS_DMM_ACCESS_MODE,"
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bitfld.long 0x0 4. "dmmb_sel,writing 1'b0 : ensures all the accesses from DMMB are user-mode writing 1'b1 : ensures all the accesses from DMMB are privilege mode" "0: ensures all the accesses from DMMB are user-mode..,?"
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bitfld.long 0x0 0. "dmma_sel,writing 1'b0 : ensures all the accesses from DMMA are user-mode writing 1'b1 : ensures all the accesses from DMMA are privilege mode" "0: ensures all the accesses from DMMA are user-mode..,?"
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group.long 0x800++0xF
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line.long 0x0 "R5_CONTROL,"
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bitfld.long 0x0 24.--26. "rom_wait_state,writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access. This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. (because it is a timing issue in this scenario)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 16.--18. "reset_fsm_trigger,Write pulse bit field: writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "lock_step_switch_wait,writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "lock_step,writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if R5_CONTROL_lock_step_switch_wait is set. Or else the switiching to Dual-core happens on the fly." "0,1,2,3,4,5,6,7"
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line.long 0x4 "R5_ROM_ECLIPSE,"
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bitfld.long 0x4 8.--10. "memswap_wait,writing 3'b111 ensures ROM-Eclipsing happens only after R5SS reset. Orelse it will be a immediate change." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "memswap,writing '111' ensures eclipsing of CR5A_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after R5SS reset assertion." "0,1,2,3,4,5,6,7"
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line.long 0x8 "R5_COREA_HALT,"
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bitfld.long 0x8 0.--2. "halt,writing '000' will unhalt CR5A. This register should be written only once." "0,1,2,3,4,5,6,7"
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line.long 0xC "R5_COREB_HALT,"
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bitfld.long 0xC 0.--2. "halt,writing '000' will unhalt for CR5B. This register should be written only once." "0,1,2,3,4,5,6,7"
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rgroup.long 0x810++0x3
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line.long 0x0 "R5_STATUS_REG,"
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bitfld.long 0x0 8. "lock_step,Reading 1: confirms R5SS is in lockstep mode. Reading 0: confirms R5SS is in Dual-core mode." "0: confirms R5SS is in Dual-core mode,1: confirms R5SS is in lockstep mode"
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bitfld.long 0x0 0. "memswap,reading 1: confirms ROM is Eclipsed from with RAM for R5." "?,1: confirms ROM is Eclipsed from with RAM for R5"
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group.long 0xFD0++0x3
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line.long 0x0 "HW_SPARE_RW0,"
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hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,[2:0] writing 3'b111 gates the clock to redundant-safe bridges and inteconnects [6:4] writing 3'b111 disables the safety on async bridge [31:7] Reserved for HW R&D"
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repeat 3. (list 0x1 0x2 0x3)(list 0x0 0x4 0x8)
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group.long ($2+0xFD4)++0x3
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line.long 0x0 "HW_SPARE_RW$1,"
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hexmask.long 0x0 0.--31. 1. "hw_spare_rw1,Reserved for HW R&D"
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repeat.end
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repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
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rgroup.long ($2+0xFE0)++0x3
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line.long 0x0 "HW_SPARE_RO$1,"
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hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
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repeat.end
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group.long 0xFF0++0x7
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line.long 0x0 "HW_SPARE_WPH,"
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hexmask.long 0x0 0.--31. 1. "proc,Write pulse bit field: For bits 0 to 7: Wrting 1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5A. For bits 8 to 15: Wrting 1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5B."
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line.long 0x4 "HW_SPARE_REC,"
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bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
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|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MSS_DCCA"
|
|
base ad:0x2F79C00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters clears the error signal"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DCCREV,Module version"
|
|
bitfld.long 0x0 30.--31. "SCHEME,SCHEME. - (RO )" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "NU1,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional release number - (RO )"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number - (RO )"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number. - (RO )"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU3,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU4,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU5,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"
|
|
line.long 0xC "DCCSTAT,Contains the error & done flag bit"
|
|
hexmask.long 0xC 2.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU7,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU8,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU9,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSSRC1,Clock source1 selection control"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x0 4.--11. 1. "NU10,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Refer to Design document section: 11.4.2 DCC"
|
|
line.long 0x4 "DCCCLKSSRC0,Clock source0 selection control"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU13,Reserved"
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x4 4.--11. 1. "NU12,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Refer to Design document section: 11.4.2 DCC"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DCCGCTRL2,Global control register 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "NU13,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FIFO_NONERR,FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_READ,FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CONT_ON_ERR,Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue.."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "DCCSTATUS2,FIFO status register"
|
|
hexmask.long 0x0 6.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full." "0: Count1 FIFO is not Full,1: Count1 FIFO is Full"
|
|
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full." "0: Valid0 FIFO is not Full,1: Valid0 FIFO is Full"
|
|
newline
|
|
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full." "0: Count0 FIFO is not Full,1: Count0 FIFO is Full"
|
|
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
|
|
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DCCERRCNT,Error count register"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU15,Reserved"
|
|
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
|
|
tree.end
|
|
tree "MSS_DCCB"
|
|
base ad:0x2F79D00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters clears the error signal"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DCCREV,Module version"
|
|
bitfld.long 0x0 30.--31. "SCHEME,SCHEME. - (RO )" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "NU1,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional release number - (RO )"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number - (RO )"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number. - (RO )"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU3,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU4,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU5,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"
|
|
line.long 0xC "DCCSTAT,Contains the error & done flag bit"
|
|
hexmask.long 0xC 2.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU7,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU8,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU9,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSSRC1,Clock source1 selection control"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x0 4.--11. 1. "NU10,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Refer to Design document section: 11.4.2 DCC"
|
|
line.long 0x4 "DCCCLKSSRC0,Clock source0 selection control"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU13,Reserved"
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x4 4.--11. 1. "NU12,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Refer to Design document section: 11.4.2 DCC"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DCCGCTRL2,Global control register 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "NU13,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FIFO_NONERR,FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_READ,FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CONT_ON_ERR,Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue.."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "DCCSTATUS2,FIFO status register"
|
|
hexmask.long 0x0 6.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full." "0: Count1 FIFO is not Full,1: Count1 FIFO is Full"
|
|
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full." "0: Valid0 FIFO is not Full,1: Valid0 FIFO is Full"
|
|
newline
|
|
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full." "0: Count0 FIFO is not Full,1: Count0 FIFO is Full"
|
|
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
|
|
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DCCERRCNT,Error count register"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU15,Reserved"
|
|
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
|
|
tree.end
|
|
tree "MSS_DCCC"
|
|
base ad:0x2F79E00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters clears the error signal"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DCCREV,Module version"
|
|
bitfld.long 0x0 30.--31. "SCHEME,SCHEME. - (RO )" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "NU1,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional release number - (RO )"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number - (RO )"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number. - (RO )"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU3,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU4,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU5,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"
|
|
line.long 0xC "DCCSTAT,Contains the error & done flag bit"
|
|
hexmask.long 0xC 2.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU7,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU8,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU9,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSSRC1,Clock source1 selection control"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x0 4.--11. 1. "NU10,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Refer to Design document section: 11.4.2 DCC"
|
|
line.long 0x4 "DCCCLKSSRC0,Clock source0 selection control"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU13,Reserved"
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x4 4.--11. 1. "NU12,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Refer to Design document section: 11.4.2 DCC"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DCCGCTRL2,Global control register 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "NU13,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FIFO_NONERR,FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_READ,FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CONT_ON_ERR,Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue.."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "DCCSTATUS2,FIFO status register"
|
|
hexmask.long 0x0 6.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full." "0: Count1 FIFO is not Full,1: Count1 FIFO is Full"
|
|
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full." "0: Valid0 FIFO is not Full,1: Valid0 FIFO is Full"
|
|
newline
|
|
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full." "0: Count0 FIFO is not Full,1: Count0 FIFO is Full"
|
|
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
|
|
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DCCERRCNT,Error count register"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU15,Reserved"
|
|
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
|
|
tree.end
|
|
tree "MSS_DCCD"
|
|
base ad:0x2F79F00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DCCGCTRL,Starts / stops the counters clears the error signal"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "DCCREV,Module version"
|
|
bitfld.long 0x0 30.--31. "SCHEME,SCHEME. - (RO )" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "NU1,Reserved" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Functional release number - (RO )"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,Design Release Number - (RO )"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number. - (RO )"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU3,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)"
|
|
line.long 0x4 "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU4,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
|
|
line.long 0x8 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU5,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1"
|
|
line.long 0xC "DCCSTAT,Contains the error & done flag bit"
|
|
hexmask.long 0xC 2.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "DCCCNT0,Value of the counter attached to clock source 0"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU7,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )"
|
|
line.long 0x4 "DCCVALID0,Value of the valid counter attached to clock source 0"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU8,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )"
|
|
line.long 0x8 "DCCCNT1,Value of the counter attached to clock source 1"
|
|
hexmask.long.word 0x8 20.--31. 1. "NU9,Reserved"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "DCCCLKSSRC1,Clock source1 selection control"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x0 4.--11. 1. "NU10,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Refer to Design document section: 11.4.2 DCC"
|
|
line.long 0x4 "DCCCLKSSRC0,Clock source0 selection control"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU13,Reserved"
|
|
hexmask.long.byte 0x4 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)"
|
|
hexmask.long.byte 0x4 4.--11. 1. "NU12,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Refer to Design document section: 11.4.2 DCC"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DCCGCTRL2,Global control register 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "NU13,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FIFO_NONERR,FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "FIFO_READ,FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CONT_ON_ERR,Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue.."
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "DCCSTATUS2,FIFO status register"
|
|
hexmask.long 0x0 6.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 5. "COUNT1_FIFO_FULL,Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full." "0: Count1 FIFO is not Full,1: Count1 FIFO is Full"
|
|
bitfld.long 0x0 4. "VALID0_FIFO_FULL,Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full." "0: Valid0 FIFO is not Full,1: Valid0 FIFO is Full"
|
|
newline
|
|
bitfld.long 0x0 3. "COUNT0_FIFO_FULL,Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full." "0: Count0 FIFO is not Full,1: Count0 FIFO is Full"
|
|
bitfld.long 0x0 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty." "0: Count1 FIFO is not empty,1: Count1 FIFO is empty"
|
|
bitfld.long 0x0 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty." "0: Valid0 FIFO is not empty,1: Valid0 FIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty." "0: Count0 FIFO is not empty,1: Count0 FIFO is empty"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "DCCERRCNT,Error count register"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU15,Reserved"
|
|
hexmask.long.word 0x0 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it."
|
|
tree.end
|
|
tree "MSS_DMM_A"
|
|
base ad:0x3F79C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "GLBCTRL,Sets the global configuration of the module"
|
|
hexmask.long.byte 0x0 25.--31. 1. "Reserved4,Reserved"
|
|
bitfld.long 0x0 24. "BUSY,BUSY User and privilege mode (read): 0 = the DMM does not currently receive data and has no data in its internal buffers which need to be transfered. 1 = the module is currently receiving data or has data in its internal buffers Privilege mode.." "0: the DMM does not currently receive data and has..,1: the module is currently receiving data"
|
|
newline
|
|
hexmask.long.byte 0x0 19.--23. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 18. "CONTCLK,CONTCLK. Continous RTPCLK output User and privilege mode (read): 0 = RTPCLK will be suspended between two packets 1 = free running RTPCLK Privilege mode (write): 0 = suspend RTPCLK between packets 1 = enable free running clock between packets" "0: suspend RTPCLK between packets,1: enable free running clock between packets"
|
|
newline
|
|
bitfld.long 0x0 17. "COS,COS. Continue On Suspend Influences behaviour of module while in suspend mode. In all cases the corresponding interrupt will be set. User and privilege mode (read): 0 = before entering suspend mode the ongoing reception (if started 1 HCLK cycle.." "0: disable data reception while in suspend mode,1: enable data reception while in suspend mode"
|
|
bitfld.long 0x0 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself. It has to be cleared by writing to it. User and privilege mode (read): 0 = no reset of DMM module 1 = reset of DMM module Privilege mode.." "0: no reset of DMM module,1: reset DMM module to its reset state"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "Reserved2,Reserved"
|
|
bitfld.long 0x0 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit.." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode. User and privilege mode (read): 0 = the DMM module assumes packets in Trace Mode definition 1 = the DMM module assumes packets in Direct.." "0: enable Trace Mode,1: enable Direct Data Mode"
|
|
hexmask.long.byte 0x0 4.--7. 1. "Reserved1,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ONOFF,ON/OFF User and privilege mode (read): 1010 = the DMM module receives data and writes it to the buffer all other = the DMM module does not receive data Privilege mode (write): 1010 = enable receive/write operations. Packets will be received 1 HCLK.."
|
|
line.long 0x4 "INTSET ,Enables interrupts"
|
|
hexmask.long.word 0x4 18.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x4 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: enable interrupt"
|
|
newline
|
|
bitfld.long 0x4 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: enable interrupt"
|
|
bitfld.long 0x4 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
|
|
newline
|
|
bitfld.long 0x4 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
|
|
bitfld.long 0x4 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
|
|
newline
|
|
bitfld.long 0x4 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
|
|
bitfld.long 0x4 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
|
|
newline
|
|
bitfld.long 0x4 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
|
|
bitfld.long 0x4 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
|
|
newline
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bitfld.long 0x4 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be generated on BMM HRESP = Error Privilege mode (write): 0 = no influence on bit 1 = enable interrupt when BMM HRESP =.." "0: no influence on bit,1: enable interrupt when BMM HRESP = Error"
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newline
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bitfld.long 0x4 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition. Either the number of bits received on a Trace Mode packet doesn't correspond to the size specified in the SIZE field or the.." "0: no influence on bit,1: enable interrupt"
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line.long 0x8 "INTCLR,Disables interrupts"
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hexmask.long.word 0x8 18.--31. 1. "Reserved,Reserved"
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bitfld.long 0x8 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be generated on BMM HRESP = Error Privilege mode (write): 0 = no influence on bit 1 = disable interrupt on BMM HRESP = Error" "0: no influence on bit,1: disable interrupt on BMM HRESP = Error"
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bitfld.long 0x8 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer.. User and privilege mode (read): 0 = no interrupt will be generated 1 =.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition. Either the number of bits received on a Trace Mode packet doesn't correspond to the size specified in the SIZE field or.." "0: no influence on bit,1: disable interrupt"
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line.long 0xC "INTLVL,Selects high or low priority interrupt level"
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hexmask.long.word 0xC 18.--31. 1. "Reserved,Reserved"
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bitfld.long 0xC 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to level 1" "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to level 1" "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to level 1" "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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line.long 0x10 "INTFLAG,Interrupt Flags"
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hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
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bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occurred 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error. User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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newline
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bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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rgroup.long 0x14++0x7
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line.long 0x0 "OFF1,Interrupt offset for high priority level"
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hexmask.long 0x0 5.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x0 0.--4. 1. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010.."
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line.long 0x4 "OFF2,Interrupt offset for low priority level"
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hexmask.long 0x4 5.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x4 0.--4. 1. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010.."
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group.long 0x1C++0x7
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line.long 0x0 "DDMDEST,Configuration of Buffer for Direct Data Mode"
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hexmask.long 0x0 0.--31. 1. "STARTADDR,STARTADDR[31:0] These bits define the starting address of the buffer. The starting address has to be a multiple of the blocksize chosen in DMMDDMBL. User and privilege mode (read): current start address Privilege mode (write): sets start.."
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line.long 0x4 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
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hexmask.long 0x4 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x4 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current start address Privilege mode (write): BLOCKSIZE[3:0] Region.."
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rgroup.long 0x24++0x3
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line.long 0x0 "DDMPT,Pointer to the last written entry in the buffer"
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hexmask.long.tbyte 0x0 15.--31. 1. "Reserved,Reserved"
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hexmask.long.word 0x0 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer. The pointer points to the byte aligned address. If in 16-bit DDM mode bit 0 will be discarded. If in 32-bit DDM mode bit 0 and 1 will be discarded. User and.."
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group.long 0x28++0x17
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line.long 0x0 "INTPT,Programmable Interrupt Pointer"
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hexmask.long.tbyte 0x0 15.--31. 1. "Reserved,Reserved"
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hexmask.long.word 0x0 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated. User and privilege mode (read): current interrupt pointer Privilege mode (write): new.."
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line.long 0x4 "DEST0REG1,Defines Region 1 for Destination 0"
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hexmask.long.word 0x4 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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hexmask.long.tbyte 0x4 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST0BL1. User and privilege mode (read): current start address Privilege mode.."
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line.long 0x8 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
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hexmask.long 0x8 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x8 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
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line.long 0xC "DEST0REG2,Defines Region 2 for Destination 0"
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hexmask.long.word 0xC 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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hexmask.long.tbyte 0xC 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST0BL2. User and privilege mode (read): current start address Privilege mode.."
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line.long 0x10 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
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hexmask.long 0x10 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x10 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region.."
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line.long 0x14 "DEST1REG1,Defines Region 1 for Destination1"
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hexmask.long.word 0x14 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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|
hexmask.long.tbyte 0x14 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST1BL1. User and privilege mode (read): current start address Privilege mode.."
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|
repeat 2. (list 0x1 0x2)(list 0x0 0x8)
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|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "DEST1BL$1,Defines the blocksize for the buffer for Destination 1 Region 1"
|
|
hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
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|
repeat.end
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DEST1REG2,Defines Region 2 for Destination 1"
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|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST1BL2. User and privilege mode (read): current start address Privilege mode.."
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|
group.long 0x4C++0x3
|
|
line.long 0x0 "DEST2REG1,Defines Region 1 for Destination 2"
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|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST2BL1. User and privilege mode (read): current start address Privilege mode.."
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|
repeat 2. (list 0x1 0x2)(list 0x0 0x8)
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|
group.long ($2+0x50)++0x3
|
|
line.long 0x0 "DEST2BL$1,Defines the blocksize for the buffer for Destination 2 Region 1"
|
|
hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
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|
repeat.end
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DEST2REG2,Defines Region 2 for Destination 2"
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|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST2BL2. User and privilege mode (read): current start address Privilege mode.."
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|
group.long 0x5C++0x3
|
|
line.long 0x0 "DEST3REG1,Defines Region 1 for Destination 3"
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|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST3BL1. User and privilege mode (read): current start address Privilege mode.."
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|
repeat 2. (list 0x1 0x2)(list 0x0 0x8)
|
|
group.long ($2+0x60)++0x3
|
|
line.long 0x0 "DEST3BL$1,Defines the blocksize for the buffer for Destination 3 Region 1"
|
|
hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
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|
repeat.end
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "DEST3REG2,Defines Region 2 for Destination 3"
|
|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST3BL2. User and privilege mode (read): current start address Privilege mode.."
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|
group.long 0x6C++0x23
|
|
line.long 0x0 "DMMPC0,Defines functional or GIO mode of pins"
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|
hexmask.long.word 0x0 19.--31. 1. "Reserved,Reserved"
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|
bitfld.long 0x0 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in Functional mode Privilege mode (write): 0 = Pin is.." "0: Pin is used in GIO mode,1: Pin is used in Functional mode"
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|
newline
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hexmask.long.word 0x0 2.--17. 1. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in FunctionaPrivilege mode (write): 0 = Pin is.."
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bitfld.long 0x0 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in Functional mode Privilege mode (write): 0 = Pin is.." "0: Pin is used in GIO mode,1: Pin is used in Functional mode"
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|
newline
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bitfld.long 0x0 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in Functional mode Privilege mode (write): 0 = Pin.." "0: Pin is used in GIO mode,1: Pin is used in Functional mode"
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|
line.long 0x4 "DMMPC1,Defines direction of pins"
|
|
hexmask.long.word 0x4 19.--31. 1. "Reserved,Reserved"
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|
bitfld.long 0x4 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 = Pin is.." "0: Pin is set to input,1: Pin is set to output"
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|
newline
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hexmask.long.word 0x4 2.--17. 1. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 =.."
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bitfld.long 0x4 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 = Pin is.." "0: Pin is set to input,1: Pin is set to output"
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|
newline
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bitfld.long 0x4 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 = Pin.." "0: Pin is set to input,1: Pin is set to output"
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|
line.long 0x8 "DMMPC2,Input level of pins"
|
|
hexmask.long.word 0x8 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x8 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this bit have.." "0: Logic low,1: Logic high"
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|
newline
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hexmask.long.word 0x8 2.--17. 1. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this.."
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|
bitfld.long 0x8 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this bit have.." "0: Logic low,1: Logic high"
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|
newline
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|
bitfld.long 0x8 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this bit.." "0: Logic low,1: Logic high"
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|
line.long 0xC "DMMPC3,Sets pins to high or low"
|
|
hexmask.long.word 0xC 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0xC 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0 = Logic.." "0: Logic low,1: Logic high"
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|
newline
|
|
hexmask.long.word 0xC 2.--17. 1. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0.."
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|
bitfld.long 0xC 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0 = Logic.." "0: Logic low,1: Logic high"
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|
newline
|
|
bitfld.long 0xC 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0 =.." "0: Logic low,1: Logic high"
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|
line.long 0x10 "DMMPC4,Sets pins to high"
|
|
hexmask.long.word 0x10 19.--31. 1. "Reserved,Reserved"
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|
bitfld.long 0x10 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL or.." "0: leaves the pin unchanged,1: Sets the pin to Logic high"
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|
newline
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hexmask.long.word 0x10 2.--17. 1. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output.."
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bitfld.long 0x10 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL or.." "0: leaves the pin unchanged,1: Sets the pin to Logic high"
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|
newline
|
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bitfld.long 0x10 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL.." "0: leaves the pin unchanged,1: Sets the pin to Logic high"
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|
line.long 0x14 "DMMPC5,Sets pins to low"
|
|
hexmask.long.word 0x14 19.--31. 1. "Reserved,Reserved"
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|
bitfld.long 0x14 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL.." "0: leaves the pin unchanged,1: clears the pin to logic low"
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|
newline
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hexmask.long.word 0x14 2.--17. 1. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output.."
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bitfld.long 0x14 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL.." "0: leaves the pin unchanged,1: clears the pin to logic low"
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newline
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bitfld.long 0x14 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output voltage is.." "0: leaves the pin unchanged,1: clears the pin to logic low"
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|
line.long 0x18 "DMMPC6,Configures open drain functionality of pin"
|
|
hexmask.long.word 0x18 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x18 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege mode.." "0: configures pin as push/pull,1: configures pin as open drain"
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|
newline
|
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hexmask.long.word 0x18 2.--17. 1. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege.."
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|
bitfld.long 0x18 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege mode.." "0: configures pin as push/pull,1: configures pin as open drain"
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|
newline
|
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bitfld.long 0x18 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege.." "0: configures pin as push/pull,1: configures pin as open drain"
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|
line.long 0x1C "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
|
|
hexmask.long.word 0x1C 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x1C 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.." "0: enables pullup/pulldown functionality,1: disables pullup/pulldown functionality"
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|
newline
|
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hexmask.long.word 0x1C 2.--17. 1. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.."
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|
bitfld.long 0x1C 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.." "0: enables pullup/pulldown functionality,1: disables pullup/pulldown functionality"
|
|
newline
|
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bitfld.long 0x1C 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.." "0: enables pullup/pulldown functionality,1: disables pullup/pulldown functionality"
|
|
line.long 0x20 "DMMPC8,Enables pullup or pulldown structure of pin"
|
|
hexmask.long.word 0x20 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x20 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1 =.." "0: enables pulldown functionality,1: enables pullup functionality"
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newline
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hexmask.long.word 0x20 2.--17. 1. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1.."
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bitfld.long 0x20 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1 =.." "0: enables pulldown functionality,1: enables pullup functionality"
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|
newline
|
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bitfld.long 0x20 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1 =.." "0: enables pulldown functionality,1: enables pullup functionality"
|
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tree.end
|
|
tree "MSS_DMM_B"
|
|
base ad:0x3F79E00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "GLBCTRL,Sets the global configuration of the module"
|
|
hexmask.long.byte 0x0 25.--31. 1. "Reserved4,Reserved"
|
|
bitfld.long 0x0 24. "BUSY,BUSY User and privilege mode (read): 0 = the DMM does not currently receive data and has no data in its internal buffers which need to be transfered. 1 = the module is currently receiving data or has data in its internal buffers Privilege mode.." "0: the DMM does not currently receive data and has..,1: the module is currently receiving data"
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|
newline
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hexmask.long.byte 0x0 19.--23. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 18. "CONTCLK,CONTCLK. Continous RTPCLK output User and privilege mode (read): 0 = RTPCLK will be suspended between two packets 1 = free running RTPCLK Privilege mode (write): 0 = suspend RTPCLK between packets 1 = enable free running clock between packets" "0: suspend RTPCLK between packets,1: enable free running clock between packets"
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|
newline
|
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bitfld.long 0x0 17. "COS,COS. Continue On Suspend Influences behaviour of module while in suspend mode. In all cases the corresponding interrupt will be set. User and privilege mode (read): 0 = before entering suspend mode the ongoing reception (if started 1 HCLK cycle.." "0: disable data reception while in suspend mode,1: enable data reception while in suspend mode"
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|
bitfld.long 0x0 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself. It has to be cleared by writing to it. User and privilege mode (read): 0 = no reset of DMM module 1 = reset of DMM module Privilege mode.." "0: no reset of DMM module,1: reset DMM module to its reset state"
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newline
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hexmask.long.byte 0x0 11.--15. 1. "Reserved2,Reserved"
|
|
bitfld.long 0x0 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit.." "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode. User and privilege mode (read): 0 = the DMM module assumes packets in Trace Mode definition 1 = the DMM module assumes packets in Direct.." "0: enable Trace Mode,1: enable Direct Data Mode"
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|
hexmask.long.byte 0x0 4.--7. 1. "Reserved1,Reserved"
|
|
newline
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hexmask.long.byte 0x0 0.--3. 1. "ONOFF,ON/OFF User and privilege mode (read): 1010 = the DMM module receives data and writes it to the buffer all other = the DMM module does not receive data Privilege mode (write): 1010 = enable receive/write operations. Packets will be received 1 HCLK.."
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|
line.long 0x4 "INTSET ,Enables interrupts"
|
|
hexmask.long.word 0x4 18.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x4 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: enable interrupt"
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|
newline
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bitfld.long 0x4 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: enable interrupt"
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|
bitfld.long 0x4 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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newline
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bitfld.long 0x4 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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|
bitfld.long 0x4 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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newline
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bitfld.long 0x4 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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|
bitfld.long 0x4 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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|
newline
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bitfld.long 0x4 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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|
bitfld.long 0x4 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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|
newline
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bitfld.long 0x4 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be generated on BMM HRESP = Error Privilege mode (write): 0 = no influence on bit 1 = enable interrupt when BMM HRESP =.." "0: no influence on bit,1: enable interrupt when BMM HRESP = Error"
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bitfld.long 0x4 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2. If both blocksizes are programmed to.." "0: no influence on bit,1: enable interrupt"
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bitfld.long 0x4 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition. Either the number of bits received on a Trace Mode packet doesn't correspond to the size specified in the SIZE field or the.." "0: no influence on bit,1: enable interrupt"
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line.long 0x8 "INTCLR,Disables interrupts"
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hexmask.long.word 0x8 18.--31. 1. "Reserved,Reserved"
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bitfld.long 0x8 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1. User and privilege mode (read): 0 = no interrupt will be generated 1 = an.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be generated on BMM HRESP = Error Privilege mode (write): 0 = no influence on bit 1 = disable interrupt on BMM HRESP = Error" "0: no influence on bit,1: disable interrupt on BMM HRESP = Error"
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bitfld.long 0x8 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer.. User and privilege mode (read): 0 = no interrupt will be generated 1 =.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet. User and privilege mode (read): 0 = no interrupt will be generated 1 = an interrupt will be.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2. If both blocksizes are programmed.." "0: no influence on bit,1: disable interrupt"
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bitfld.long 0x8 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition. Either the number of bits received on a Trace Mode packet doesn't correspond to the size specified in the SIZE field or.." "0: no influence on bit,1: disable interrupt"
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line.long 0xC "INTLVL,Selects high or low priority interrupt level"
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hexmask.long.word 0xC 18.--31. 1. "Reserved,Reserved"
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bitfld.long 0xC 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to level 1" "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to level 1" "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to level 1" "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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bitfld.long 0xC 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read): 0 = interrupt mapped to level 0 1 = interrupt mapped to level 1 Privilege mode (write): 0 = interrupt will be mapped to level 0 1 = interrupt will be mapped to.." "0: interrupt will be mapped to level 0,1: interrupt will be mapped to level 1"
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line.long 0x10 "INTFLAG,Interrupt Flags"
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hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
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bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read): 0 = no interrupt occurred 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error. User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read): 0 = no interrupt occured 1 = interrupt occured Privilege mode (write): 0 = no influence on bit 1 = bit will be cleared" "0: no influence on bit,1: bit will be cleared"
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rgroup.long 0x14++0x7
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line.long 0x0 "OFF1,Interrupt offset for high priority level"
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hexmask.long 0x0 5.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x0 0.--4. 1. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010.."
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line.long 0x4 "OFF2,Interrupt offset for low priority level"
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hexmask.long 0x4 5.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x4 0.--4. 1. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010.."
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group.long 0x1C++0x7
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line.long 0x0 "DDMDEST,Configuration of Buffer for Direct Data Mode"
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hexmask.long 0x0 0.--31. 1. "STARTADDR,STARTADDR[31:0] These bits define the starting address of the buffer. The starting address has to be a multiple of the blocksize chosen in DMMDDMBL. User and privilege mode (read): current start address Privilege mode (write): sets start.."
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line.long 0x4 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
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hexmask.long 0x4 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x4 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current start address Privilege mode (write): BLOCKSIZE[3:0] Region.."
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rgroup.long 0x24++0x3
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line.long 0x0 "DDMPT,Pointer to the last written entry in the buffer"
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hexmask.long.tbyte 0x0 15.--31. 1. "Reserved,Reserved"
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hexmask.long.word 0x0 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer. The pointer points to the byte aligned address. If in 16-bit DDM mode bit 0 will be discarded. If in 32-bit DDM mode bit 0 and 1 will be discarded. User and.."
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group.long 0x28++0x17
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line.long 0x0 "INTPT,Programmable Interrupt Pointer"
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hexmask.long.tbyte 0x0 15.--31. 1. "Reserved,Reserved"
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hexmask.long.word 0x0 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated. User and privilege mode (read): current interrupt pointer Privilege mode (write): new.."
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line.long 0x4 "DEST0REG1,Defines Region 1 for Destination 0"
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hexmask.long.word 0x4 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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hexmask.long.tbyte 0x4 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST0BL1. User and privilege mode (read): current start address Privilege mode.."
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line.long 0x8 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
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hexmask.long 0x8 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x8 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
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line.long 0xC "DEST0REG2,Defines Region 2 for Destination 0"
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hexmask.long.word 0xC 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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hexmask.long.tbyte 0xC 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST0BL2. User and privilege mode (read): current start address Privilege mode.."
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line.long 0x10 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
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hexmask.long 0x10 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x10 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region.."
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line.long 0x14 "DEST1REG1,Defines Region 1 for Destination1"
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hexmask.long.word 0x14 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
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hexmask.long.tbyte 0x14 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST1BL1. User and privilege mode (read): current start address Privilege mode.."
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|
repeat 2. (list 0x1 0x2)(list 0x0 0x8)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "DEST1BL$1,Defines the blocksize for the buffer for Destination 1 Region 1"
|
|
hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
|
|
repeat.end
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DEST1REG2,Defines Region 2 for Destination 1"
|
|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST1BL2. User and privilege mode (read): current start address Privilege mode.."
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "DEST2REG1,Defines Region 1 for Destination 2"
|
|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST2BL1. User and privilege mode (read): current start address Privilege mode.."
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x8)
|
|
group.long ($2+0x50)++0x3
|
|
line.long 0x0 "DEST2BL$1,Defines the blocksize for the buffer for Destination 2 Region 1"
|
|
hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
|
|
repeat.end
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "DEST2REG2,Defines Region 2 for Destination 2"
|
|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST2BL2. User and privilege mode (read): current start address Privilege mode.."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "DEST3REG1,Defines Region 1 for Destination 3"
|
|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST3BL1. User and privilege mode (read): current start address Privilege mode.."
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x8)
|
|
group.long ($2+0x60)++0x3
|
|
line.long 0x0 "DEST3BL$1,Defines the blocksize for the buffer for Destination 3 Region 1"
|
|
hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
|
|
hexmask.long.byte 0x0 0.--3. 1. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region. If all bits are 0 the region is disabled and no data will be stored. User and privilege mode (read): current block size Privilege mode (write): BLOCKSIZE[3:0] Region Size.."
|
|
repeat.end
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "DEST3REG2,Defines Region 2 for Destination 3"
|
|
hexmask.long.word 0x0 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located. User and privilege mode (read): current start address Privilege mode (write): sets base address to value written"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page. The starting address has to be a multiple of the blocksize chosen in DMMDEST3BL2. User and privilege mode (read): current start address Privilege mode.."
|
|
group.long 0x6C++0x23
|
|
line.long 0x0 "DMMPC0,Defines functional or GIO mode of pins"
|
|
hexmask.long.word 0x0 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x0 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in Functional mode Privilege mode (write): 0 = Pin is.." "0: Pin is used in GIO mode,1: Pin is used in Functional mode"
|
|
newline
|
|
hexmask.long.word 0x0 2.--17. 1. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in FunctionaPrivilege mode (write): 0 = Pin is.."
|
|
bitfld.long 0x0 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in Functional mode Privilege mode (write): 0 = Pin is.." "0: Pin is used in GIO mode,1: Pin is used in Functional mode"
|
|
newline
|
|
bitfld.long 0x0 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read): 0 = Pin is used in GIO mode 1 = Pin is used in Functional mode Privilege mode (write): 0 = Pin.." "0: Pin is used in GIO mode,1: Pin is used in Functional mode"
|
|
line.long 0x4 "DMMPC1,Defines direction of pins"
|
|
hexmask.long.word 0x4 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x4 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 = Pin is.." "0: Pin is set to input,1: Pin is set to output"
|
|
newline
|
|
hexmask.long.word 0x4 2.--17. 1. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 =.."
|
|
bitfld.long 0x4 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 = Pin is.." "0: Pin is set to input,1: Pin is set to output"
|
|
newline
|
|
bitfld.long 0x4 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read): 0 = Pin is used as input 1 = Pin is used as output Privilege mode (write): 0 = Pin is set to input 1 = Pin.." "0: Pin is set to input,1: Pin is set to output"
|
|
line.long 0x8 "DMMPC2,Input level of pins"
|
|
hexmask.long.word 0x8 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x8 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this bit have.." "0: Logic low,1: Logic high"
|
|
newline
|
|
hexmask.long.word 0x8 2.--17. 1. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this.."
|
|
bitfld.long 0x8 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this bit have.." "0: Logic low,1: Logic high"
|
|
newline
|
|
bitfld.long 0x8 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read): 0 = Logic low (input voltage is VIL or lower) 1 = Logic high (input voltage is VIH or higher) Privilege mode (write): Writes to this bit.." "0: Logic low,1: Logic high"
|
|
line.long 0xC "DMMPC3,Sets pins to high or low"
|
|
hexmask.long.word 0xC 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0xC 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0 = Logic.." "0: Logic low,1: Logic high"
|
|
newline
|
|
hexmask.long.word 0xC 2.--17. 1. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0.."
|
|
bitfld.long 0xC 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0 = Logic.." "0: Logic low,1: Logic high"
|
|
newline
|
|
bitfld.long 0xC 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read): 0 = Logic low (output voltage is VOL or lower) 1 = Logic high (output voltage is VOH or higher) Privilege mode (write): 0 =.." "0: Logic low,1: Logic high"
|
|
line.long 0x10 "DMMPC4,Sets pins to high"
|
|
hexmask.long.word 0x10 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x10 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL or.." "0: leaves the pin unchanged,1: Sets the pin to Logic high"
|
|
newline
|
|
hexmask.long.word 0x10 2.--17. 1. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output.."
|
|
bitfld.long 0x10 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL or.." "0: leaves the pin unchanged,1: Sets the pin to Logic high"
|
|
newline
|
|
bitfld.long 0x10 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL.." "0: leaves the pin unchanged,1: Sets the pin to Logic high"
|
|
line.long 0x14 "DMMPC5,Sets pins to low"
|
|
hexmask.long.word 0x14 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x14 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL.." "0: leaves the pin unchanged,1: clears the pin to logic low"
|
|
newline
|
|
hexmask.long.word 0x14 2.--17. 1. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output.."
|
|
bitfld.long 0x14 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output voltage is VOL.." "0: leaves the pin unchanged,1: clears the pin to logic low"
|
|
newline
|
|
bitfld.long 0x14 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read): 0 = Logic low (output voltage is.." "0: leaves the pin unchanged,1: clears the pin to logic low"
|
|
line.long 0x18 "DMMPC6,Configures open drain functionality of pin"
|
|
hexmask.long.word 0x18 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x18 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege mode.." "0: configures pin as push/pull,1: configures pin as open drain"
|
|
newline
|
|
hexmask.long.word 0x18 2.--17. 1. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege.."
|
|
bitfld.long 0x18 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege mode.." "0: configures pin as push/pull,1: configures pin as open drain"
|
|
newline
|
|
bitfld.long 0x18 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1). If pin is configured as functional pin (DMMPC0.x=1) the open drain functionality is disabled. User and privilege.." "0: configures pin as push/pull,1: configures pin as open drain"
|
|
line.long 0x1C "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
|
|
hexmask.long.word 0x1C 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x1C 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.." "0: enables pullup/pulldown functionality,1: disables pullup/pulldown functionality"
|
|
newline
|
|
hexmask.long.word 0x1C 2.--17. 1. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.."
|
|
bitfld.long 0x1C 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.." "0: enables pullup/pulldown functionality,1: disables pullup/pulldown functionality"
|
|
newline
|
|
bitfld.long 0x1C 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0). User and privilege mode (read): 0 = pullup/pulldown functionality enabled 1 = pullup/pulldown functionality disabled.." "0: enables pullup/pulldown functionality,1: disables pullup/pulldown functionality"
|
|
line.long 0x20 "DMMPC8,Enables pullup or pulldown structure of pin"
|
|
hexmask.long.word 0x20 19.--31. 1. "Reserved,Reserved"
|
|
bitfld.long 0x20 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1 =.." "0: enables pulldown functionality,1: enables pullup functionality"
|
|
newline
|
|
hexmask.long.word 0x20 2.--17. 1. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1.."
|
|
bitfld.long 0x20 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1 =.." "0: enables pulldown functionality,1: enables pullup functionality"
|
|
newline
|
|
bitfld.long 0x20 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0. User and privilege mode (read): 0 = pulldown functionality enabled 1 = pullup functionality enabled Privilege mode (write): 0 = enables pulldown functionality 1 =.." "0: enables pulldown functionality,1: enables pullup functionality"
|
|
tree.end
|
|
tree "MSS_ECC_AGG_MSS"
|
|
base ad:0x2F7C000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "rev,Revision parameters"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "module_id,Module ID"
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "custom,Custom version" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor version"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "vector,ECC Vector Register"
|
|
rbitfld.long 0x0 24. "rd_svbus_done,Status to indicate if read on serial VBUS is complete" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "rd_svbus_address,Read address"
|
|
bitfld.long 0x0 15. "rd_svbus,Write 1 to trigger a read on the serial VBUS" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "ecc_vector,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "stat,Misc Status"
|
|
hexmask.long.word 0x0 0.--10. 1. "num_rams,Indicates the number of RAMS serviced by the ECC aggregator"
|
|
line.long 0x4 "wrap_rev,Revision parameters"
|
|
bitfld.long 0x4 30.--31. "scheme,Scheme" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x4 16.--27. 1. "module_id,Module ID"
|
|
hexmask.long.byte 0x4 11.--15. 1. "revrtl,RTL version"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "custom,Custom version" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--5. 1. "revmin,Minor version"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "ctrl,ECC Control Register"
|
|
bitfld.long 0x0 8. "check_svbus_timeout,check for svbus timeout errors" "0,1"
|
|
bitfld.long 0x0 7. "check_parity,check for parity errors" "0,1"
|
|
bitfld.long 0x0 6. "error_once,Force Error only once" "0,1"
|
|
bitfld.long 0x0 5. "force_n_row,Force Error on any RAM read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "force_ded,Force Double Bit Error" "0,1"
|
|
bitfld.long 0x0 3. "force_sec,Force Single Bit Error" "0,1"
|
|
bitfld.long 0x0 2. "enable_rmw,Enable rmw" "0,1"
|
|
bitfld.long 0x0 1. "ecc_check,Enable ECC check" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ecc_enable,Enable ECC" "0,1"
|
|
line.long 0x4 "err_ctrl1,ECC Error Control1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "ecc_row,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
|
|
line.long 0x8 "err_ctrl2,ECC Error Control2 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ecc_bit2,Data bit that needs to be flipped if double bit error needs to be forced"
|
|
hexmask.long.word 0x8 0.--15. 1. "ecc_bit1,Data bit that needs to be flipped when force_sec is set"
|
|
line.long 0xC "err_stat1,ECC Error Status1 Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ecc_bit1,Data bit that corresponds to the single-bit error"
|
|
bitfld.long 0xC 15. "clr_ctrl_reg_err,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
|
|
bitfld.long 0xC 13.--14. "clr_ctrl_reg_err,Clear parity Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 12. "clr_ecc_other,Clear other Error Status" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "clr_ecc_ded,Clear Double Bit Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "clr_ecc_sec,Clear Single Bit Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 7. "ctr_reg_err,control register error pending Level interrupt" "0,1"
|
|
bitfld.long 0xC 5.--6. "parity_err,Level parity error Error Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "ecc_other,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
|
|
bitfld.long 0xC 2.--3. "ecc_ded,Level Double Bit Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "ecc_sec,Level Single Bit Error Status" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "err_stat2,ECC Error Status2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ecc_row,Row address where the single or double-bit error has occurred"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "err_stat3,ECC Error Status3 Register"
|
|
bitfld.long 0x0 9. "clr_svbus_timeout_err,Clear svbus timeout Error Status" "0,1"
|
|
bitfld.long 0x0 1. "svbus_timeout_err,Level svbus timeout error Error Status" "0,1"
|
|
rbitfld.long 0x0 0. "wb_pend,delayed write back pending Status" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "sec_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
|
|
line.long 0x4 "sec_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 7. "tptc_b0_pend,Interrupt Pending Status for tptc_b0_pend" "0,1"
|
|
bitfld.long 0x4 6. "tptc_a1_pend,Interrupt Pending Status for tptc_a1_pend" "0,1"
|
|
bitfld.long 0x4 5. "tptc_a0_pend,Interrupt Pending Status for tptc_a0_pend" "0,1"
|
|
bitfld.long 0x4 4. "gpadc_pend,Interrupt Pending Status for gpadc_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "mss_retram_pend,Interrupt Pending Status for mss_retram_pend" "0,1"
|
|
bitfld.long 0x4 2. "mss_mbox_pend,Interrupt Pending Status for mss_mbox_pend" "0,1"
|
|
bitfld.long 0x4 1. "mss_l2slv1_pend,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
|
|
bitfld.long 0x4 0. "mss_l2slv0_pend,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 7. "tptc_b0_enable_set,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 6. "tptc_a1_enable_set,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 5. "tptc_a0_enable_set,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 4. "gpadc_enable_set,Interrupt Enable Set Register for gpadc_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "mss_retram_enable_set,Interrupt Enable Set Register for mss_retram_pend" "0,1"
|
|
bitfld.long 0x0 2. "mss_mbox_enable_set,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
|
|
bitfld.long 0x0 1. "mss_l2slv1_enable_set,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
|
|
bitfld.long 0x0 0. "mss_l2slv0_enable_set,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 7. "tptc_b0_enable_clr,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 6. "tptc_a1_enable_clr,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 5. "tptc_a0_enable_clr,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 4. "gpadc_enable_clr,Interrupt Enable Clear Register for gpadc_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "mss_retram_enable_clr,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
|
|
bitfld.long 0x0 2. "mss_mbox_enable_clr,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
|
|
bitfld.long 0x0 1. "mss_l2slv1_enable_clr,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
|
|
bitfld.long 0x0 0. "mss_l2slv0_enable_clr,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
|
|
group.long 0x13C++0x7
|
|
line.long 0x0 "ded_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
|
|
line.long 0x4 "ded_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 7. "tptc_b0_pend,Interrupt Pending Status for tptc_b0_pend" "0,1"
|
|
bitfld.long 0x4 6. "tptc_a1_pend,Interrupt Pending Status for tptc_a1_pend" "0,1"
|
|
bitfld.long 0x4 5. "tptc_a0_pend,Interrupt Pending Status for tptc_a0_pend" "0,1"
|
|
bitfld.long 0x4 4. "gpadc_pend,Interrupt Pending Status for gpadc_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "mss_retram_pend,Interrupt Pending Status for mss_retram_pend" "0,1"
|
|
bitfld.long 0x4 2. "mss_mbox_pend,Interrupt Pending Status for mss_mbox_pend" "0,1"
|
|
bitfld.long 0x4 1. "mss_l2slv1_pend,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
|
|
bitfld.long 0x4 0. "mss_l2slv0_pend,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 7. "tptc_b0_enable_set,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 6. "tptc_a1_enable_set,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 5. "tptc_a0_enable_set,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 4. "gpadc_enable_set,Interrupt Enable Set Register for gpadc_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "mss_retram_enable_set,Interrupt Enable Set Register for mss_retram_pend" "0,1"
|
|
bitfld.long 0x0 2. "mss_mbox_enable_set,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
|
|
bitfld.long 0x0 1. "mss_l2slv1_enable_set,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
|
|
bitfld.long 0x0 0. "mss_l2slv0_enable_set,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 7. "tptc_b0_enable_clr,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
|
|
bitfld.long 0x0 6. "tptc_a1_enable_clr,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
|
|
bitfld.long 0x0 5. "tptc_a0_enable_clr,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
|
|
bitfld.long 0x0 4. "gpadc_enable_clr,Interrupt Enable Clear Register for gpadc_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "mss_retram_enable_clr,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
|
|
bitfld.long 0x0 2. "mss_mbox_enable_clr,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
|
|
bitfld.long 0x0 1. "mss_l2slv1_enable_clr,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
|
|
bitfld.long 0x0 0. "mss_l2slv0_enable_clr,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "aggr_enable_set,AGGR interrupt enable set Register"
|
|
bitfld.long 0x0 1. "timeout,interrupt enable set for svbus timeout errors" "0,1"
|
|
bitfld.long 0x0 0. "parity,interrupt enable set for parity errors" "0,1"
|
|
line.long 0x4 "aggr_enable_clr,AGGR interrupt enable clear Register"
|
|
bitfld.long 0x4 1. "timeout,interrupt enable clear for svbus timeout errors" "0,1"
|
|
bitfld.long 0x4 0. "parity,interrupt enable clear for parity errors" "0,1"
|
|
line.long 0x8 "aggr_status_set,AGGR interrupt status set Register"
|
|
bitfld.long 0x8 2.--3. "timeout,interrupt status set for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "parity,interrupt status set for parity errors" "0,1,2,3"
|
|
line.long 0xC "aggr_status_clr,AGGR interrupt status clear Register"
|
|
bitfld.long 0xC 2.--3. "timeout,interrupt status clear for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "parity,interrupt status clear for parity errors" "0,1,2,3"
|
|
tree.end
|
|
tree "MSS_ECC_AGG_R5A"
|
|
base ad:0x2F7B800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "rev,Revision parameters"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "module_id,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL version"
|
|
bitfld.long 0x0 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "custom,Custom version" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor version"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "vector,ECC Vector Register"
|
|
rbitfld.long 0x0 24. "rd_svbus_done,Status to indicate if read on serial VBUS is complete" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "rd_svbus_address,Read address"
|
|
bitfld.long 0x0 15. "rd_svbus,Write 1 to trigger a read on the serial VBUS" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ecc_vector,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "stat,Misc Status"
|
|
hexmask.long.word 0x0 0.--10. 1. "num_rams,Indicates the number of RAMS serviced by the ECC aggregator"
|
|
line.long 0x4 "wrap_rev,Revision parameters"
|
|
bitfld.long 0x4 30.--31. "scheme,Scheme" "0,1,2,3"
|
|
bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x4 16.--27. 1. "module_id,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x4 11.--15. 1. "revrtl,RTL version"
|
|
bitfld.long 0x4 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "custom,Custom version" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "revmin,Minor version"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "ctrl,ECC Control Register"
|
|
bitfld.long 0x0 8. "check_svbus_timeout,check for svbus timeout errors" "0,1"
|
|
bitfld.long 0x0 7. "check_parity,check for parity errors" "0,1"
|
|
bitfld.long 0x0 6. "error_once,Force Error only once" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "force_n_row,Force Error on any RAM read" "0,1"
|
|
bitfld.long 0x0 4. "force_ded,Force Double Bit Error" "0,1"
|
|
bitfld.long 0x0 3. "force_sec,Force Single Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "enable_rmw,Enable rmw" "0,1"
|
|
bitfld.long 0x0 1. "ecc_check,Enable ECC check" "0,1"
|
|
bitfld.long 0x0 0. "ecc_enable,Enable ECC" "0,1"
|
|
line.long 0x4 "err_ctrl1,ECC Error Control1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "ecc_row,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
|
|
line.long 0x8 "err_ctrl2,ECC Error Control2 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ecc_bit2,Data bit that needs to be flipped if double bit error needs to be forced"
|
|
hexmask.long.word 0x8 0.--15. 1. "ecc_bit1,Data bit that needs to be flipped when force_sec is set"
|
|
line.long 0xC "err_stat1,ECC Error Status1 Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ecc_bit1,Data bit that corresponds to the single-bit error"
|
|
bitfld.long 0xC 15. "clr_ctrl_reg_err,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
|
|
bitfld.long 0xC 13.--14. "clr_ctrl_reg_err,Clear parity Error Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 12. "clr_ecc_other,Clear other Error Status" "0,1"
|
|
bitfld.long 0xC 10.--11. "clr_ecc_ded,Clear Double Bit Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "clr_ecc_sec,Clear Single Bit Error Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 7. "ctr_reg_err,control register error pending Level interrupt" "0,1"
|
|
bitfld.long 0xC 5.--6. "parity_err,Level parity error Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 4. "ecc_other,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "ecc_ded,Level Double Bit Error Status" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "ecc_sec,Level Single Bit Error Status" "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "err_stat2,ECC Error Status2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ecc_row,Row address where the single or double-bit error has occurred"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "err_stat3,ECC Error Status3 Register"
|
|
bitfld.long 0x0 9. "clr_svbus_timeout_err,Clear svbus timeout Error Status" "0,1"
|
|
bitfld.long 0x0 1. "svbus_timeout_err,Level svbus timeout error Error Status" "0,1"
|
|
rbitfld.long 0x0 0. "wb_pend,delayed write back pending Status" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "sec_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
|
|
line.long 0x4 "sec_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 27. "cpu0_ks_vim_ramecc_pend,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
|
|
bitfld.long 0x4 26. "b1tcm0_bank1_pend,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x4 25. "b1tcm0_bank0_pend,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "b0tcm0_bank1_pend,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x4 23. "b0tcm0_bank0_pend,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x4 22. "atcm0_bank1_pend,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "atcm0_bank0_pend,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x4 20. "cpu0_ddata_ram7_pend,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x4 19. "cpu0_ddata_ram6_pend,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "cpu0_ddata_ram5_pend,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x4 17. "cpu0_ddata_ram4_pend,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x4 16. "cpu0_ddata_ram3_pend,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "cpu0_ddata_ram2_pend,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x4 14. "cpu0_ddata_ram1_pend,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x4 13. "cpu0_ddata_ram0_pend,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "cpu0_ddirty_ram_pend,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x4 11. "cpu0_dtag_ram3_pend,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x4 10. "cpu0_dtag_ram2_pend,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "cpu0_dtag_ram1_pend,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x4 8. "cpu0_dtag_ram0_pend,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x4 7. "cpu0_idata_bank3_pend,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "cpu0_idata_bank2_pend,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x4 5. "cpu0_idata_bank1_pend,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x4 4. "cpu0_idata_bank0_pend,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "cpu0_itag_ram3_pend,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x4 2. "cpu0_itag_ram2_pend,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x4 1. "cpu0_itag_ram1_pend,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "cpu0_itag_ram0_pend,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 27. "cpu0_ks_vim_ramecc_enable_set,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
|
|
bitfld.long 0x0 26. "b1tcm0_bank1_enable_set,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 25. "b1tcm0_bank0_enable_set,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "b0tcm0_bank1_enable_set,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 23. "b0tcm0_bank0_enable_set,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 22. "atcm0_bank1_enable_set,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "atcm0_bank0_enable_set,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 20. "cpu0_ddata_ram7_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x0 19. "cpu0_ddata_ram6_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "cpu0_ddata_ram5_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x0 17. "cpu0_ddata_ram4_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x0 16. "cpu0_ddata_ram3_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "cpu0_ddata_ram2_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x0 14. "cpu0_ddata_ram1_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x0 13. "cpu0_ddata_ram0_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "cpu0_ddirty_ram_enable_set,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x0 11. "cpu0_dtag_ram3_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 10. "cpu0_dtag_ram2_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "cpu0_dtag_ram1_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x0 8. "cpu0_dtag_ram0_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x0 7. "cpu0_idata_bank3_enable_set,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
|
|
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|
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bitfld.long 0x0 6. "cpu0_idata_bank2_enable_set,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x0 5. "cpu0_idata_bank1_enable_set,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x0 4. "cpu0_idata_bank0_enable_set,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "cpu0_itag_ram3_enable_set,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "cpu0_itag_ram2_enable_set,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
|
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bitfld.long 0x0 1. "cpu0_itag_ram1_enable_set,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "cpu0_itag_ram0_enable_set,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 27. "cpu0_ks_vim_ramecc_enable_clr,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
|
|
bitfld.long 0x0 26. "b1tcm0_bank1_enable_clr,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 25. "b1tcm0_bank0_enable_clr,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "b0tcm0_bank1_enable_clr,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 23. "b0tcm0_bank0_enable_clr,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 22. "atcm0_bank1_enable_clr,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "atcm0_bank0_enable_clr,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 20. "cpu0_ddata_ram7_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x0 19. "cpu0_ddata_ram6_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "cpu0_ddata_ram5_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x0 17. "cpu0_ddata_ram4_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x0 16. "cpu0_ddata_ram3_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "cpu0_ddata_ram2_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x0 14. "cpu0_ddata_ram1_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x0 13. "cpu0_ddata_ram0_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
|
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newline
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bitfld.long 0x0 12. "cpu0_ddirty_ram_enable_clr,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
|
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bitfld.long 0x0 11. "cpu0_dtag_ram3_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
|
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bitfld.long 0x0 10. "cpu0_dtag_ram2_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
|
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newline
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bitfld.long 0x0 9. "cpu0_dtag_ram1_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
|
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bitfld.long 0x0 8. "cpu0_dtag_ram0_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
|
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bitfld.long 0x0 7. "cpu0_idata_bank3_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
|
|
newline
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bitfld.long 0x0 6. "cpu0_idata_bank2_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x0 5. "cpu0_idata_bank1_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x0 4. "cpu0_idata_bank0_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "cpu0_itag_ram3_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "cpu0_itag_ram2_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x0 1. "cpu0_itag_ram1_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "cpu0_itag_ram0_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
|
|
group.long 0x13C++0x7
|
|
line.long 0x0 "ded_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
|
|
line.long 0x4 "ded_status_reg0,Interrupt Status Register 0"
|
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bitfld.long 0x4 27. "cpu0_ks_vim_ramecc_pend,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
|
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bitfld.long 0x4 26. "b1tcm0_bank1_pend,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
|
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bitfld.long 0x4 25. "b1tcm0_bank0_pend,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
|
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|
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bitfld.long 0x4 24. "b0tcm0_bank1_pend,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x4 23. "b0tcm0_bank0_pend,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
|
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bitfld.long 0x4 22. "atcm0_bank1_pend,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 21. "atcm0_bank0_pend,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x4 20. "cpu0_ddata_ram7_pend,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x4 19. "cpu0_ddata_ram6_pend,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
|
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newline
|
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bitfld.long 0x4 18. "cpu0_ddata_ram5_pend,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x4 17. "cpu0_ddata_ram4_pend,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x4 16. "cpu0_ddata_ram3_pend,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 15. "cpu0_ddata_ram2_pend,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x4 14. "cpu0_ddata_ram1_pend,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x4 13. "cpu0_ddata_ram0_pend,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 12. "cpu0_ddirty_ram_pend,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x4 11. "cpu0_dtag_ram3_pend,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x4 10. "cpu0_dtag_ram2_pend,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "cpu0_dtag_ram1_pend,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x4 8. "cpu0_dtag_ram0_pend,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x4 7. "cpu0_idata_bank3_pend,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "cpu0_idata_bank2_pend,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x4 5. "cpu0_idata_bank1_pend,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x4 4. "cpu0_idata_bank0_pend,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "cpu0_itag_ram3_pend,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x4 2. "cpu0_itag_ram2_pend,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x4 1. "cpu0_itag_ram1_pend,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "cpu0_itag_ram0_pend,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 27. "cpu0_ks_vim_ramecc_enable_set,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
|
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bitfld.long 0x0 26. "b1tcm0_bank1_enable_set,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 25. "b1tcm0_bank0_enable_set,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "b0tcm0_bank1_enable_set,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 23. "b0tcm0_bank0_enable_set,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 22. "atcm0_bank1_enable_set,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "atcm0_bank0_enable_set,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 20. "cpu0_ddata_ram7_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x0 19. "cpu0_ddata_ram6_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "cpu0_ddata_ram5_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x0 17. "cpu0_ddata_ram4_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x0 16. "cpu0_ddata_ram3_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "cpu0_ddata_ram2_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x0 14. "cpu0_ddata_ram1_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x0 13. "cpu0_ddata_ram0_enable_set,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "cpu0_ddirty_ram_enable_set,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x0 11. "cpu0_dtag_ram3_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 10. "cpu0_dtag_ram2_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "cpu0_dtag_ram1_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x0 8. "cpu0_dtag_ram0_enable_set,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x0 7. "cpu0_idata_bank3_enable_set,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "cpu0_idata_bank2_enable_set,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x0 5. "cpu0_idata_bank1_enable_set,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x0 4. "cpu0_idata_bank0_enable_set,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "cpu0_itag_ram3_enable_set,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "cpu0_itag_ram2_enable_set,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x0 1. "cpu0_itag_ram1_enable_set,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "cpu0_itag_ram0_enable_set,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 27. "cpu0_ks_vim_ramecc_enable_clr,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
|
|
bitfld.long 0x0 26. "b1tcm0_bank1_enable_clr,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 25. "b1tcm0_bank0_enable_clr,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "b0tcm0_bank1_enable_clr,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
|
|
bitfld.long 0x0 23. "b0tcm0_bank0_enable_clr,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 22. "atcm0_bank1_enable_clr,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "atcm0_bank0_enable_clr,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
|
|
bitfld.long 0x0 20. "cpu0_ddata_ram7_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x0 19. "cpu0_ddata_ram6_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "cpu0_ddata_ram5_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x0 17. "cpu0_ddata_ram4_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x0 16. "cpu0_ddata_ram3_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "cpu0_ddata_ram2_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x0 14. "cpu0_ddata_ram1_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x0 13. "cpu0_ddata_ram0_enable_clr,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "cpu0_ddirty_ram_enable_clr,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x0 11. "cpu0_dtag_ram3_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 10. "cpu0_dtag_ram2_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "cpu0_dtag_ram1_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x0 8. "cpu0_dtag_ram0_enable_clr,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x0 7. "cpu0_idata_bank3_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "cpu0_idata_bank2_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x0 5. "cpu0_idata_bank1_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x0 4. "cpu0_idata_bank0_enable_clr,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "cpu0_itag_ram3_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "cpu0_itag_ram2_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x0 1. "cpu0_itag_ram1_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "cpu0_itag_ram0_enable_clr,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "aggr_enable_set,AGGR interrupt enable set Register"
|
|
bitfld.long 0x0 1. "timeout,interrupt enable set for svbus timeout errors" "0,1"
|
|
bitfld.long 0x0 0. "parity,interrupt enable set for parity errors" "0,1"
|
|
line.long 0x4 "aggr_enable_clr,AGGR interrupt enable clear Register"
|
|
bitfld.long 0x4 1. "timeout,interrupt enable clear for svbus timeout errors" "0,1"
|
|
bitfld.long 0x4 0. "parity,interrupt enable clear for parity errors" "0,1"
|
|
line.long 0x8 "aggr_status_set,AGGR interrupt status set Register"
|
|
bitfld.long 0x8 2.--3. "timeout,interrupt status set for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "parity,interrupt status set for parity errors" "0,1,2,3"
|
|
line.long 0xC "aggr_status_clr,AGGR interrupt status clear Register"
|
|
bitfld.long 0xC 2.--3. "timeout,interrupt status clear for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "parity,interrupt status clear for parity errors" "0,1,2,3"
|
|
tree.end
|
|
tree "MSS_ECC_AGG_R5B"
|
|
base ad:0x2F7BC00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "rev,Revision parameters"
|
|
bitfld.long 0x0 30.--31. "scheme,Scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "module_id,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "revrtl,RTL version"
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|
bitfld.long 0x0 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "custom,Custom version" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "revmin,Minor version"
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group.long 0x8++0x3
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line.long 0x0 "vector,ECC Vector Register"
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rbitfld.long 0x0 24. "rd_svbus_done,Status to indicate if read on serial VBUS is complete" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "rd_svbus_address,Read address"
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bitfld.long 0x0 15. "rd_svbus,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x0 0.--10. 1. "ecc_vector,Value written to select the corresponding ECC RAM for control or status"
|
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rgroup.long 0xC++0x7
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line.long 0x0 "stat,Misc Status"
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hexmask.long.word 0x0 0.--10. 1. "num_rams,Indicates the number of RAMS serviced by the ECC aggregator"
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line.long 0x4 "wrap_rev,Revision parameters"
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bitfld.long 0x4 30.--31. "scheme,Scheme" "0,1,2,3"
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bitfld.long 0x4 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x4 16.--27. 1. "module_id,Module ID"
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hexmask.long.byte 0x4 11.--15. 1. "revrtl,RTL version"
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bitfld.long 0x4 8.--10. "revmaj,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 6.--7. "custom,Custom version" "0,1,2,3"
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hexmask.long.byte 0x4 0.--5. 1. "revmin,Minor version"
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group.long 0x14++0xF
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line.long 0x0 "ctrl,ECC Control Register"
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bitfld.long 0x0 8. "check_svbus_timeout,check for svbus timeout errors" "0,1"
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bitfld.long 0x0 7. "check_parity,check for parity errors" "0,1"
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bitfld.long 0x0 6. "error_once,Force Error only once" "0,1"
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bitfld.long 0x0 5. "force_n_row,Force Error on any RAM read" "0,1"
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bitfld.long 0x0 4. "force_ded,Force Double Bit Error" "0,1"
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bitfld.long 0x0 3. "force_sec,Force Single Bit Error" "0,1"
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bitfld.long 0x0 2. "enable_rmw,Enable rmw" "0,1"
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bitfld.long 0x0 1. "ecc_check,Enable ECC check" "0,1"
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bitfld.long 0x0 0. "ecc_enable,Enable ECC" "0,1"
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line.long 0x4 "err_ctrl1,ECC Error Control1 Register"
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hexmask.long 0x4 0.--31. 1. "ecc_row,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
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line.long 0x8 "err_ctrl2,ECC Error Control2 Register"
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hexmask.long.word 0x8 16.--31. 1. "ecc_bit2,Data bit that needs to be flipped if double bit error needs to be forced"
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hexmask.long.word 0x8 0.--15. 1. "ecc_bit1,Data bit that needs to be flipped when force_sec is set"
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line.long 0xC "err_stat1,ECC Error Status1 Register"
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hexmask.long.word 0xC 16.--31. 1. "ecc_bit1,Data bit that corresponds to the single-bit error"
|
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bitfld.long 0xC 15. "clr_ctrl_reg_err,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
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bitfld.long 0xC 13.--14. "clr_ctrl_reg_err,Clear parity Error Status" "0,1,2,3"
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bitfld.long 0xC 12. "clr_ecc_other,Clear other Error Status" "0,1"
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bitfld.long 0xC 10.--11. "clr_ecc_ded,Clear Double Bit Error Status" "0,1,2,3"
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bitfld.long 0xC 8.--9. "clr_ecc_sec,Clear Single Bit Error Status" "0,1,2,3"
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newline
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bitfld.long 0xC 7. "ctr_reg_err,control register error pending Level interrupt" "0,1"
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bitfld.long 0xC 5.--6. "parity_err,Level parity error Error Status" "0,1,2,3"
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bitfld.long 0xC 4. "ecc_other,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
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newline
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bitfld.long 0xC 2.--3. "ecc_ded,Level Double Bit Error Status" "0,1,2,3"
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bitfld.long 0xC 0.--1. "ecc_sec,Level Single Bit Error Status" "0,1,2,3"
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rgroup.long 0x24++0x3
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line.long 0x0 "err_stat2,ECC Error Status2 Register"
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hexmask.long 0x0 0.--31. 1. "ecc_row,Row address where the single or double-bit error has occurred"
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group.long 0x28++0x3
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line.long 0x0 "err_stat3,ECC Error Status3 Register"
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bitfld.long 0x0 9. "clr_svbus_timeout_err,Clear svbus timeout Error Status" "0,1"
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bitfld.long 0x0 1. "svbus_timeout_err,Level svbus timeout error Error Status" "0,1"
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rbitfld.long 0x0 0. "wb_pend,delayed write back pending Status" "0,1"
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group.long 0x3C++0x7
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line.long 0x0 "sec_eoi_reg,EOI Register"
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bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
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line.long 0x4 "sec_status_reg0,Interrupt Status Register 0"
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bitfld.long 0x4 27. "cpu1_ks_vim_ramecc_pend,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
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bitfld.long 0x4 26. "b1tcm1_bank1_pend,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
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bitfld.long 0x4 25. "b1tcm1_bank0_pend,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
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bitfld.long 0x4 24. "b0tcm1_bank1_pend,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
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bitfld.long 0x4 23. "b0tcm1_bank0_pend,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
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bitfld.long 0x4 22. "atcm1_bank1_pend,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
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|
newline
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bitfld.long 0x4 21. "atcm1_bank0_pend,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
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bitfld.long 0x4 20. "cpu1_ddata_ram7_pend,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
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bitfld.long 0x4 19. "cpu1_ddata_ram6_pend,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
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bitfld.long 0x4 18. "cpu1_ddata_ram5_pend,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
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bitfld.long 0x4 17. "cpu1_ddata_ram4_pend,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
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bitfld.long 0x4 16. "cpu1_ddata_ram3_pend,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
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bitfld.long 0x4 15. "cpu1_ddata_ram2_pend,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
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bitfld.long 0x4 14. "cpu1_ddata_ram1_pend,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
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bitfld.long 0x4 13. "cpu1_ddata_ram0_pend,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
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newline
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bitfld.long 0x4 12. "cpu1_ddirty_ram_pend,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
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bitfld.long 0x4 11. "cpu1_dtag_ram3_pend,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
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bitfld.long 0x4 10. "cpu1_dtag_ram2_pend,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
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bitfld.long 0x4 9. "cpu1_dtag_ram1_pend,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
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bitfld.long 0x4 8. "cpu1_dtag_ram0_pend,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
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bitfld.long 0x4 7. "cpu1_idata_bank3_pend,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
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bitfld.long 0x4 6. "cpu1_idata_bank2_pend,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
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bitfld.long 0x4 5. "cpu1_idata_bank1_pend,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
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bitfld.long 0x4 4. "cpu1_idata_bank0_pend,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
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newline
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bitfld.long 0x4 3. "cpu1_itag_ram3_pend,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
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bitfld.long 0x4 2. "cpu1_itag_ram2_pend,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
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bitfld.long 0x4 1. "cpu1_itag_ram1_pend,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
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newline
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bitfld.long 0x4 0. "cpu1_itag_ram0_pend,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
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group.long 0x80++0x3
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line.long 0x0 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
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bitfld.long 0x0 27. "cpu1_ks_vim_ramecc_enable_set,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
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bitfld.long 0x0 26. "b1tcm1_bank1_enable_set,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
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bitfld.long 0x0 25. "b1tcm1_bank0_enable_set,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
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newline
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bitfld.long 0x0 24. "b0tcm1_bank1_enable_set,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
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bitfld.long 0x0 23. "b0tcm1_bank0_enable_set,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
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bitfld.long 0x0 22. "atcm1_bank1_enable_set,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
|
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newline
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bitfld.long 0x0 21. "atcm1_bank0_enable_set,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
|
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bitfld.long 0x0 20. "cpu1_ddata_ram7_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
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bitfld.long 0x0 19. "cpu1_ddata_ram6_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
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newline
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bitfld.long 0x0 18. "cpu1_ddata_ram5_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
|
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bitfld.long 0x0 17. "cpu1_ddata_ram4_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
|
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bitfld.long 0x0 16. "cpu1_ddata_ram3_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "cpu1_ddata_ram2_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
|
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bitfld.long 0x0 14. "cpu1_ddata_ram1_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
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bitfld.long 0x0 13. "cpu1_ddata_ram0_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
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newline
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bitfld.long 0x0 12. "cpu1_ddirty_ram_enable_set,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
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bitfld.long 0x0 11. "cpu1_dtag_ram3_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
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bitfld.long 0x0 10. "cpu1_dtag_ram2_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
|
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newline
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bitfld.long 0x0 9. "cpu1_dtag_ram1_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
|
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bitfld.long 0x0 8. "cpu1_dtag_ram0_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
|
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bitfld.long 0x0 7. "cpu1_idata_bank3_enable_set,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
|
|
newline
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bitfld.long 0x0 6. "cpu1_idata_bank2_enable_set,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
|
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bitfld.long 0x0 5. "cpu1_idata_bank1_enable_set,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
|
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bitfld.long 0x0 4. "cpu1_idata_bank0_enable_set,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "cpu1_itag_ram3_enable_set,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
|
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bitfld.long 0x0 2. "cpu1_itag_ram2_enable_set,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
|
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bitfld.long 0x0 1. "cpu1_itag_ram1_enable_set,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
|
|
newline
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bitfld.long 0x0 0. "cpu1_itag_ram0_enable_set,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
|
|
group.long 0xC0++0x3
|
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line.long 0x0 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
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bitfld.long 0x0 27. "cpu1_ks_vim_ramecc_enable_clr,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
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bitfld.long 0x0 26. "b1tcm1_bank1_enable_clr,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x0 25. "b1tcm1_bank0_enable_clr,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "b0tcm1_bank1_enable_clr,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x0 23. "b0tcm1_bank0_enable_clr,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
|
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bitfld.long 0x0 22. "atcm1_bank1_enable_clr,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "atcm1_bank0_enable_clr,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
|
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bitfld.long 0x0 20. "cpu1_ddata_ram7_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
|
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bitfld.long 0x0 19. "cpu1_ddata_ram6_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "cpu1_ddata_ram5_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x0 17. "cpu1_ddata_ram4_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x0 16. "cpu1_ddata_ram3_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
|
|
newline
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bitfld.long 0x0 15. "cpu1_ddata_ram2_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x0 14. "cpu1_ddata_ram1_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x0 13. "cpu1_ddata_ram0_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "cpu1_ddirty_ram_enable_clr,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x0 11. "cpu1_dtag_ram3_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 10. "cpu1_dtag_ram2_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "cpu1_dtag_ram1_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x0 8. "cpu1_dtag_ram0_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x0 7. "cpu1_idata_bank3_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "cpu1_idata_bank2_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x0 5. "cpu1_idata_bank1_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x0 4. "cpu1_idata_bank0_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "cpu1_itag_ram3_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "cpu1_itag_ram2_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x0 1. "cpu1_itag_ram1_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "cpu1_itag_ram0_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
|
|
group.long 0x13C++0x7
|
|
line.long 0x0 "ded_eoi_reg,EOI Register"
|
|
bitfld.long 0x0 0. "eoi_wr,EOI Register" "0,1"
|
|
line.long 0x4 "ded_status_reg0,Interrupt Status Register 0"
|
|
bitfld.long 0x4 27. "cpu1_ks_vim_ramecc_pend,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
|
|
bitfld.long 0x4 26. "b1tcm1_bank1_pend,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x4 25. "b1tcm1_bank0_pend,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "b0tcm1_bank1_pend,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x4 23. "b0tcm1_bank0_pend,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
|
|
bitfld.long 0x4 22. "atcm1_bank1_pend,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "atcm1_bank0_pend,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
|
|
bitfld.long 0x4 20. "cpu1_ddata_ram7_pend,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x4 19. "cpu1_ddata_ram6_pend,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "cpu1_ddata_ram5_pend,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x4 17. "cpu1_ddata_ram4_pend,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x4 16. "cpu1_ddata_ram3_pend,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "cpu1_ddata_ram2_pend,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x4 14. "cpu1_ddata_ram1_pend,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x4 13. "cpu1_ddata_ram0_pend,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "cpu1_ddirty_ram_pend,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x4 11. "cpu1_dtag_ram3_pend,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x4 10. "cpu1_dtag_ram2_pend,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "cpu1_dtag_ram1_pend,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x4 8. "cpu1_dtag_ram0_pend,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x4 7. "cpu1_idata_bank3_pend,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "cpu1_idata_bank2_pend,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x4 5. "cpu1_idata_bank1_pend,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x4 4. "cpu1_idata_bank0_pend,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "cpu1_itag_ram3_pend,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x4 2. "cpu1_itag_ram2_pend,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x4 1. "cpu1_itag_ram1_pend,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "cpu1_itag_ram0_pend,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x0 27. "cpu1_ks_vim_ramecc_enable_set,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
|
|
bitfld.long 0x0 26. "b1tcm1_bank1_enable_set,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x0 25. "b1tcm1_bank0_enable_set,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "b0tcm1_bank1_enable_set,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x0 23. "b0tcm1_bank0_enable_set,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
|
|
bitfld.long 0x0 22. "atcm1_bank1_enable_set,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "atcm1_bank0_enable_set,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
|
|
bitfld.long 0x0 20. "cpu1_ddata_ram7_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x0 19. "cpu1_ddata_ram6_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "cpu1_ddata_ram5_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x0 17. "cpu1_ddata_ram4_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x0 16. "cpu1_ddata_ram3_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "cpu1_ddata_ram2_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x0 14. "cpu1_ddata_ram1_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x0 13. "cpu1_ddata_ram0_enable_set,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "cpu1_ddirty_ram_enable_set,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x0 11. "cpu1_dtag_ram3_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 10. "cpu1_dtag_ram2_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "cpu1_dtag_ram1_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x0 8. "cpu1_dtag_ram0_enable_set,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x0 7. "cpu1_idata_bank3_enable_set,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "cpu1_idata_bank2_enable_set,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x0 5. "cpu1_idata_bank1_enable_set,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x0 4. "cpu1_idata_bank0_enable_set,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "cpu1_itag_ram3_enable_set,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "cpu1_itag_ram2_enable_set,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x0 1. "cpu1_itag_ram1_enable_set,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "cpu1_itag_ram0_enable_set,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x0 27. "cpu1_ks_vim_ramecc_enable_clr,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
|
|
bitfld.long 0x0 26. "b1tcm1_bank1_enable_clr,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x0 25. "b1tcm1_bank0_enable_clr,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "b0tcm1_bank1_enable_clr,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
|
|
bitfld.long 0x0 23. "b0tcm1_bank0_enable_clr,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
|
|
bitfld.long 0x0 22. "atcm1_bank1_enable_clr,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "atcm1_bank0_enable_clr,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
|
|
bitfld.long 0x0 20. "cpu1_ddata_ram7_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
|
|
bitfld.long 0x0 19. "cpu1_ddata_ram6_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "cpu1_ddata_ram5_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
|
|
bitfld.long 0x0 17. "cpu1_ddata_ram4_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
|
|
bitfld.long 0x0 16. "cpu1_ddata_ram3_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "cpu1_ddata_ram2_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
|
|
bitfld.long 0x0 14. "cpu1_ddata_ram1_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
|
|
bitfld.long 0x0 13. "cpu1_ddata_ram0_enable_clr,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "cpu1_ddirty_ram_enable_clr,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
|
|
bitfld.long 0x0 11. "cpu1_dtag_ram3_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 10. "cpu1_dtag_ram2_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "cpu1_dtag_ram1_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
|
|
bitfld.long 0x0 8. "cpu1_dtag_ram0_enable_clr,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
|
|
bitfld.long 0x0 7. "cpu1_idata_bank3_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "cpu1_idata_bank2_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
|
|
bitfld.long 0x0 5. "cpu1_idata_bank1_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
|
|
bitfld.long 0x0 4. "cpu1_idata_bank0_enable_clr,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "cpu1_itag_ram3_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
|
|
bitfld.long 0x0 2. "cpu1_itag_ram2_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
|
|
bitfld.long 0x0 1. "cpu1_itag_ram1_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "cpu1_itag_ram0_enable_clr,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "aggr_enable_set,AGGR interrupt enable set Register"
|
|
bitfld.long 0x0 1. "timeout,interrupt enable set for svbus timeout errors" "0,1"
|
|
bitfld.long 0x0 0. "parity,interrupt enable set for parity errors" "0,1"
|
|
line.long 0x4 "aggr_enable_clr,AGGR interrupt enable clear Register"
|
|
bitfld.long 0x4 1. "timeout,interrupt enable clear for svbus timeout errors" "0,1"
|
|
bitfld.long 0x4 0. "parity,interrupt enable clear for parity errors" "0,1"
|
|
line.long 0x8 "aggr_status_set,AGGR interrupt status set Register"
|
|
bitfld.long 0x8 2.--3. "timeout,interrupt status set for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "parity,interrupt status set for parity errors" "0,1,2,3"
|
|
line.long 0xC "aggr_status_clr,AGGR interrupt status clear Register"
|
|
bitfld.long 0xC 2.--3. "timeout,interrupt status clear for svbus timeout errors" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "parity,interrupt status clear for parity errors" "0,1,2,3"
|
|
tree.end
|
|
tree "MSS_ESM"
|
|
base ad:0x2F7A400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
|
|
hexmask.long 0x0 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1.."
|
|
line.long 0x4 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
|
|
hexmask.long 0x4 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1.."
|
|
line.long 0x8 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
|
|
hexmask.long 0x8 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0xC "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
|
|
hexmask.long 0xC 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
|
|
hexmask.long 0x10 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register.."
|
|
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
|
|
hexmask.long 0x14 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register.."
|
|
repeat 4. (list 0x1 0x4 0x7 0xA)(list 0x0 0x40 0x80 0xC0)
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "ESMSR$1,ESM Status Register 1"
|
|
hexmask.long 0x0 0.--31. 1. "ESF,Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt.."
|
|
repeat.end
|
|
group.long 0x1C++0x3B
|
|
line.long 0x0 "ESMSR2,ESM Status Register 2"
|
|
hexmask.long 0x0 0.--31. 1. "ESF,Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt.."
|
|
line.long 0x4 "ESMSR3,ESM Status Register 3"
|
|
hexmask.long 0x4 0.--31. 1. "ESF,Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."
|
|
line.long 0x8 "ESMEPSR,ESM ERROR Pin Status Register"
|
|
hexmask.long 0x8 1.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
bitfld.long 0x8 0. "EPSF,ERROR Pin Status Flag. Provides status information for the ERROR Pin. Read/Write in User and Privileged mode. 0 Read: ERROR Pin is low (active) if any error has occurred. Write: Writes have no effect. 1 Read: ERROR Pin is high if no error has.." "0,1"
|
|
line.long 0xC "ESMIOFFHR,ESM Interrupt Offset High Register"
|
|
hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.word 0xC 0.--8. 1. "INTOFFH,Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts of error Group1. Inside a group channel.."
|
|
line.long 0x10 "ESMIOFFLR,ESM Interrupt Offset Low Register"
|
|
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.byte 0x10 0.--7. 1. "INTOFFL,Offset Low Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the low level interrupt line. Inside a group channel 0 has highest priority and channel 31 has lowest priority. User and privileged.."
|
|
line.long 0x14 "ESMLTCR,ESM Low-Time Counter Register"
|
|
hexmask.long.word 0x14 16.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.word 0x14 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin. The low-time counter is triggered by the peripheral clock (VCLK). Note: Low time counter is set to the default preload value of the ESMLTCPR in the.."
|
|
line.long 0x18 "ESMLTCPR,ESM Low-Time Counter Preload Register"
|
|
hexmask.long.word 0x18 16.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.word 0x18 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write)."
|
|
line.long 0x1C "ESMEKR,ESM Error Key Register"
|
|
hexmask.long 0x1C 4.--31. 1. "RESERVED,Read returns 0. Writes have no effect."
|
|
hexmask.long.byte 0x1C 0.--3. 1. "EKEY,Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. User and privileged mode (read): Returns current value of the EKEY. Privileged mode (write): 0 Activates normal mode (recommended default mode). Ah Forces error on.."
|
|
line.long 0x20 "ESMSSR2,ESM Status Shadow Register 2"
|
|
hexmask.long 0x20 0.--31. 1. "ESF,Error Status Flag. Shadow register for status information on pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit."
|
|
line.long 0x24 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
|
|
hexmask.long 0x24 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4.."
|
|
line.long 0x28 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
|
|
hexmask.long 0x28 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4.."
|
|
line.long 0x2C "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
|
|
hexmask.long 0x2C 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x30 "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
|
|
hexmask.long 0x30 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x34 "ESMILSR4,Interrupt Level Set/Status Register 4"
|
|
hexmask.long 0x34 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register.."
|
|
line.long 0x38 "ESMILCR4,Interrupt Level Clear/Status Register 4"
|
|
hexmask.long 0x38 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register.."
|
|
group.long 0x80++0x17
|
|
line.long 0x0 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
|
|
hexmask.long 0x0 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7.."
|
|
line.long 0x4 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
|
|
hexmask.long 0x4 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR7.."
|
|
line.long 0x8 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
|
|
hexmask.long 0x8 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0xC "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
|
|
hexmask.long 0xC 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR7 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
|
|
hexmask.long 0x10 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register.."
|
|
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
|
|
hexmask.long 0x14 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register.."
|
|
group.long 0xC0++0x17
|
|
line.long 0x0 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
|
|
hexmask.long 0x0 0.--31. 1. "IEPSET,Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR10.."
|
|
line.long 0x4 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
|
|
hexmask.long 0x4 0.--31. 1. "IEPCLR,Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR10.."
|
|
line.long 0x8 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
|
|
hexmask.long 0x8 0.--31. 1. "INTENSET,Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR10 register unchanged. 1 Read: Interrupt is enabled. Write:.."
|
|
line.long 0xC "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
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hexmask.long 0xC 0.--31. 1. "INTENCLR,Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR10 register unchanged. 1 Read: Interrupt is enabled. Write:.."
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line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
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hexmask.long 0x10 0.--31. 1. "INTLVLSET,Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR10 register.."
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line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
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hexmask.long 0x14 0.--31. 1. "INTLVLCLR,Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR10 register.."
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tree.end
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tree "MSS_ETPWMA"
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base ad:0x3F78C00
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group.long 0x0++0x3F
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line.long 0x0 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
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hexmask.long.word 0x0 19.--31. 1. "Reserved,Reserved"
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bitfld.long 0x0 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event." "0,1"
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bitfld.long 0x0 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event." "0,1"
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bitfld.long 0x0 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit. At reset the counter is frozen; therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]. 0 Time-Base Counter is currently counting.." "0,1"
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bitfld.long 0x0 14.--15. "TBCTL_FREE _SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: - Up-count mode:.." "0,1,2,3"
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bitfld.long 0x0 13. "TBCTL_PHSDIR,Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new.." "0,1"
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bitfld.long 0x0 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV x CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV x CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC.." "0,1"
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bitfld.long 0x0 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB).." "0,1,2,3"
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bitfld.long 0x0 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero. A write or read to the TBPRD register accesses the shadow register." "0,1"
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bitfld.long 0x0 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x0 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall.." "0,1,2,3"
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line.long 0x4 "TBPHS,Time-Base Phase Register"
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hexmask.long.word 0x4 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.."
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hexmask.long.word 0x4 0.--15. 1. "Reserved,Reserved"
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line.long 0x8 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
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hexmask.long.word 0x8 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD].."
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hexmask.long.word 0x8 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base.."
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line.long 0xC "CMPCTL,Counter-Compare Control Register"
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hexmask.long.byte 0xC 26.--31. 1. "Reserved4,Reserved"
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bitfld.long 0xC 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value." "0,1"
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bitfld.long 0xC 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0,1"
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rbitfld.long 0xC 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0xC 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0,1"
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rbitfld.long 0xC 21. "Reserved2,Reserved" "0,1"
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bitfld.long 0xC 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0,1"
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bitfld.long 0xC 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal.." "0,1,2,3"
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bitfld.long 0xC 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL[SHDWAMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal.." "0,1,2,3"
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hexmask.long.word 0xC 0.--15. 1. "Reserved1,Reserved"
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line.long 0x10 "CMPA,Counter-Compare A Register"
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hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This.."
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hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
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line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
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hexmask.long.byte 0x14 28.--31. 1. "Reserved,Reserved"
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bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal.." "0,1,2,3"
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bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set:.." "0,1,2,3"
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bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output.." "0,1,2,3"
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hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the.."
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line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
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hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly.." "0,1,2,3"
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bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is a forced event is initiated.) This is a one-shot forced event. It can.." "0,1"
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bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1 Initiates a single software forced.." "0,1"
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bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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hexmask.long.byte 0x18 12.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set:.." "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output.." "0,1,2,3"
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line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
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bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK x 2." "0,1"
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hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
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bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms.." "0,1,2,3"
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bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following.." "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0.." "0,1,2,3"
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hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To.." "0,1,2,3"
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bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing.." "0,1,2,3"
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line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.long.byte 0x20 26.--31. 1. "Reserved1,Reserved"
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hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count. 10-bit counter"
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hexmask.long.byte 0x20 10.--15. 1. "Reserved2,Reserved"
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hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count. 10-bit counter"
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line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
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hexmask.long.byte 0x24 28.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
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bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
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bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
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line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
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hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
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bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
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bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt" "0,1"
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rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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hexmask.long.byte 0x28 12.--15. 1. "Reserved1,Reserved"
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bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB.." "0,1,2,3"
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bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA.." "0,1,2,3"
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line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
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hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition." "0,1"
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bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition" "0,1"
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bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition." "0,1"
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bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition." "0,1"
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bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition." "0,1"
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bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
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bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
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bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
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bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register" "0,1"
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bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0,1"
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bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is.." "0,1"
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line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
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bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse" "0,1"
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bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse." "0,1"
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bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 20.--23. 1. "Reserved1,Reserved"
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bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
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bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or.." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0,1"
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bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit" "0,1"
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bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit" "0,1"
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bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG[OST] bit" "0,1"
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bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0,1"
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rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
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line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
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hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
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bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag.." "0,1"
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bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was.." "0,1"
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rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be.." "0,1"
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bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have.." "0,1,2,3"
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bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled (ETSEL[SOCBEN] = 1)." "0,1,2,3"
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bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have.." "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled (ETSEL[SOCAEN] = 1)." "0,1,2,3"
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hexmask.long.byte 0x34 4.--7. 1. "Reserved3,Reserved"
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bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0.." "0,1,2,3"
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bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt status flag.." "0,1,2,3"
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line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
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hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
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bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG.." "0,1"
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bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on.." "0,1"
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rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and.." "0,1"
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hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCB] flag bit" "0,1"
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bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCA] flag bit" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
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bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0,1"
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line.long 0x3C "PCCTL,PWM-Chopper Control Register"
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hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
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bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x3C 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide (.."
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
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repeat 8. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
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rgroup.long ($2+0x40)++0x3
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line.long 0x0 "Reserved$1,Reserved"
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hexmask.long 0x0 0.--31. 1. "Reserved,Reserved"
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repeat.end
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group.long 0x60++0x13
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line.long 0x0 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
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hexmask.long.byte 0x0 26.--31. 1. "Reserved2,Reserved"
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bitfld.long 0x0 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x0 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "Reserved1,Reserved"
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bitfld.long 0x0 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
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bitfld.long 0x0 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
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bitfld.long 0x0 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x0 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input.."
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hexmask.long.byte 0x0 8.--11. 1. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3.."
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hexmask.long.byte 0x0 4.--7. 1. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input.."
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hexmask.long.byte 0x0 0.--3. 1. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3.."
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line.long 0x4 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
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hexmask.long.word 0x4 22.--31. 1. "Reserved3,Reserved"
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bitfld.long 0x4 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
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bitfld.long 0x4 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
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bitfld.long 0x4 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x4 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
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hexmask.long.byte 0x4 10.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x4 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x4 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x4 4.--7. 1. "Reserved1,Reserved"
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bitfld.long 0x4 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
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bitfld.long 0x4 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
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bitfld.long 0x4 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x4 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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line.long 0x8 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
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hexmask.long.word 0x8 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.."
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hexmask.long.word 0x8 2.--15. 1. "Reserved,Reserved"
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bitfld.long 0x8 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will.." "0,1"
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bitfld.long 0x8 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture." "0,1"
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line.long 0xC "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
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hexmask.long.byte 0xC 24.--31. 1. "Reserved1,Reserved"
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hexmask.long.byte 0xC 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.."
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hexmask.long.word 0xC 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.."
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line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
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hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event."
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hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again."
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tree.end
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tree "MSS_ETPWMB"
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base ad:0x3F78D00
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group.long 0x0++0x3F
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line.long 0x0 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
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hexmask.long.word 0x0 19.--31. 1. "Reserved,Reserved"
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bitfld.long 0x0 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event." "0,1"
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bitfld.long 0x0 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event." "0,1"
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bitfld.long 0x0 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit. At reset the counter is frozen; therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]. 0 Time-Base Counter is currently counting.." "0,1"
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bitfld.long 0x0 14.--15. "TBCTL_FREE _SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: - Up-count mode:.." "0,1,2,3"
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bitfld.long 0x0 13. "TBCTL_PHSDIR,Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new.." "0,1"
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bitfld.long 0x0 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV x CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV x CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC.." "0,1"
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bitfld.long 0x0 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB).." "0,1,2,3"
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bitfld.long 0x0 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero. A write or read to the TBPRD register accesses the shadow register." "0,1"
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bitfld.long 0x0 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x0 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall.." "0,1,2,3"
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line.long 0x4 "TBPHS,Time-Base Phase Register"
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hexmask.long.word 0x4 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.."
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hexmask.long.word 0x4 0.--15. 1. "Reserved,Reserved"
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line.long 0x8 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
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hexmask.long.word 0x8 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD].."
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hexmask.long.word 0x8 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base.."
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line.long 0xC "CMPCTL,Counter-Compare Control Register"
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hexmask.long.byte 0xC 26.--31. 1. "Reserved4,Reserved"
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bitfld.long 0xC 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value." "0,1"
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bitfld.long 0xC 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0,1"
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rbitfld.long 0xC 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0xC 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0,1"
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rbitfld.long 0xC 21. "Reserved2,Reserved" "0,1"
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bitfld.long 0xC 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0,1"
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bitfld.long 0xC 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal.." "0,1,2,3"
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bitfld.long 0xC 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL[SHDWAMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal.." "0,1,2,3"
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hexmask.long.word 0xC 0.--15. 1. "Reserved1,Reserved"
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line.long 0x10 "CMPA,Counter-Compare A Register"
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hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This.."
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hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
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line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
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hexmask.long.byte 0x14 28.--31. 1. "Reserved,Reserved"
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bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal.." "0,1,2,3"
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bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set:.." "0,1,2,3"
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bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output.." "0,1,2,3"
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hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the.."
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line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
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hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly.." "0,1,2,3"
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bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is a forced event is initiated.) This is a one-shot forced event. It can.." "0,1"
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bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1 Initiates a single software forced.." "0,1"
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bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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hexmask.long.byte 0x18 12.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set:.." "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output.." "0,1,2,3"
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line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
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bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK x 2." "0,1"
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hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
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bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms.." "0,1,2,3"
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bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following.." "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0.." "0,1,2,3"
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hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To.." "0,1,2,3"
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bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing.." "0,1,2,3"
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line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.long.byte 0x20 26.--31. 1. "Reserved1,Reserved"
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hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count. 10-bit counter"
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hexmask.long.byte 0x20 10.--15. 1. "Reserved2,Reserved"
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hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count. 10-bit counter"
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line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
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hexmask.long.byte 0x24 28.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
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bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
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bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
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line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
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hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
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bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
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bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt" "0,1"
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rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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hexmask.long.byte 0x28 12.--15. 1. "Reserved1,Reserved"
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bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB.." "0,1,2,3"
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bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA.." "0,1,2,3"
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line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
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hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition." "0,1"
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bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition" "0,1"
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bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition." "0,1"
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bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition." "0,1"
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bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition." "0,1"
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bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
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bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
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bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
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bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register" "0,1"
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bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0,1"
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bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is.." "0,1"
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line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
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bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse" "0,1"
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bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse." "0,1"
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bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 20.--23. 1. "Reserved1,Reserved"
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bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
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bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or.." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0,1"
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bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit" "0,1"
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bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit" "0,1"
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bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG[OST] bit" "0,1"
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bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0,1"
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rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
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line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
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hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
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bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag.." "0,1"
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bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was.." "0,1"
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rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be.." "0,1"
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bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have.." "0,1,2,3"
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bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled (ETSEL[SOCBEN] = 1)." "0,1,2,3"
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bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have.." "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled (ETSEL[SOCAEN] = 1)." "0,1,2,3"
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hexmask.long.byte 0x34 4.--7. 1. "Reserved3,Reserved"
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bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0.." "0,1,2,3"
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bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt status flag.." "0,1,2,3"
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line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
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hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
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bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG.." "0,1"
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bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on.." "0,1"
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rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and.." "0,1"
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hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCB] flag bit" "0,1"
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bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCA] flag bit" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
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bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0,1"
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line.long 0x3C "PCCTL,PWM-Chopper Control Register"
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hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
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bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x3C 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide (.."
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
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repeat 8. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
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rgroup.long ($2+0x40)++0x3
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line.long 0x0 "Reserved$1,Reserved"
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hexmask.long 0x0 0.--31. 1. "Reserved,Reserved"
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repeat.end
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group.long 0x60++0x13
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line.long 0x0 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
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hexmask.long.byte 0x0 26.--31. 1. "Reserved2,Reserved"
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bitfld.long 0x0 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x0 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "Reserved1,Reserved"
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bitfld.long 0x0 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
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bitfld.long 0x0 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
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bitfld.long 0x0 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x0 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input.."
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hexmask.long.byte 0x0 8.--11. 1. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3.."
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hexmask.long.byte 0x0 4.--7. 1. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input.."
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hexmask.long.byte 0x0 0.--3. 1. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3.."
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line.long 0x4 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
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hexmask.long.word 0x4 22.--31. 1. "Reserved3,Reserved"
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bitfld.long 0x4 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
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bitfld.long 0x4 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
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bitfld.long 0x4 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x4 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
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hexmask.long.byte 0x4 10.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x4 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x4 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x4 4.--7. 1. "Reserved1,Reserved"
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bitfld.long 0x4 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
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bitfld.long 0x4 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
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bitfld.long 0x4 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x4 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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line.long 0x8 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
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hexmask.long.word 0x8 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.."
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hexmask.long.word 0x8 2.--15. 1. "Reserved,Reserved"
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bitfld.long 0x8 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will.." "0,1"
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bitfld.long 0x8 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture." "0,1"
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line.long 0xC "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
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hexmask.long.byte 0xC 24.--31. 1. "Reserved1,Reserved"
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hexmask.long.byte 0xC 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.."
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hexmask.long.word 0xC 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.."
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line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
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hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event."
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hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again."
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tree.end
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tree "MSS_ETPWMC"
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base ad:0x3F78E00
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group.long 0x0++0x3F
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line.long 0x0 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
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hexmask.long.word 0x0 19.--31. 1. "Reserved,Reserved"
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bitfld.long 0x0 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event." "0,1"
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bitfld.long 0x0 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event." "0,1"
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bitfld.long 0x0 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit. At reset the counter is frozen; therefore this bit has no meaning. To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]. 0 Time-Base Counter is currently counting.." "0,1"
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bitfld.long 0x0 14.--15. "TBCTL_FREE _SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: - Up-count mode:.." "0,1,2,3"
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bitfld.long 0x0 13. "TBCTL_PHSDIR,Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new.." "0,1"
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bitfld.long 0x0 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV x CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV x CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC.." "0,1"
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bitfld.long 0x0 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB).." "0,1,2,3"
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bitfld.long 0x0 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero. A write or read to the TBPRD register accesses the shadow register." "0,1"
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bitfld.long 0x0 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x0 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall.." "0,1,2,3"
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line.long 0x4 "TBPHS,Time-Base Phase Register"
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hexmask.long.word 0x4 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.."
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hexmask.long.word 0x4 0.--15. 1. "Reserved,Reserved"
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line.long 0x8 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
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hexmask.long.word 0x8 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD].."
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hexmask.long.word 0x8 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base.."
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line.long 0xC "CMPCTL,Counter-Compare Control Register"
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hexmask.long.byte 0xC 26.--31. 1. "Reserved4,Reserved"
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bitfld.long 0xC 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value." "0,1"
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bitfld.long 0xC 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0,1"
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rbitfld.long 0xC 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0xC 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access.." "0,1"
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rbitfld.long 0xC 21. "Reserved2,Reserved" "0,1"
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bitfld.long 0xC 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the.." "0,1"
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bitfld.long 0xC 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal.." "0,1,2,3"
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bitfld.long 0xC 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL[SHDWAMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal.." "0,1,2,3"
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hexmask.long.word 0xC 0.--15. 1. "Reserved1,Reserved"
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line.long 0x10 "CMPA,Counter-Compare A Register"
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hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare A' event. This.."
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hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
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line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
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hexmask.long.byte 0x14 28.--31. 1. "Reserved,Reserved"
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bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal.." "0,1,2,3"
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bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set:.." "0,1,2,3"
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bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output.." "0,1,2,3"
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hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the.."
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line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
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hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly.." "0,1,2,3"
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bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is a forced event is initiated.) This is a one-shot forced event. It can.." "0,1"
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bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is a forced event is initiated). 1 Initiates a single software forced.." "0,1"
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bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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hexmask.long.byte 0x18 12.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be.." "0,1,2,3"
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bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period. Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set:.." "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero. Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output.." "0,1,2,3"
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line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
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bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK x 2." "0,1"
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hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
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bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms.." "0,1,2,3"
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bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following.." "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0.." "0,1,2,3"
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hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To.." "0,1,2,3"
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bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing.." "0,1,2,3"
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line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
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hexmask.long.byte 0x20 26.--31. 1. "Reserved1,Reserved"
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hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count. 10-bit counter"
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hexmask.long.byte 0x20 10.--15. 1. "Reserved2,Reserved"
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hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count. 10-bit counter"
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line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
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hexmask.long.byte 0x24 28.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
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bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
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bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
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line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
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hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
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bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
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bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt" "0,1"
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rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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hexmask.long.byte 0x28 12.--15. 1. "Reserved1,Reserved"
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bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing trip action is disabled" "0,1,2,3"
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bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB.." "0,1,2,3"
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bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA.." "0,1,2,3"
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line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
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hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition." "0,1"
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bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition" "0,1"
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bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition." "0,1"
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bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition." "0,1"
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bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition." "0,1"
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bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
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bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
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bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
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bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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newline
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
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bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register" "0,1"
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bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0,1"
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newline
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bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is.." "0,1"
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line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
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bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse" "0,1"
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bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse." "0,1"
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newline
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bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 20.--23. 1. "Reserved1,Reserved"
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bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
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newline
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bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or.." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0,1"
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newline
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bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit" "0,1"
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bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit" "0,1"
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bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit" "0,1"
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newline
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG[OST] bit" "0,1"
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bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0,1"
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rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
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line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
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hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
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bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag.." "0,1"
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bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was.." "0,1"
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newline
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rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be.." "0,1"
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bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have.." "0,1,2,3"
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newline
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bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled (ETSEL[SOCBEN] = 1)." "0,1,2,3"
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bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have.." "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled (ETSEL[SOCAEN] = 1)." "0,1,2,3"
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newline
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hexmask.long.byte 0x34 4.--7. 1. "Reserved3,Reserved"
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bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0.." "0,1,2,3"
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bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt status flag.." "0,1,2,3"
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line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
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hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
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bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG.." "0,1"
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bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on.." "0,1"
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newline
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rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and.." "0,1"
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hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
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newline
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bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCB] flag bit" "0,1"
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bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCA] flag bit" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
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newline
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bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0,1"
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line.long 0x3C "PCCTL,PWM-Chopper Control Register"
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hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
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bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x3C 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide (.."
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
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repeat 8. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C)
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rgroup.long ($2+0x40)++0x3
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line.long 0x0 "Reserved$1,Reserved"
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hexmask.long 0x0 0.--31. 1. "Reserved,Reserved"
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repeat.end
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group.long 0x60++0x13
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line.long 0x0 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
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hexmask.long.byte 0x0 26.--31. 1. "Reserved2,Reserved"
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bitfld.long 0x0 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x0 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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newline
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hexmask.long.byte 0x0 20.--23. 1. "Reserved1,Reserved"
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bitfld.long 0x0 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
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bitfld.long 0x0 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
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newline
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bitfld.long 0x0 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x0 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input.."
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newline
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hexmask.long.byte 0x0 8.--11. 1. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3.."
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hexmask.long.byte 0x0 4.--7. 1. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input.."
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hexmask.long.byte 0x0 0.--3. 1. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals when used as trip signals are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3.."
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line.long 0x4 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
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hexmask.long.word 0x4 22.--31. 1. "Reserved3,Reserved"
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bitfld.long 0x4 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
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bitfld.long 0x4 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
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newline
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bitfld.long 0x4 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x4 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
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hexmask.long.byte 0x4 10.--15. 1. "Reserved2,Reserved"
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newline
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bitfld.long 0x4 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x4 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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hexmask.long.byte 0x4 4.--7. 1. "Reserved1,Reserved"
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newline
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bitfld.long 0x4 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
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bitfld.long 0x4 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
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bitfld.long 0x4 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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newline
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bitfld.long 0x4 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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line.long 0x8 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
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hexmask.long.word 0x8 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.."
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hexmask.long.word 0x8 2.--15. 1. "Reserved,Reserved"
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bitfld.long 0x8 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will.." "0,1"
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newline
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bitfld.long 0x8 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture." "0,1"
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line.long 0xC "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
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hexmask.long.byte 0xC 24.--31. 1. "Reserved1,Reserved"
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hexmask.long.byte 0xC 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.."
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hexmask.long.word 0xC 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.."
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line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
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hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event."
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hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again."
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tree.end
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tree "MSS_GIO"
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base ad:0x2F7B400
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group.long 0x0++0x153
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line.long 0x0 "GIOGCR,GIO reset"
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hexmask.long 0x0 1.--31. 1. "NU0,Reserved"
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bitfld.long 0x0 0. "RESET,GIO reset" "0,1"
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line.long 0x4 "GIOPWDN,GIO power down mode register"
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hexmask.long 0x4 1.--31. 1. "NU,Reserved"
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bitfld.long 0x4 0. "GIOPWDN,Writing to the GIOPWDN bit is only allowed in privilege mode. Reading of the GIOPWDN bit is allowed in all modes. Privilege mode (write): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode User mode (write): Writes have no.." "0: Normal operation; clocks enabled to GIO module,1: Power-down mode"
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line.long 0x8 "GIOINTDET,Interrupt detection select for pins [0:1] GIO[7:0]."
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hexmask.long.byte 0x8 24.--31. 1. "GIOINTDET_3,Interrupt detection select for pins GIOD[7:0]."
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hexmask.long.byte 0x8 16.--23. 1. "GIOINTDET_2,Interrupt detection select for pins GIOC[7:0]."
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hexmask.long.byte 0x8 8.--15. 1. "GIOINTDET_1,Interrupt detection select for pins GIOB[7:0]."
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hexmask.long.byte 0x8 0.--7. 1. "GIOINTDET_0,Interrupt detection select for pins GIOA[7:0]."
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line.long 0xC "GIOPOL,Interrupt polarity select for pins [0:1] GIO[7:0]."
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hexmask.long.byte 0xC 24.--31. 1. "GIOPOL_3,Interrupt polarity select for pins GIOD[7:0]"
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hexmask.long.byte 0xC 16.--23. 1. "GIOPOL_2,Interrupt polarity select for pins GIOC[7:0]"
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hexmask.long.byte 0xC 8.--15. 1. "GIOPOL_1,Interrupt polarity select for pins GIOB[7:0]"
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hexmask.long.byte 0xC 0.--7. 1. "GIOPOL_0,Interrupt polarity select for pins GIOA[7:0]"
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line.long 0x10 "GIOENASET,Interrupt enable for pins [0:1] GIO[7:0]."
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hexmask.long.byte 0x10 24.--31. 1. "GIOENASET_3,Interrupt enable for pins GIOD [7:0]"
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hexmask.long.byte 0x10 16.--23. 1. "GIOENASET_2,Interrupt enable for pins GIOC [7:0]"
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hexmask.long.byte 0x10 8.--15. 1. "GIOENASET_1,Interrupt enable for pins GIOB [7:0]"
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hexmask.long.byte 0x10 0.--7. 1. "GIOENASET_0,Interrupt enable for pins GIOA [7:0]"
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line.long 0x14 "GIOENACLR,Interrupt enable for pins [0:1] GIO[7:0]."
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hexmask.long.byte 0x14 24.--31. 1. "GIOENACLR_3,Interrupt enable for pins GIOD [7:0]"
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hexmask.long.byte 0x14 16.--23. 1. "GIOENACLR_2,Interrupt enable for pins GIOC [7:0]"
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|
hexmask.long.byte 0x14 8.--15. 1. "GIOENACLR_1,Interrupt enable for pins GIOB [7:0]"
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hexmask.long.byte 0x14 0.--7. 1. "GIOENACLR_0,Interrupt enable for pins GIOA [7:0]"
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line.long 0x18 "GIOLVLSET,GIO high priority interrupt for pins [0:1] GIO[7:0]."
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hexmask.long.byte 0x18 24.--31. 1. "GIOLVLSET_3,GIO high priority interrupt for pins GIOD[7:0]"
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|
hexmask.long.byte 0x18 16.--23. 1. "GIOLVLSET_2,GIO high priority interrupt for pins GIOC[7:0]"
|
|
hexmask.long.byte 0x18 8.--15. 1. "GIOLVLSET_1,GIO high priority interrupt for pins GIOB[7:0]"
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|
hexmask.long.byte 0x18 0.--7. 1. "GIOLVLSET_0,GIO high priority interrupt for pins GIOA[7:0]"
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line.long 0x1C "GIOLVLCLR,GIO low priority interrupt for pins [0:1] GIO[7:0]."
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|
hexmask.long.byte 0x1C 24.--31. 1. "GIOLVLCLR_3,GIO low priority interrupt for pins GIOD[7:0]"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "GIOLVLCLR_2,GIO low priority interrupt for pins GIOC[7:0]"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "GIOLVLCLR_1,GIO low priority interrupt for pins GIOB[7:0]"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "GIOLVLCLR_0,GIO low priority interrupt for pins GIOA[7:0]"
|
|
line.long 0x20 "GIOFLG,GIO flag for pins [0:1] GIO[7:0]."
|
|
hexmask.long.byte 0x20 24.--31. 1. "GIOFLG_3,GIO flag for pins GIOD[7:0]"
|
|
hexmask.long.byte 0x20 16.--23. 1. "GIOFLG_2,GIO flag for pins GIOC[7:0]"
|
|
hexmask.long.byte 0x20 8.--15. 1. "GIOFLG_1,GIO flag for pins GIOB[7:0]"
|
|
hexmask.long.byte 0x20 0.--7. 1. "GIOFLG_0,GIO flag for pins GIOA[7:0]"
|
|
line.long 0x24 "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
|
|
hexmask.long 0x24 6.--31. 1. "NU1,Reserved"
|
|
hexmask.long.byte 0x24 0.--5. 1. "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
|
|
line.long 0x28 "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
|
|
hexmask.long 0x28 6.--31. 1. "NU2,Reserved"
|
|
hexmask.long.byte 0x28 0.--5. 1. "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
|
|
line.long 0x2C "GIOEMUA,GIO emulation register A"
|
|
hexmask.long 0x2C 6.--31. 1. "NU3,Reserved"
|
|
hexmask.long.byte 0x2C 0.--5. 1. "GIOEMUA,GIO emulation register A"
|
|
line.long 0x30 "GIOEMUB,GIO emulation register B"
|
|
hexmask.long 0x30 6.--31. 1. "NU4,Reserved"
|
|
hexmask.long.byte 0x30 0.--5. 1. "GIOEMUB,GIO emulation register B"
|
|
line.long 0x34 "GIODIRA,GIO data direction of pins in Port A"
|
|
hexmask.long.tbyte 0x34 8.--31. 1. "NU5,Reserved"
|
|
hexmask.long.byte 0x34 0.--7. 1. "GIODIRA,GIO data direction of pins in Port A"
|
|
line.long 0x38 "GIODINA,GIO data input for pins in port A"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "NU11,Reserved"
|
|
hexmask.long.byte 0x38 0.--7. 1. "GIODINA,GIO data input for pins in port A"
|
|
line.long 0x3C "GIODOUTA,GIO data output for pins in port A"
|
|
hexmask.long.tbyte 0x3C 8.--31. 1. "NU17,Reserved"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "GIODOUTA,GIO data output for pins in port A"
|
|
line.long 0x40 "GIOSETA,GIO data set for port A"
|
|
hexmask.long.tbyte 0x40 8.--31. 1. "NU23,Reserved"
|
|
hexmask.long.byte 0x40 0.--7. 1. "GIODSETA,GIO data set for port A"
|
|
line.long 0x44 "GIOCLRA,GIO data clear for port A"
|
|
hexmask.long.tbyte 0x44 8.--31. 1. "NU29,Reserved"
|
|
hexmask.long.byte 0x44 0.--7. 1. "GIODCLRA,GIO data clear for port A"
|
|
line.long 0x48 "GIOPDRA,GIO open drain for port A"
|
|
hexmask.long.tbyte 0x48 8.--31. 1. "NU35,Reserved"
|
|
hexmask.long.byte 0x48 0.--7. 1. "GIOPDRA,GIO open drain for port A"
|
|
line.long 0x4C "GIOPULDISA,GIO pul disable for port A"
|
|
hexmask.long.tbyte 0x4C 8.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "GIOPULDISA,GIO pull disable for port A"
|
|
line.long 0x50 "GIOPSLA,GIO pul select for port A"
|
|
hexmask.long.tbyte 0x50 8.--31. 1. "NU35,Reserved"
|
|
hexmask.long.byte 0x50 0.--7. 1. "GIOPSLA,GIO pull select for port A"
|
|
line.long 0x54 "GIODIRB,GIO data direction of pins in Port B"
|
|
hexmask.long.tbyte 0x54 8.--31. 1. "NU6,Reserved"
|
|
hexmask.long.byte 0x54 0.--7. 1. "GIODIRB,GIO data direction of pins in Port B"
|
|
line.long 0x58 "GIODINB,GIO data input for pins in port B"
|
|
hexmask.long.tbyte 0x58 8.--31. 1. "NU12,Reserved"
|
|
hexmask.long.byte 0x58 0.--7. 1. "GIODINB,GIO data input for pins in port B"
|
|
line.long 0x5C "GIODOUTB,GIO data output for pins in port B"
|
|
hexmask.long.tbyte 0x5C 8.--31. 1. "NU18,Reserved"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "GIODOUTB,GIO data output for pins in port B"
|
|
line.long 0x60 "GIOSETB,GIO data set for port B"
|
|
hexmask.long.tbyte 0x60 8.--31. 1. "NU24,Reserved"
|
|
hexmask.long.byte 0x60 0.--7. 1. "GIODSETB,GIO data set for port B"
|
|
line.long 0x64 "GIOCLRB,GIO data clear for port B"
|
|
hexmask.long.tbyte 0x64 8.--31. 1. "NU30,Reserved"
|
|
hexmask.long.byte 0x64 0.--7. 1. "GIODCLRB,GIO data clear for port B"
|
|
line.long 0x68 "GIOPDRB,GIO open drain for port B"
|
|
hexmask.long.tbyte 0x68 8.--31. 1. "NU36,Reserved"
|
|
hexmask.long.byte 0x68 0.--7. 1. "GIOPDRB,GIO open drain for port B"
|
|
line.long 0x6C "GIOPULDISB,GIO pul disable for port B"
|
|
hexmask.long.tbyte 0x6C 8.--31. 1. "NU36,Reserved"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "GIOPULDISB,GIO pull disable for port B"
|
|
line.long 0x70 "GIOPSLB,GIO pul select for port B"
|
|
hexmask.long.tbyte 0x70 8.--31. 1. "NU36,Reserved"
|
|
hexmask.long.byte 0x70 0.--7. 1. "GIOPSLB,GIO pull select for port B"
|
|
line.long 0x74 "GIODIRC,GIO data direction of pins in Port C"
|
|
hexmask.long.tbyte 0x74 8.--31. 1. "NU7,Reserved"
|
|
hexmask.long.byte 0x74 0.--7. 1. "GIODIRC,GIO data direction of pins in Port C"
|
|
line.long 0x78 "GIODINC,GIO data input for pins in port C"
|
|
hexmask.long.tbyte 0x78 8.--31. 1. "NU13,Reserved"
|
|
hexmask.long.byte 0x78 0.--7. 1. "GIODINC,GIO data input for pins in port C"
|
|
line.long 0x7C "GIODOUTC,GIO data output for pins in port C"
|
|
hexmask.long.tbyte 0x7C 8.--31. 1. "NU19,Reserved"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "GIODOUTC,GIO data output for pins in port C"
|
|
line.long 0x80 "GIOSETC,GIO data set for port C"
|
|
hexmask.long.tbyte 0x80 8.--31. 1. "NU25,Reserved"
|
|
hexmask.long.byte 0x80 0.--7. 1. "GIODSETC,GIO data set for port C"
|
|
line.long 0x84 "GIOCLRC,GIO data clear for port C"
|
|
hexmask.long.tbyte 0x84 8.--31. 1. "NU31,Reserved"
|
|
hexmask.long.byte 0x84 0.--7. 1. "GIODCLRC,GIO data clear for port C"
|
|
line.long 0x88 "GIOPDRC,GIO open drain for port C"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "NU37,Reserved"
|
|
hexmask.long.byte 0x88 0.--7. 1. "GIOPDRC,GIO open drain for port C"
|
|
line.long 0x8C "GIOPULDISC,GIO pul disable for port C"
|
|
hexmask.long.tbyte 0x8C 8.--31. 1. "NU37,Reserved"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "GIOPULDISC,GIO pull disable for port C"
|
|
line.long 0x90 "GIOPSLC,GIO pul select for port C"
|
|
hexmask.long.tbyte 0x90 8.--31. 1. "NU37,Reserved"
|
|
hexmask.long.byte 0x90 0.--7. 1. "GIOPSLC,GIO pull select for port C"
|
|
line.long 0x94 "GIODIRD,GIO data direction of pins in Port D"
|
|
hexmask.long.tbyte 0x94 8.--31. 1. "NU8,Reserved"
|
|
hexmask.long.byte 0x94 0.--7. 1. "GIODIRD,GIO data direction of pins in Port D"
|
|
line.long 0x98 "GIODIND,GIO data input for pins in port D"
|
|
hexmask.long.tbyte 0x98 8.--31. 1. "NU14,Reserved"
|
|
hexmask.long.byte 0x98 0.--7. 1. "GIODIND,GIO data input for pins in port D"
|
|
line.long 0x9C "GIODOUTD,GIO data output for pins in port D"
|
|
hexmask.long.tbyte 0x9C 8.--31. 1. "NU20,Reserved"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "GIODOUTD,GIO data output for pins in port D"
|
|
line.long 0xA0 "GIOSETD,GIO data set for port D"
|
|
hexmask.long.tbyte 0xA0 8.--31. 1. "NU26,Reserved"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "GIODSETD,GIO data set for port D"
|
|
line.long 0xA4 "GIOCLRD,GIO data clear for port D"
|
|
hexmask.long.tbyte 0xA4 8.--31. 1. "NU32,Reserved"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "GIODCLRD,GIO data clear for port D"
|
|
line.long 0xA8 "GIOPDRD,GIO open drain for port D"
|
|
hexmask.long.tbyte 0xA8 8.--31. 1. "NU38,Reserved"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "GIOPDRD,GIO open drain for port D"
|
|
line.long 0xAC "GIOPULDISD,GIO pul disable for port D"
|
|
hexmask.long.tbyte 0xAC 8.--31. 1. "NU38,Reserved"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "GIOPULDISD,GIO pull disable for port D"
|
|
line.long 0xB0 "GIOPSLD,GIO pul select for port D"
|
|
hexmask.long.tbyte 0xB0 8.--31. 1. "NU38,Reserved"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "GIOPSLD,GIO pull select for port D"
|
|
line.long 0xB4 "GIODIRE,GIO data direction of pins in Port E"
|
|
hexmask.long.tbyte 0xB4 8.--31. 1. "NU9,Reserved"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "GIODIRE,GIO data direction of pins in Port E"
|
|
line.long 0xB8 "GIODINE,GIO data input for pins in port E"
|
|
hexmask.long.tbyte 0xB8 8.--31. 1. "NU15,Reserved"
|
|
hexmask.long.byte 0xB8 0.--7. 1. "GIODINE,GIO data input for pins in port E"
|
|
line.long 0xBC "GIODOUTE,GIO data output for pins in port E"
|
|
hexmask.long.tbyte 0xBC 8.--31. 1. "NU21,Reserved"
|
|
hexmask.long.byte 0xBC 0.--7. 1. "GIODOUTE,GIO data output for pins in port E"
|
|
line.long 0xC0 "GIOSETE,GIO data set for port E"
|
|
hexmask.long.tbyte 0xC0 8.--31. 1. "NU27,Reserved"
|
|
hexmask.long.byte 0xC0 0.--7. 1. "GIODSETE,GIO data set for port E"
|
|
line.long 0xC4 "GIOCLRE,GIO data clear for port E"
|
|
hexmask.long.tbyte 0xC4 8.--31. 1. "NU33,Reserved"
|
|
hexmask.long.byte 0xC4 0.--7. 1. "GIODCLRE,GIO data clear for port E"
|
|
line.long 0xC8 "GIOPDRE,GIO open drain for port E"
|
|
hexmask.long.tbyte 0xC8 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0xC8 0.--7. 1. "GIOPDRE,GIO open drain for port E"
|
|
line.long 0xCC "GIOPULDISE,GIO pul disable for port E"
|
|
hexmask.long.tbyte 0xCC 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0xCC 0.--7. 1. "GIOPULDISE,GIO pull disable for port E"
|
|
line.long 0xD0 "GIOPSLE,GIO pul select for port E"
|
|
hexmask.long.tbyte 0xD0 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0xD0 0.--7. 1. "GIOPSLE,GIO pull select for port E"
|
|
line.long 0xD4 "GIODIRF,GIO data direction of pins in Port F"
|
|
hexmask.long.tbyte 0xD4 8.--31. 1. "NU10,Reserved"
|
|
hexmask.long.byte 0xD4 0.--7. 1. "GIODIRF,GIO data direction of pins in Port F"
|
|
line.long 0xD8 "GIODINF,GIO data input for pins in Port F"
|
|
hexmask.long.tbyte 0xD8 8.--31. 1. "NU16,Reserved"
|
|
hexmask.long.byte 0xD8 0.--7. 1. "GIODINF,GIO data input for pins in port F"
|
|
line.long 0xDC "GIODOUTF,GIO data output for pins in Port F"
|
|
hexmask.long.tbyte 0xDC 8.--31. 1. "NU22,Reserved"
|
|
hexmask.long.byte 0xDC 0.--7. 1. "GIODOUTF,GIO data output for pins in port F"
|
|
line.long 0xE0 "GIOSETF,GIO data set for Port F"
|
|
hexmask.long.tbyte 0xE0 8.--31. 1. "NU28,Reserved"
|
|
hexmask.long.byte 0xE0 0.--7. 1. "GIODSETF,GIO data set for port F"
|
|
line.long 0xE4 "GIOCLRF,GIO data clear for Port F"
|
|
hexmask.long.tbyte 0xE4 8.--31. 1. "NU34,Reserved"
|
|
hexmask.long.byte 0xE4 0.--7. 1. "GIODCLRF,GIO data clear for port F"
|
|
line.long 0xE8 "GIOPDRF,GIO open drain for Port F"
|
|
hexmask.long.tbyte 0xE8 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0xE8 0.--7. 1. "GIOPDRF,GIO open drain for port F"
|
|
line.long 0xEC "GIOPULDISF,GIO pul disable for port F"
|
|
hexmask.long.tbyte 0xEC 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0xEC 0.--7. 1. "GIOPULDISF,GIO pull disable for port F"
|
|
line.long 0xF0 "GIOPSLF,GIO pul select for port F"
|
|
hexmask.long.tbyte 0xF0 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0xF0 0.--7. 1. "GIOPSLF,GIO pull select for port F"
|
|
line.long 0xF4 "GIODIRG,GIO data direction of pins in Port G"
|
|
hexmask.long.tbyte 0xF4 8.--31. 1. "NU9,Reserved"
|
|
hexmask.long.byte 0xF4 0.--7. 1. "GIODIRG,GIO data direction of pins in Port G"
|
|
line.long 0xF8 "GIODING,GIO data input for pins in port G"
|
|
hexmask.long.tbyte 0xF8 8.--31. 1. "NU15,Reserved"
|
|
hexmask.long.byte 0xF8 0.--7. 1. "GIODING,GIO data input for pins in port G"
|
|
line.long 0xFC "GIODOUTG,GIO data output for pins in port G"
|
|
hexmask.long.tbyte 0xFC 8.--31. 1. "NU21,Reserved"
|
|
hexmask.long.byte 0xFC 0.--7. 1. "GIODOUTG,GIO data output for pins in port G"
|
|
line.long 0x100 "GIOSETG,GIO data set for port G"
|
|
hexmask.long.tbyte 0x100 8.--31. 1. "NU27,Reserved"
|
|
hexmask.long.byte 0x100 0.--7. 1. "GIODSETG,GIO data set for port G"
|
|
line.long 0x104 "GIOCLRG,GIO data clear for port G"
|
|
hexmask.long.tbyte 0x104 8.--31. 1. "NU33,Reserved"
|
|
hexmask.long.byte 0x104 0.--7. 1. "GIODCLRG,GIO data clear for port G"
|
|
line.long 0x108 "GIOPDRG,GIO open drain for port G"
|
|
hexmask.long.tbyte 0x108 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0x108 0.--7. 1. "GIOPDRG,GIO open drain for port G"
|
|
line.long 0x10C "GIOPULDISG,GIO pul disable for port G"
|
|
hexmask.long.tbyte 0x10C 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0x10C 0.--7. 1. "GIOPULDISG,GIO pull disable for port G"
|
|
line.long 0x110 "GIOPSLG,GIO pul select for port G"
|
|
hexmask.long.tbyte 0x110 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0x110 0.--7. 1. "GIOPSLG,GIO pull select for port G"
|
|
line.long 0x114 "GIODIRH,GIO data direction of pins in Port H"
|
|
hexmask.long.tbyte 0x114 8.--31. 1. "NU10,Reserved"
|
|
hexmask.long.byte 0x114 0.--7. 1. "GIODIRH,GIO data direction of pins in Port H"
|
|
line.long 0x118 "GIODINH,GIO data input for pins in Port H"
|
|
hexmask.long.tbyte 0x118 8.--31. 1. "NU16,Reserved"
|
|
hexmask.long.byte 0x118 0.--7. 1. "GIODINH,GIO data input for pins in port H"
|
|
line.long 0x11C "GIODOUTH,GIO data output for pins in Port H"
|
|
hexmask.long.tbyte 0x11C 8.--31. 1. "NU22,Reserved"
|
|
hexmask.long.byte 0x11C 0.--7. 1. "GIODOUTH,GIO data output for pins in port H"
|
|
line.long 0x120 "GIOSETH,GIO data set for Port H"
|
|
hexmask.long.tbyte 0x120 8.--31. 1. "NU28,Reserved"
|
|
hexmask.long.byte 0x120 0.--7. 1. "GIODSETH,GIO data set for port H"
|
|
line.long 0x124 "GIOCLRH,GIO data clear for Port H"
|
|
hexmask.long.tbyte 0x124 8.--31. 1. "NU34,Reserved"
|
|
hexmask.long.byte 0x124 0.--7. 1. "GIODCLRH,GIO data clear for port H"
|
|
line.long 0x128 "GIOPDRH,GIO open drain for Port H"
|
|
hexmask.long.tbyte 0x128 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0x128 0.--7. 1. "GIOPDRH,GIO open drain for port H"
|
|
line.long 0x12C "GIOPULDISH,GIO pul disable for port H"
|
|
hexmask.long.tbyte 0x12C 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0x12C 0.--7. 1. "GIOPULDISH,GIO pull disable for port H"
|
|
line.long 0x130 "GIOPSLH,GIO pul select for port H"
|
|
hexmask.long.tbyte 0x130 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0x130 0.--7. 1. "GIOPSLH,GIO pull select for port H"
|
|
line.long 0x134 "GIOSRCA,GIO slew rate select for port A"
|
|
hexmask.long.tbyte 0x134 8.--31. 1. "NU35,Reserved"
|
|
hexmask.long.byte 0x134 0.--7. 1. "GIOSRCA,GIO slew rate control for port A"
|
|
line.long 0x138 "GIOSRCB,GIO slew rate select for port B"
|
|
hexmask.long.tbyte 0x138 8.--31. 1. "NU36,Reserved"
|
|
hexmask.long.byte 0x138 0.--7. 1. "GIOSRCB,GIO slew rate control for port B"
|
|
line.long 0x13C "GIOSRCC,GIO slew rate select for port C"
|
|
hexmask.long.tbyte 0x13C 8.--31. 1. "NU37,Reserved"
|
|
hexmask.long.byte 0x13C 0.--7. 1. "GIOSRCC,GIO slew rate control for port C"
|
|
line.long 0x140 "GIOSRCD,GIO slew rate select for port D"
|
|
hexmask.long.tbyte 0x140 8.--31. 1. "NU38,Reserved"
|
|
hexmask.long.byte 0x140 0.--7. 1. "GIOSRCD,GIO slew rate control for port D"
|
|
line.long 0x144 "GIOSRCE,GIO slew rate select for port E"
|
|
hexmask.long.tbyte 0x144 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0x144 0.--7. 1. "GIOSRCE,GIO slew rate control for port E"
|
|
line.long 0x148 "GIOSRCF,GIO slew rate select for port F"
|
|
hexmask.long.tbyte 0x148 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0x148 0.--7. 1. "GIOSRCF,GIO slew rate control for port F"
|
|
line.long 0x14C "GIOSRCG,GIO slew rate select for port G"
|
|
hexmask.long.tbyte 0x14C 8.--31. 1. "NU39,Reserved"
|
|
hexmask.long.byte 0x14C 0.--7. 1. "GIOSRCG,GIO slew rate control for port G"
|
|
line.long 0x150 "GIOSRCH,GIO slew rate select for port H"
|
|
hexmask.long.tbyte 0x150 8.--31. 1. "NU40,Reserved"
|
|
hexmask.long.byte 0x150 0.--7. 1. "GIOSRCH,GIO slew rate control for port H"
|
|
tree.end
|
|
tree "MSS_GPADC_DATA_RAM"
|
|
base ad:0xC5030000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "START,"
|
|
hexmask.long 0x0 0.--31. 1. "start,Memory start address"
|
|
group.long 0x7FC++0x3
|
|
line.long 0x0 "END,"
|
|
hexmask.long 0x0 0.--31. 1. "end,Memory end address"
|
|
tree.end
|
|
tree "MSS_GPADC_PKT_RAM"
|
|
base ad:0x30C0000
|
|
group.long 0x0++0x7FF
|
|
line.long 0x0 "INST0_0,"
|
|
hexmask.long 0x0 0.--31. 1. "CONFIG_VALUE,configuration value to be passed to analog"
|
|
line.long 0x4 "INST0_1,"
|
|
hexmask.long.byte 0x4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4 24. "NU1,1:Continue tests from the next instruction for the next chirp with the same profile" "?,1: Continue tests from the next instruction for the.."
|
|
bitfld.long 0x4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SKIP_SAMPLES,Number of GPADC clock cycles to skip before collecting valid samples"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "COLLECT_SAMPLES,Number of GPADC samples to collect"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PARAM,Parameter(input to one hot encoding) to be passed to analog"
|
|
line.long 0x8 "INST1_0,"
|
|
hexmask.long 0x8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xC "INST1_1,"
|
|
hexmask.long.byte 0xC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xC 24. "NU1," "0,1"
|
|
bitfld.long 0xC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PARAM,"
|
|
line.long 0x10 "INST2_0,"
|
|
hexmask.long 0x10 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x14 "INST2_1,"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x14 24. "NU1," "0,1"
|
|
bitfld.long 0x14 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x14 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PARAM,"
|
|
line.long 0x18 "INST3_0,"
|
|
hexmask.long 0x18 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1C "INST3_1,"
|
|
hexmask.long.byte 0x1C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1C 24. "NU1," "0,1"
|
|
bitfld.long 0x1C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PARAM,"
|
|
line.long 0x20 "INST4_0,"
|
|
hexmask.long 0x20 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x24 "INST4_1,"
|
|
hexmask.long.byte 0x24 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x24 24. "NU1," "0,1"
|
|
bitfld.long 0x24 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x24 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x24 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PARAM,"
|
|
line.long 0x28 "INST5_0,"
|
|
hexmask.long 0x28 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2C "INST5_1,"
|
|
hexmask.long.byte 0x2C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2C 24. "NU1," "0,1"
|
|
bitfld.long 0x2C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PARAM,"
|
|
line.long 0x30 "INST6_0,"
|
|
hexmask.long 0x30 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x34 "INST6_1,"
|
|
hexmask.long.byte 0x34 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x34 24. "NU1," "0,1"
|
|
bitfld.long 0x34 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x34 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x34 0.--7. 1. "PARAM,"
|
|
line.long 0x38 "INST7_0,"
|
|
hexmask.long 0x38 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3C "INST7_1,"
|
|
hexmask.long.byte 0x3C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3C 24. "NU1," "0,1"
|
|
bitfld.long 0x3C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3C 0.--7. 1. "PARAM,"
|
|
line.long 0x40 "INST8_0,"
|
|
hexmask.long 0x40 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x44 "INST8_1,"
|
|
hexmask.long.byte 0x44 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x44 24. "NU1," "0,1"
|
|
bitfld.long 0x44 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x44 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x44 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PARAM,"
|
|
line.long 0x48 "INST9_0,"
|
|
hexmask.long 0x48 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4C "INST9_1,"
|
|
hexmask.long.byte 0x4C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4C 24. "NU1," "0,1"
|
|
bitfld.long 0x4C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4C 0.--7. 1. "PARAM,"
|
|
line.long 0x50 "INST10_0,"
|
|
hexmask.long 0x50 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x54 "INST10_1,"
|
|
hexmask.long.byte 0x54 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x54 24. "NU1," "0,1"
|
|
bitfld.long 0x54 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x54 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x54 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x54 0.--7. 1. "PARAM,"
|
|
line.long 0x58 "INST11_0,"
|
|
hexmask.long 0x58 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5C "INST11_1,"
|
|
hexmask.long.byte 0x5C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5C 24. "NU1," "0,1"
|
|
bitfld.long 0x5C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5C 0.--7. 1. "PARAM,"
|
|
line.long 0x60 "INST12_0,"
|
|
hexmask.long 0x60 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x64 "INST12_1,"
|
|
hexmask.long.byte 0x64 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x64 24. "NU1," "0,1"
|
|
bitfld.long 0x64 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x64 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x64 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x64 0.--7. 1. "PARAM,"
|
|
line.long 0x68 "INST13_0,"
|
|
hexmask.long 0x68 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6C "INST13_1,"
|
|
hexmask.long.byte 0x6C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6C 24. "NU1," "0,1"
|
|
bitfld.long 0x6C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6C 0.--7. 1. "PARAM,"
|
|
line.long 0x70 "INST14_0,"
|
|
hexmask.long 0x70 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x74 "INST14_1,"
|
|
hexmask.long.byte 0x74 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x74 24. "NU1," "0,1"
|
|
bitfld.long 0x74 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x74 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x74 0.--7. 1. "PARAM,"
|
|
line.long 0x78 "INST15_0,"
|
|
hexmask.long 0x78 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7C "INST15_1,"
|
|
hexmask.long.byte 0x7C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7C 24. "NU1," "0,1"
|
|
bitfld.long 0x7C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "PARAM,"
|
|
line.long 0x80 "INST16_0,"
|
|
hexmask.long 0x80 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x84 "INST16_1,"
|
|
hexmask.long.byte 0x84 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x84 24. "NU1," "0,1"
|
|
bitfld.long 0x84 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x84 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x84 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x84 0.--7. 1. "PARAM,"
|
|
line.long 0x88 "INST17_0,"
|
|
hexmask.long 0x88 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x8C "INST17_1,"
|
|
hexmask.long.byte 0x8C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x8C 24. "NU1," "0,1"
|
|
bitfld.long 0x8C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x8C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x8C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "PARAM,"
|
|
line.long 0x90 "INST18_0,"
|
|
hexmask.long 0x90 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x94 "INST18_1,"
|
|
hexmask.long.byte 0x94 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x94 24. "NU1," "0,1"
|
|
bitfld.long 0x94 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x94 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x94 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x94 0.--7. 1. "PARAM,"
|
|
line.long 0x98 "INST19_0,"
|
|
hexmask.long 0x98 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x9C "INST19_1,"
|
|
hexmask.long.byte 0x9C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x9C 24. "NU1," "0,1"
|
|
bitfld.long 0x9C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x9C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x9C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "PARAM,"
|
|
line.long 0xA0 "INST20_0,"
|
|
hexmask.long 0xA0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xA4 "INST20_1,"
|
|
hexmask.long.byte 0xA4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xA4 24. "NU1," "0,1"
|
|
bitfld.long 0xA4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xA4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xA4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "PARAM,"
|
|
line.long 0xA8 "INST21_0,"
|
|
hexmask.long 0xA8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xAC "INST21_1,"
|
|
hexmask.long.byte 0xAC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xAC 24. "NU1," "0,1"
|
|
bitfld.long 0xAC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xAC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xAC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "PARAM,"
|
|
line.long 0xB0 "INST22_0,"
|
|
hexmask.long 0xB0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xB4 "INST22_1,"
|
|
hexmask.long.byte 0xB4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xB4 24. "NU1," "0,1"
|
|
bitfld.long 0xB4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xB4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xB4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "PARAM,"
|
|
line.long 0xB8 "INST23_0,"
|
|
hexmask.long 0xB8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xBC "INST23_1,"
|
|
hexmask.long.byte 0xBC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xBC 24. "NU1," "0,1"
|
|
bitfld.long 0xBC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xBC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xBC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xBC 0.--7. 1. "PARAM,"
|
|
line.long 0xC0 "INST24_0,"
|
|
hexmask.long 0xC0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xC4 "INST24_1,"
|
|
hexmask.long.byte 0xC4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xC4 24. "NU1," "0,1"
|
|
bitfld.long 0xC4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xC4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xC4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xC4 0.--7. 1. "PARAM,"
|
|
line.long 0xC8 "INST25_0,"
|
|
hexmask.long 0xC8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xCC "INST25_1,"
|
|
hexmask.long.byte 0xCC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xCC 24. "NU1," "0,1"
|
|
bitfld.long 0xCC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xCC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xCC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xCC 0.--7. 1. "PARAM,"
|
|
line.long 0xD0 "INST26_0,"
|
|
hexmask.long 0xD0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xD4 "INST26_1,"
|
|
hexmask.long.byte 0xD4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xD4 24. "NU1," "0,1"
|
|
bitfld.long 0xD4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xD4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xD4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xD4 0.--7. 1. "PARAM,"
|
|
line.long 0xD8 "INST27_0,"
|
|
hexmask.long 0xD8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xDC "INST27_1,"
|
|
hexmask.long.byte 0xDC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xDC 24. "NU1," "0,1"
|
|
bitfld.long 0xDC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xDC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xDC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xDC 0.--7. 1. "PARAM,"
|
|
line.long 0xE0 "INST28_0,"
|
|
hexmask.long 0xE0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xE4 "INST28_1,"
|
|
hexmask.long.byte 0xE4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xE4 24. "NU1," "0,1"
|
|
bitfld.long 0xE4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xE4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xE4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xE4 0.--7. 1. "PARAM,"
|
|
line.long 0xE8 "INST29_0,"
|
|
hexmask.long 0xE8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xEC "INST29_1,"
|
|
hexmask.long.byte 0xEC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xEC 24. "NU1," "0,1"
|
|
bitfld.long 0xEC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xEC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xEC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xEC 0.--7. 1. "PARAM,"
|
|
line.long 0xF0 "INST30_0,"
|
|
hexmask.long 0xF0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xF4 "INST30_1,"
|
|
hexmask.long.byte 0xF4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xF4 24. "NU1," "0,1"
|
|
bitfld.long 0xF4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xF4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xF4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xF4 0.--7. 1. "PARAM,"
|
|
line.long 0xF8 "INST31_0,"
|
|
hexmask.long 0xF8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0xFC "INST31_1,"
|
|
hexmask.long.byte 0xFC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0xFC 24. "NU1," "0,1"
|
|
bitfld.long 0xFC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0xFC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0xFC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0xFC 0.--7. 1. "PARAM,"
|
|
line.long 0x100 "INST32_0,"
|
|
hexmask.long 0x100 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x104 "INST32_1,"
|
|
hexmask.long.byte 0x104 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x104 24. "NU1," "0,1"
|
|
bitfld.long 0x104 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x104 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x104 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x104 0.--7. 1. "PARAM,"
|
|
line.long 0x108 "INST33_0,"
|
|
hexmask.long 0x108 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x10C "INST33_1,"
|
|
hexmask.long.byte 0x10C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x10C 24. "NU1," "0,1"
|
|
bitfld.long 0x10C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x10C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x10C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x10C 0.--7. 1. "PARAM,"
|
|
line.long 0x110 "INST34_0,"
|
|
hexmask.long 0x110 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x114 "INST34_1,"
|
|
hexmask.long.byte 0x114 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x114 24. "NU1," "0,1"
|
|
bitfld.long 0x114 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x114 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x114 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x114 0.--7. 1. "PARAM,"
|
|
line.long 0x118 "INST35_0,"
|
|
hexmask.long 0x118 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x11C "INST35_1,"
|
|
hexmask.long.byte 0x11C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x11C 24. "NU1," "0,1"
|
|
bitfld.long 0x11C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x11C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x11C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x11C 0.--7. 1. "PARAM,"
|
|
line.long 0x120 "INST36_0,"
|
|
hexmask.long 0x120 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x124 "INST36_1,"
|
|
hexmask.long.byte 0x124 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x124 24. "NU1," "0,1"
|
|
bitfld.long 0x124 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x124 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x124 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x124 0.--7. 1. "PARAM,"
|
|
line.long 0x128 "INST37_0,"
|
|
hexmask.long 0x128 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x12C "INST37_1,"
|
|
hexmask.long.byte 0x12C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x12C 24. "NU1," "0,1"
|
|
bitfld.long 0x12C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x12C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x12C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x12C 0.--7. 1. "PARAM,"
|
|
line.long 0x130 "INST38_0,"
|
|
hexmask.long 0x130 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x134 "INST38_1,"
|
|
hexmask.long.byte 0x134 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x134 24. "NU1," "0,1"
|
|
bitfld.long 0x134 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x134 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x134 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x134 0.--7. 1. "PARAM,"
|
|
line.long 0x138 "INST39_0,"
|
|
hexmask.long 0x138 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x13C "INST39_1,"
|
|
hexmask.long.byte 0x13C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x13C 24. "NU1," "0,1"
|
|
bitfld.long 0x13C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x13C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x13C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x13C 0.--7. 1. "PARAM,"
|
|
line.long 0x140 "INST40_0,"
|
|
hexmask.long 0x140 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x144 "INST40_1,"
|
|
hexmask.long.byte 0x144 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x144 24. "NU1," "0,1"
|
|
bitfld.long 0x144 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x144 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x144 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x144 0.--7. 1. "PARAM,"
|
|
line.long 0x148 "INST41_0,"
|
|
hexmask.long 0x148 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x14C "INST41_1,"
|
|
hexmask.long.byte 0x14C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x14C 24. "NU1," "0,1"
|
|
bitfld.long 0x14C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x14C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x14C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x14C 0.--7. 1. "PARAM,"
|
|
line.long 0x150 "INST42_0,"
|
|
hexmask.long 0x150 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x154 "INST42_1,"
|
|
hexmask.long.byte 0x154 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x154 24. "NU1," "0,1"
|
|
bitfld.long 0x154 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x154 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x154 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x154 0.--7. 1. "PARAM,"
|
|
line.long 0x158 "INST43_0,"
|
|
hexmask.long 0x158 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x15C "INST43_1,"
|
|
hexmask.long.byte 0x15C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x15C 24. "NU1," "0,1"
|
|
bitfld.long 0x15C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x15C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x15C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x15C 0.--7. 1. "PARAM,"
|
|
line.long 0x160 "INST44_0,"
|
|
hexmask.long 0x160 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x164 "INST44_1,"
|
|
hexmask.long.byte 0x164 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x164 24. "NU1," "0,1"
|
|
bitfld.long 0x164 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x164 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x164 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x164 0.--7. 1. "PARAM,"
|
|
line.long 0x168 "INST45_0,"
|
|
hexmask.long 0x168 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x16C "INST45_1,"
|
|
hexmask.long.byte 0x16C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x16C 24. "NU1," "0,1"
|
|
bitfld.long 0x16C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x16C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x16C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x16C 0.--7. 1. "PARAM,"
|
|
line.long 0x170 "INST46_0,"
|
|
hexmask.long 0x170 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x174 "INST46_1,"
|
|
hexmask.long.byte 0x174 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x174 24. "NU1," "0,1"
|
|
bitfld.long 0x174 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x174 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x174 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x174 0.--7. 1. "PARAM,"
|
|
line.long 0x178 "INST47_0,"
|
|
hexmask.long 0x178 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x17C "INST47_1,"
|
|
hexmask.long.byte 0x17C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x17C 24. "NU1," "0,1"
|
|
bitfld.long 0x17C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x17C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x17C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x17C 0.--7. 1. "PARAM,"
|
|
line.long 0x180 "INST48_0,"
|
|
hexmask.long 0x180 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x184 "INST48_1,"
|
|
hexmask.long.byte 0x184 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x184 24. "NU1," "0,1"
|
|
bitfld.long 0x184 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x184 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x184 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x184 0.--7. 1. "PARAM,"
|
|
line.long 0x188 "INST49_0,"
|
|
hexmask.long 0x188 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x18C "INST49_1,"
|
|
hexmask.long.byte 0x18C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x18C 24. "NU1," "0,1"
|
|
bitfld.long 0x18C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x18C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x18C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x18C 0.--7. 1. "PARAM,"
|
|
line.long 0x190 "INST50_0,"
|
|
hexmask.long 0x190 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x194 "INST50_1,"
|
|
hexmask.long.byte 0x194 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x194 24. "NU1," "0,1"
|
|
bitfld.long 0x194 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x194 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x194 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x194 0.--7. 1. "PARAM,"
|
|
line.long 0x198 "INST51_0,"
|
|
hexmask.long 0x198 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x19C "INST51_1,"
|
|
hexmask.long.byte 0x19C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x19C 24. "NU1," "0,1"
|
|
bitfld.long 0x19C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x19C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x19C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x19C 0.--7. 1. "PARAM,"
|
|
line.long 0x1A0 "INST52_0,"
|
|
hexmask.long 0x1A0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1A4 "INST52_1,"
|
|
hexmask.long.byte 0x1A4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1A4 24. "NU1," "0,1"
|
|
bitfld.long 0x1A4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1A4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1A4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1A4 0.--7. 1. "PARAM,"
|
|
line.long 0x1A8 "INST53_0,"
|
|
hexmask.long 0x1A8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1AC "INST53_1,"
|
|
hexmask.long.byte 0x1AC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1AC 24. "NU1," "0,1"
|
|
bitfld.long 0x1AC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1AC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1AC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1AC 0.--7. 1. "PARAM,"
|
|
line.long 0x1B0 "INST54_0,"
|
|
hexmask.long 0x1B0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1B4 "INST54_1,"
|
|
hexmask.long.byte 0x1B4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1B4 24. "NU1," "0,1"
|
|
bitfld.long 0x1B4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1B4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1B4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1B4 0.--7. 1. "PARAM,"
|
|
line.long 0x1B8 "INST55_0,"
|
|
hexmask.long 0x1B8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1BC "INST55_1,"
|
|
hexmask.long.byte 0x1BC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1BC 24. "NU1," "0,1"
|
|
bitfld.long 0x1BC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1BC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1BC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1BC 0.--7. 1. "PARAM,"
|
|
line.long 0x1C0 "INST56_0,"
|
|
hexmask.long 0x1C0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1C4 "INST56_1,"
|
|
hexmask.long.byte 0x1C4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1C4 24. "NU1," "0,1"
|
|
bitfld.long 0x1C4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1C4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1C4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1C4 0.--7. 1. "PARAM,"
|
|
line.long 0x1C8 "INST57_0,"
|
|
hexmask.long 0x1C8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1CC "INST57_1,"
|
|
hexmask.long.byte 0x1CC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1CC 24. "NU1," "0,1"
|
|
bitfld.long 0x1CC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1CC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1CC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1CC 0.--7. 1. "PARAM,"
|
|
line.long 0x1D0 "INST58_0,"
|
|
hexmask.long 0x1D0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1D4 "INST58_1,"
|
|
hexmask.long.byte 0x1D4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1D4 24. "NU1," "0,1"
|
|
bitfld.long 0x1D4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1D4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1D4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1D4 0.--7. 1. "PARAM,"
|
|
line.long 0x1D8 "INST59_0,"
|
|
hexmask.long 0x1D8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1DC "INST59_1,"
|
|
hexmask.long.byte 0x1DC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1DC 24. "NU1," "0,1"
|
|
bitfld.long 0x1DC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1DC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1DC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1DC 0.--7. 1. "PARAM,"
|
|
line.long 0x1E0 "INST60_0,"
|
|
hexmask.long 0x1E0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1E4 "INST60_1,"
|
|
hexmask.long.byte 0x1E4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1E4 24. "NU1," "0,1"
|
|
bitfld.long 0x1E4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1E4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1E4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1E4 0.--7. 1. "PARAM,"
|
|
line.long 0x1E8 "INST61_0,"
|
|
hexmask.long 0x1E8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1EC "INST61_1,"
|
|
hexmask.long.byte 0x1EC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1EC 24. "NU1," "0,1"
|
|
bitfld.long 0x1EC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1EC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1EC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1EC 0.--7. 1. "PARAM,"
|
|
line.long 0x1F0 "INST62_0,"
|
|
hexmask.long 0x1F0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1F4 "INST62_1,"
|
|
hexmask.long.byte 0x1F4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1F4 24. "NU1," "0,1"
|
|
bitfld.long 0x1F4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1F4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1F4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1F4 0.--7. 1. "PARAM,"
|
|
line.long 0x1F8 "INST63_0,"
|
|
hexmask.long 0x1F8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x1FC "INST63_1,"
|
|
hexmask.long.byte 0x1FC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x1FC 24. "NU1," "0,1"
|
|
bitfld.long 0x1FC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x1FC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x1FC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x1FC 0.--7. 1. "PARAM,"
|
|
line.long 0x200 "INST64_0,"
|
|
hexmask.long 0x200 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x204 "INST64_1,"
|
|
hexmask.long.byte 0x204 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x204 24. "NU1," "0,1"
|
|
bitfld.long 0x204 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x204 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x204 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x204 0.--7. 1. "PARAM,"
|
|
line.long 0x208 "INST65_0,"
|
|
hexmask.long 0x208 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x20C "INST65_1,"
|
|
hexmask.long.byte 0x20C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x20C 24. "NU1," "0,1"
|
|
bitfld.long 0x20C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x20C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x20C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x20C 0.--7. 1. "PARAM,"
|
|
line.long 0x210 "INST66_0,"
|
|
hexmask.long 0x210 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x214 "INST66_1,"
|
|
hexmask.long.byte 0x214 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x214 24. "NU1," "0,1"
|
|
bitfld.long 0x214 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x214 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x214 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x214 0.--7. 1. "PARAM,"
|
|
line.long 0x218 "INST67_0,"
|
|
hexmask.long 0x218 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x21C "INST67_1,"
|
|
hexmask.long.byte 0x21C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x21C 24. "NU1," "0,1"
|
|
bitfld.long 0x21C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x21C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x21C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x21C 0.--7. 1. "PARAM,"
|
|
line.long 0x220 "INST68_0,"
|
|
hexmask.long 0x220 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x224 "INST68_1,"
|
|
hexmask.long.byte 0x224 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x224 24. "NU1," "0,1"
|
|
bitfld.long 0x224 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x224 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x224 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x224 0.--7. 1. "PARAM,"
|
|
line.long 0x228 "INST69_0,"
|
|
hexmask.long 0x228 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x22C "INST69_1,"
|
|
hexmask.long.byte 0x22C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x22C 24. "NU1," "0,1"
|
|
bitfld.long 0x22C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x22C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x22C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x22C 0.--7. 1. "PARAM,"
|
|
line.long 0x230 "INST70_0,"
|
|
hexmask.long 0x230 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x234 "INST70_1,"
|
|
hexmask.long.byte 0x234 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x234 24. "NU1," "0,1"
|
|
bitfld.long 0x234 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x234 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x234 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x234 0.--7. 1. "PARAM,"
|
|
line.long 0x238 "INST71_0,"
|
|
hexmask.long 0x238 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x23C "INST71_1,"
|
|
hexmask.long.byte 0x23C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x23C 24. "NU1," "0,1"
|
|
bitfld.long 0x23C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x23C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x23C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x23C 0.--7. 1. "PARAM,"
|
|
line.long 0x240 "INST72_0,"
|
|
hexmask.long 0x240 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x244 "INST72_1,"
|
|
hexmask.long.byte 0x244 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x244 24. "NU1," "0,1"
|
|
bitfld.long 0x244 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x244 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x244 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x244 0.--7. 1. "PARAM,"
|
|
line.long 0x248 "INST73_0,"
|
|
hexmask.long 0x248 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x24C "INST73_1,"
|
|
hexmask.long.byte 0x24C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x24C 24. "NU1," "0,1"
|
|
bitfld.long 0x24C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x24C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x24C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x24C 0.--7. 1. "PARAM,"
|
|
line.long 0x250 "INST74_0,"
|
|
hexmask.long 0x250 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x254 "INST74_1,"
|
|
hexmask.long.byte 0x254 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x254 24. "NU1," "0,1"
|
|
bitfld.long 0x254 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x254 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x254 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x254 0.--7. 1. "PARAM,"
|
|
line.long 0x258 "INST75_0,"
|
|
hexmask.long 0x258 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x25C "INST75_1,"
|
|
hexmask.long.byte 0x25C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x25C 24. "NU1," "0,1"
|
|
bitfld.long 0x25C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x25C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x25C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x25C 0.--7. 1. "PARAM,"
|
|
line.long 0x260 "INST76_0,"
|
|
hexmask.long 0x260 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x264 "INST76_1,"
|
|
hexmask.long.byte 0x264 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x264 24. "NU1," "0,1"
|
|
bitfld.long 0x264 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x264 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x264 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x264 0.--7. 1. "PARAM,"
|
|
line.long 0x268 "INST77_0,"
|
|
hexmask.long 0x268 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x26C "INST77_1,"
|
|
hexmask.long.byte 0x26C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x26C 24. "NU1," "0,1"
|
|
bitfld.long 0x26C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x26C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x26C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x26C 0.--7. 1. "PARAM,"
|
|
line.long 0x270 "INST78_0,"
|
|
hexmask.long 0x270 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x274 "INST78_1,"
|
|
hexmask.long.byte 0x274 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x274 24. "NU1," "0,1"
|
|
bitfld.long 0x274 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x274 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x274 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x274 0.--7. 1. "PARAM,"
|
|
line.long 0x278 "INST79_0,"
|
|
hexmask.long 0x278 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x27C "INST79_1,"
|
|
hexmask.long.byte 0x27C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x27C 24. "NU1," "0,1"
|
|
bitfld.long 0x27C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x27C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x27C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x27C 0.--7. 1. "PARAM,"
|
|
line.long 0x280 "INST80_0,"
|
|
hexmask.long 0x280 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x284 "INST80_1,"
|
|
hexmask.long.byte 0x284 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x284 24. "NU1," "0,1"
|
|
bitfld.long 0x284 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x284 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x284 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x284 0.--7. 1. "PARAM,"
|
|
line.long 0x288 "INST81_0,"
|
|
hexmask.long 0x288 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x28C "INST81_1,"
|
|
hexmask.long.byte 0x28C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x28C 24. "NU1," "0,1"
|
|
bitfld.long 0x28C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x28C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x28C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x28C 0.--7. 1. "PARAM,"
|
|
line.long 0x290 "INST82_0,"
|
|
hexmask.long 0x290 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x294 "INST82_1,"
|
|
hexmask.long.byte 0x294 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x294 24. "NU1," "0,1"
|
|
bitfld.long 0x294 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x294 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x294 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x294 0.--7. 1. "PARAM,"
|
|
line.long 0x298 "INST83_0,"
|
|
hexmask.long 0x298 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x29C "INST83_1,"
|
|
hexmask.long.byte 0x29C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x29C 24. "NU1," "0,1"
|
|
bitfld.long 0x29C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x29C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x29C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x29C 0.--7. 1. "PARAM,"
|
|
line.long 0x2A0 "INST84_0,"
|
|
hexmask.long 0x2A0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2A4 "INST84_1,"
|
|
hexmask.long.byte 0x2A4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2A4 24. "NU1," "0,1"
|
|
bitfld.long 0x2A4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2A4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2A4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2A4 0.--7. 1. "PARAM,"
|
|
line.long 0x2A8 "INST85_0,"
|
|
hexmask.long 0x2A8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2AC "INST85_1,"
|
|
hexmask.long.byte 0x2AC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2AC 24. "NU1," "0,1"
|
|
bitfld.long 0x2AC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2AC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2AC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2AC 0.--7. 1. "PARAM,"
|
|
line.long 0x2B0 "INST86_0,"
|
|
hexmask.long 0x2B0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2B4 "INST86_1,"
|
|
hexmask.long.byte 0x2B4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2B4 24. "NU1," "0,1"
|
|
bitfld.long 0x2B4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2B4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2B4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2B4 0.--7. 1. "PARAM,"
|
|
line.long 0x2B8 "INST87_0,"
|
|
hexmask.long 0x2B8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2BC "INST87_1,"
|
|
hexmask.long.byte 0x2BC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2BC 24. "NU1," "0,1"
|
|
bitfld.long 0x2BC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2BC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2BC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2BC 0.--7. 1. "PARAM,"
|
|
line.long 0x2C0 "INST88_0,"
|
|
hexmask.long 0x2C0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2C4 "INST88_1,"
|
|
hexmask.long.byte 0x2C4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2C4 24. "NU1," "0,1"
|
|
bitfld.long 0x2C4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2C4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2C4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2C4 0.--7. 1. "PARAM,"
|
|
line.long 0x2C8 "INST89_0,"
|
|
hexmask.long 0x2C8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2CC "INST89_1,"
|
|
hexmask.long.byte 0x2CC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2CC 24. "NU1," "0,1"
|
|
bitfld.long 0x2CC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2CC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2CC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2CC 0.--7. 1. "PARAM,"
|
|
line.long 0x2D0 "INST90_0,"
|
|
hexmask.long 0x2D0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2D4 "INST90_1,"
|
|
hexmask.long.byte 0x2D4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2D4 24. "NU1," "0,1"
|
|
bitfld.long 0x2D4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2D4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2D4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2D4 0.--7. 1. "PARAM,"
|
|
line.long 0x2D8 "INST91_0,"
|
|
hexmask.long 0x2D8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2DC "INST91_1,"
|
|
hexmask.long.byte 0x2DC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2DC 24. "NU1," "0,1"
|
|
bitfld.long 0x2DC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2DC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2DC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2DC 0.--7. 1. "PARAM,"
|
|
line.long 0x2E0 "INST92_0,"
|
|
hexmask.long 0x2E0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2E4 "INST92_1,"
|
|
hexmask.long.byte 0x2E4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2E4 24. "NU1," "0,1"
|
|
bitfld.long 0x2E4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2E4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2E4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2E4 0.--7. 1. "PARAM,"
|
|
line.long 0x2E8 "INST93_0,"
|
|
hexmask.long 0x2E8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2EC "INST93_1,"
|
|
hexmask.long.byte 0x2EC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2EC 24. "NU1," "0,1"
|
|
bitfld.long 0x2EC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2EC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2EC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2EC 0.--7. 1. "PARAM,"
|
|
line.long 0x2F0 "INST94_0,"
|
|
hexmask.long 0x2F0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2F4 "INST94_1,"
|
|
hexmask.long.byte 0x2F4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2F4 24. "NU1," "0,1"
|
|
bitfld.long 0x2F4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2F4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2F4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2F4 0.--7. 1. "PARAM,"
|
|
line.long 0x2F8 "INST95_0,"
|
|
hexmask.long 0x2F8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x2FC "INST95_1,"
|
|
hexmask.long.byte 0x2FC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x2FC 24. "NU1," "0,1"
|
|
bitfld.long 0x2FC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x2FC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x2FC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x2FC 0.--7. 1. "PARAM,"
|
|
line.long 0x300 "INST96_0,"
|
|
hexmask.long 0x300 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x304 "INST96_1,"
|
|
hexmask.long.byte 0x304 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x304 24. "NU1," "0,1"
|
|
bitfld.long 0x304 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x304 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x304 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x304 0.--7. 1. "PARAM,"
|
|
line.long 0x308 "INST97_0,"
|
|
hexmask.long 0x308 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x30C "INST97_1,"
|
|
hexmask.long.byte 0x30C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x30C 24. "NU1," "0,1"
|
|
bitfld.long 0x30C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x30C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x30C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x30C 0.--7. 1. "PARAM,"
|
|
line.long 0x310 "INST98_0,"
|
|
hexmask.long 0x310 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x314 "INST98_1,"
|
|
hexmask.long.byte 0x314 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x314 24. "NU1," "0,1"
|
|
bitfld.long 0x314 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x314 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x314 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x314 0.--7. 1. "PARAM,"
|
|
line.long 0x318 "INST99_0,"
|
|
hexmask.long 0x318 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x31C "INST99_1,"
|
|
hexmask.long.byte 0x31C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x31C 24. "NU1," "0,1"
|
|
bitfld.long 0x31C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x31C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x31C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x31C 0.--7. 1. "PARAM,"
|
|
line.long 0x320 "INST100_0,"
|
|
hexmask.long 0x320 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x324 "INST100_1,"
|
|
hexmask.long.byte 0x324 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x324 24. "NU1," "0,1"
|
|
bitfld.long 0x324 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x324 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x324 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x324 0.--7. 1. "PARAM,"
|
|
line.long 0x328 "INST101_0,"
|
|
hexmask.long 0x328 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x32C "INST101_1,"
|
|
hexmask.long.byte 0x32C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x32C 24. "NU1," "0,1"
|
|
bitfld.long 0x32C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x32C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x32C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x32C 0.--7. 1. "PARAM,"
|
|
line.long 0x330 "INST102_0,"
|
|
hexmask.long 0x330 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x334 "INST102_1,"
|
|
hexmask.long.byte 0x334 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x334 24. "NU1," "0,1"
|
|
bitfld.long 0x334 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x334 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x334 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x334 0.--7. 1. "PARAM,"
|
|
line.long 0x338 "INST103_0,"
|
|
hexmask.long 0x338 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x33C "INST103_1,"
|
|
hexmask.long.byte 0x33C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x33C 24. "NU1," "0,1"
|
|
bitfld.long 0x33C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x33C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x33C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x33C 0.--7. 1. "PARAM,"
|
|
line.long 0x340 "INST104_0,"
|
|
hexmask.long 0x340 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x344 "INST104_1,"
|
|
hexmask.long.byte 0x344 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x344 24. "NU1," "0,1"
|
|
bitfld.long 0x344 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x344 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x344 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x344 0.--7. 1. "PARAM,"
|
|
line.long 0x348 "INST105_0,"
|
|
hexmask.long 0x348 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x34C "INST105_1,"
|
|
hexmask.long.byte 0x34C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x34C 24. "NU1," "0,1"
|
|
bitfld.long 0x34C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x34C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x34C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x34C 0.--7. 1. "PARAM,"
|
|
line.long 0x350 "INST106_0,"
|
|
hexmask.long 0x350 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x354 "INST106_1,"
|
|
hexmask.long.byte 0x354 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x354 24. "NU1," "0,1"
|
|
bitfld.long 0x354 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x354 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x354 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x354 0.--7. 1. "PARAM,"
|
|
line.long 0x358 "INST107_0,"
|
|
hexmask.long 0x358 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x35C "INST107_1,"
|
|
hexmask.long.byte 0x35C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x35C 24. "NU1," "0,1"
|
|
bitfld.long 0x35C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x35C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x35C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x35C 0.--7. 1. "PARAM,"
|
|
line.long 0x360 "INST108_0,"
|
|
hexmask.long 0x360 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x364 "INST108_1,"
|
|
hexmask.long.byte 0x364 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x364 24. "NU1," "0,1"
|
|
bitfld.long 0x364 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x364 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x364 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x364 0.--7. 1. "PARAM,"
|
|
line.long 0x368 "INST109_0,"
|
|
hexmask.long 0x368 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x36C "INST109_1,"
|
|
hexmask.long.byte 0x36C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x36C 24. "NU1," "0,1"
|
|
bitfld.long 0x36C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x36C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x36C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x36C 0.--7. 1. "PARAM,"
|
|
line.long 0x370 "INST110_0,"
|
|
hexmask.long 0x370 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x374 "INST110_1,"
|
|
hexmask.long.byte 0x374 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x374 24. "NU1," "0,1"
|
|
bitfld.long 0x374 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x374 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x374 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x374 0.--7. 1. "PARAM,"
|
|
line.long 0x378 "INST111_0,"
|
|
hexmask.long 0x378 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x37C "INST111_1,"
|
|
hexmask.long.byte 0x37C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x37C 24. "NU1," "0,1"
|
|
bitfld.long 0x37C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x37C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x37C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x37C 0.--7. 1. "PARAM,"
|
|
line.long 0x380 "INST112_0,"
|
|
hexmask.long 0x380 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x384 "INST112_1,"
|
|
hexmask.long.byte 0x384 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x384 24. "NU1," "0,1"
|
|
bitfld.long 0x384 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x384 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x384 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x384 0.--7. 1. "PARAM,"
|
|
line.long 0x388 "INST113_0,"
|
|
hexmask.long 0x388 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x38C "INST113_1,"
|
|
hexmask.long.byte 0x38C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x38C 24. "NU1," "0,1"
|
|
bitfld.long 0x38C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x38C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x38C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x38C 0.--7. 1. "PARAM,"
|
|
line.long 0x390 "INST114_0,"
|
|
hexmask.long 0x390 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x394 "INST114_1,"
|
|
hexmask.long.byte 0x394 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x394 24. "NU1," "0,1"
|
|
bitfld.long 0x394 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x394 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x394 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x394 0.--7. 1. "PARAM,"
|
|
line.long 0x398 "INST115_0,"
|
|
hexmask.long 0x398 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x39C "INST115_1,"
|
|
hexmask.long.byte 0x39C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x39C 24. "NU1," "0,1"
|
|
bitfld.long 0x39C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x39C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x39C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x39C 0.--7. 1. "PARAM,"
|
|
line.long 0x3A0 "INST116_0,"
|
|
hexmask.long 0x3A0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3A4 "INST116_1,"
|
|
hexmask.long.byte 0x3A4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3A4 24. "NU1," "0,1"
|
|
bitfld.long 0x3A4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3A4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3A4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3A4 0.--7. 1. "PARAM,"
|
|
line.long 0x3A8 "INST117_0,"
|
|
hexmask.long 0x3A8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3AC "INST117_1,"
|
|
hexmask.long.byte 0x3AC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3AC 24. "NU1," "0,1"
|
|
bitfld.long 0x3AC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3AC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3AC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3AC 0.--7. 1. "PARAM,"
|
|
line.long 0x3B0 "INST118_0,"
|
|
hexmask.long 0x3B0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3B4 "INST118_1,"
|
|
hexmask.long.byte 0x3B4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3B4 24. "NU1," "0,1"
|
|
bitfld.long 0x3B4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3B4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3B4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3B4 0.--7. 1. "PARAM,"
|
|
line.long 0x3B8 "INST119_0,"
|
|
hexmask.long 0x3B8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3BC "INST119_1,"
|
|
hexmask.long.byte 0x3BC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3BC 24. "NU1," "0,1"
|
|
bitfld.long 0x3BC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3BC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3BC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3BC 0.--7. 1. "PARAM,"
|
|
line.long 0x3C0 "INST120_0,"
|
|
hexmask.long 0x3C0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3C4 "INST120_1,"
|
|
hexmask.long.byte 0x3C4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3C4 24. "NU1," "0,1"
|
|
bitfld.long 0x3C4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3C4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3C4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3C4 0.--7. 1. "PARAM,"
|
|
line.long 0x3C8 "INST121_0,"
|
|
hexmask.long 0x3C8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3CC "INST121_1,"
|
|
hexmask.long.byte 0x3CC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3CC 24. "NU1," "0,1"
|
|
bitfld.long 0x3CC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3CC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3CC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3CC 0.--7. 1. "PARAM,"
|
|
line.long 0x3D0 "INST122_0,"
|
|
hexmask.long 0x3D0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3D4 "INST122_1,"
|
|
hexmask.long.byte 0x3D4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3D4 24. "NU1," "0,1"
|
|
bitfld.long 0x3D4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3D4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3D4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3D4 0.--7. 1. "PARAM,"
|
|
line.long 0x3D8 "INST123_0,"
|
|
hexmask.long 0x3D8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3DC "INST123_1,"
|
|
hexmask.long.byte 0x3DC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3DC 24. "NU1," "0,1"
|
|
bitfld.long 0x3DC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3DC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3DC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3DC 0.--7. 1. "PARAM,"
|
|
line.long 0x3E0 "INST124_0,"
|
|
hexmask.long 0x3E0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3E4 "INST124_1,"
|
|
hexmask.long.byte 0x3E4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3E4 24. "NU1," "0,1"
|
|
bitfld.long 0x3E4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3E4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3E4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3E4 0.--7. 1. "PARAM,"
|
|
line.long 0x3E8 "INST125_0,"
|
|
hexmask.long 0x3E8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3EC "INST125_1,"
|
|
hexmask.long.byte 0x3EC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3EC 24. "NU1," "0,1"
|
|
bitfld.long 0x3EC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3EC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3EC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3EC 0.--7. 1. "PARAM,"
|
|
line.long 0x3F0 "INST126_0,"
|
|
hexmask.long 0x3F0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3F4 "INST126_1,"
|
|
hexmask.long.byte 0x3F4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3F4 24. "NU1," "0,1"
|
|
bitfld.long 0x3F4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3F4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3F4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3F4 0.--7. 1. "PARAM,"
|
|
line.long 0x3F8 "INST127_0,"
|
|
hexmask.long 0x3F8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x3FC "INST127_1,"
|
|
hexmask.long.byte 0x3FC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x3FC 24. "NU1," "0,1"
|
|
bitfld.long 0x3FC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x3FC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x3FC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x3FC 0.--7. 1. "PARAM,"
|
|
line.long 0x400 "INST128_0,"
|
|
hexmask.long 0x400 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x404 "INST128_1,"
|
|
hexmask.long.byte 0x404 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x404 24. "NU1," "0,1"
|
|
bitfld.long 0x404 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x404 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x404 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x404 0.--7. 1. "PARAM,"
|
|
line.long 0x408 "INST129_0,"
|
|
hexmask.long 0x408 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x40C "INST129_1,"
|
|
hexmask.long.byte 0x40C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x40C 24. "NU1," "0,1"
|
|
bitfld.long 0x40C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x40C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x40C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x40C 0.--7. 1. "PARAM,"
|
|
line.long 0x410 "INST130_0,"
|
|
hexmask.long 0x410 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x414 "INST130_1,"
|
|
hexmask.long.byte 0x414 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x414 24. "NU1," "0,1"
|
|
bitfld.long 0x414 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x414 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x414 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x414 0.--7. 1. "PARAM,"
|
|
line.long 0x418 "INST131_0,"
|
|
hexmask.long 0x418 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x41C "INST131_1,"
|
|
hexmask.long.byte 0x41C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x41C 24. "NU1," "0,1"
|
|
bitfld.long 0x41C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x41C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x41C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x41C 0.--7. 1. "PARAM,"
|
|
line.long 0x420 "INST132_0,"
|
|
hexmask.long 0x420 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x424 "INST132_1,"
|
|
hexmask.long.byte 0x424 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x424 24. "NU1," "0,1"
|
|
bitfld.long 0x424 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x424 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x424 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x424 0.--7. 1. "PARAM,"
|
|
line.long 0x428 "INST133_0,"
|
|
hexmask.long 0x428 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x42C "INST133_1,"
|
|
hexmask.long.byte 0x42C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x42C 24. "NU1," "0,1"
|
|
bitfld.long 0x42C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x42C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x42C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x42C 0.--7. 1. "PARAM,"
|
|
line.long 0x430 "INST134_0,"
|
|
hexmask.long 0x430 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x434 "INST134_1,"
|
|
hexmask.long.byte 0x434 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x434 24. "NU1," "0,1"
|
|
bitfld.long 0x434 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x434 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x434 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x434 0.--7. 1. "PARAM,"
|
|
line.long 0x438 "INST135_0,"
|
|
hexmask.long 0x438 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x43C "INST135_1,"
|
|
hexmask.long.byte 0x43C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x43C 24. "NU1," "0,1"
|
|
bitfld.long 0x43C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x43C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x43C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x43C 0.--7. 1. "PARAM,"
|
|
line.long 0x440 "INST136_0,"
|
|
hexmask.long 0x440 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x444 "INST136_1,"
|
|
hexmask.long.byte 0x444 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x444 24. "NU1," "0,1"
|
|
bitfld.long 0x444 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x444 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x444 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x444 0.--7. 1. "PARAM,"
|
|
line.long 0x448 "INST137_0,"
|
|
hexmask.long 0x448 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x44C "INST137_1,"
|
|
hexmask.long.byte 0x44C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x44C 24. "NU1," "0,1"
|
|
bitfld.long 0x44C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x44C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x44C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x44C 0.--7. 1. "PARAM,"
|
|
line.long 0x450 "INST138_0,"
|
|
hexmask.long 0x450 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x454 "INST138_1,"
|
|
hexmask.long.byte 0x454 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x454 24. "NU1," "0,1"
|
|
bitfld.long 0x454 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x454 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x454 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x454 0.--7. 1. "PARAM,"
|
|
line.long 0x458 "INST139_0,"
|
|
hexmask.long 0x458 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x45C "INST139_1,"
|
|
hexmask.long.byte 0x45C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x45C 24. "NU1," "0,1"
|
|
bitfld.long 0x45C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x45C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x45C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x45C 0.--7. 1. "PARAM,"
|
|
line.long 0x460 "INST140_0,"
|
|
hexmask.long 0x460 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x464 "INST140_1,"
|
|
hexmask.long.byte 0x464 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x464 24. "NU1," "0,1"
|
|
bitfld.long 0x464 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x464 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x464 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x464 0.--7. 1. "PARAM,"
|
|
line.long 0x468 "INST141_0,"
|
|
hexmask.long 0x468 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x46C "INST141_1,"
|
|
hexmask.long.byte 0x46C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x46C 24. "NU1," "0,1"
|
|
bitfld.long 0x46C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x46C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x46C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x46C 0.--7. 1. "PARAM,"
|
|
line.long 0x470 "INST142_0,"
|
|
hexmask.long 0x470 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x474 "INST142_1,"
|
|
hexmask.long.byte 0x474 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x474 24. "NU1," "0,1"
|
|
bitfld.long 0x474 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x474 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x474 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x474 0.--7. 1. "PARAM,"
|
|
line.long 0x478 "INST143_0,"
|
|
hexmask.long 0x478 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x47C "INST143_1,"
|
|
hexmask.long.byte 0x47C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x47C 24. "NU1," "0,1"
|
|
bitfld.long 0x47C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x47C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x47C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x47C 0.--7. 1. "PARAM,"
|
|
line.long 0x480 "INST144_0,"
|
|
hexmask.long 0x480 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x484 "INST144_1,"
|
|
hexmask.long.byte 0x484 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x484 24. "NU1," "0,1"
|
|
bitfld.long 0x484 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x484 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x484 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x484 0.--7. 1. "PARAM,"
|
|
line.long 0x488 "INST145_0,"
|
|
hexmask.long 0x488 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x48C "INST145_1,"
|
|
hexmask.long.byte 0x48C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x48C 24. "NU1," "0,1"
|
|
bitfld.long 0x48C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x48C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x48C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x48C 0.--7. 1. "PARAM,"
|
|
line.long 0x490 "INST146_0,"
|
|
hexmask.long 0x490 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x494 "INST146_1,"
|
|
hexmask.long.byte 0x494 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x494 24. "NU1," "0,1"
|
|
bitfld.long 0x494 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x494 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x494 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x494 0.--7. 1. "PARAM,"
|
|
line.long 0x498 "INST147_0,"
|
|
hexmask.long 0x498 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x49C "INST147_1,"
|
|
hexmask.long.byte 0x49C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x49C 24. "NU1," "0,1"
|
|
bitfld.long 0x49C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x49C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x49C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x49C 0.--7. 1. "PARAM,"
|
|
line.long 0x4A0 "INST148_0,"
|
|
hexmask.long 0x4A0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4A4 "INST148_1,"
|
|
hexmask.long.byte 0x4A4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4A4 24. "NU1," "0,1"
|
|
bitfld.long 0x4A4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4A4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4A4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4A4 0.--7. 1. "PARAM,"
|
|
line.long 0x4A8 "INST149_0,"
|
|
hexmask.long 0x4A8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4AC "INST149_1,"
|
|
hexmask.long.byte 0x4AC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4AC 24. "NU1," "0,1"
|
|
bitfld.long 0x4AC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4AC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4AC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4AC 0.--7. 1. "PARAM,"
|
|
line.long 0x4B0 "INST150_0,"
|
|
hexmask.long 0x4B0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4B4 "INST150_1,"
|
|
hexmask.long.byte 0x4B4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4B4 24. "NU1," "0,1"
|
|
bitfld.long 0x4B4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4B4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4B4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4B4 0.--7. 1. "PARAM,"
|
|
line.long 0x4B8 "INST151_0,"
|
|
hexmask.long 0x4B8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4BC "INST151_1,"
|
|
hexmask.long.byte 0x4BC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4BC 24. "NU1," "0,1"
|
|
bitfld.long 0x4BC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4BC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4BC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4BC 0.--7. 1. "PARAM,"
|
|
line.long 0x4C0 "INST152_0,"
|
|
hexmask.long 0x4C0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4C4 "INST152_1,"
|
|
hexmask.long.byte 0x4C4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4C4 24. "NU1," "0,1"
|
|
bitfld.long 0x4C4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4C4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4C4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4C4 0.--7. 1. "PARAM,"
|
|
line.long 0x4C8 "INST153_0,"
|
|
hexmask.long 0x4C8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4CC "INST153_1,"
|
|
hexmask.long.byte 0x4CC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4CC 24. "NU1," "0,1"
|
|
bitfld.long 0x4CC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4CC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4CC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4CC 0.--7. 1. "PARAM,"
|
|
line.long 0x4D0 "INST154_0,"
|
|
hexmask.long 0x4D0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4D4 "INST154_1,"
|
|
hexmask.long.byte 0x4D4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4D4 24. "NU1," "0,1"
|
|
bitfld.long 0x4D4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4D4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4D4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4D4 0.--7. 1. "PARAM,"
|
|
line.long 0x4D8 "INST155_0,"
|
|
hexmask.long 0x4D8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4DC "INST155_1,"
|
|
hexmask.long.byte 0x4DC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4DC 24. "NU1," "0,1"
|
|
bitfld.long 0x4DC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4DC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4DC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4DC 0.--7. 1. "PARAM,"
|
|
line.long 0x4E0 "INST156_0,"
|
|
hexmask.long 0x4E0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4E4 "INST156_1,"
|
|
hexmask.long.byte 0x4E4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4E4 24. "NU1," "0,1"
|
|
bitfld.long 0x4E4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4E4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4E4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4E4 0.--7. 1. "PARAM,"
|
|
line.long 0x4E8 "INST157_0,"
|
|
hexmask.long 0x4E8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4EC "INST157_1,"
|
|
hexmask.long.byte 0x4EC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4EC 24. "NU1," "0,1"
|
|
bitfld.long 0x4EC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4EC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4EC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4EC 0.--7. 1. "PARAM,"
|
|
line.long 0x4F0 "INST158_0,"
|
|
hexmask.long 0x4F0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4F4 "INST158_1,"
|
|
hexmask.long.byte 0x4F4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4F4 24. "NU1," "0,1"
|
|
bitfld.long 0x4F4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4F4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4F4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4F4 0.--7. 1. "PARAM,"
|
|
line.long 0x4F8 "INST159_0,"
|
|
hexmask.long 0x4F8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x4FC "INST159_1,"
|
|
hexmask.long.byte 0x4FC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x4FC 24. "NU1," "0,1"
|
|
bitfld.long 0x4FC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x4FC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x4FC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x4FC 0.--7. 1. "PARAM,"
|
|
line.long 0x500 "INST160_0,"
|
|
hexmask.long 0x500 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x504 "INST160_1,"
|
|
hexmask.long.byte 0x504 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x504 24. "NU1," "0,1"
|
|
bitfld.long 0x504 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x504 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x504 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x504 0.--7. 1. "PARAM,"
|
|
line.long 0x508 "INST161_0,"
|
|
hexmask.long 0x508 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x50C "INST161_1,"
|
|
hexmask.long.byte 0x50C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x50C 24. "NU1," "0,1"
|
|
bitfld.long 0x50C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x50C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x50C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x50C 0.--7. 1. "PARAM,"
|
|
line.long 0x510 "INST162_0,"
|
|
hexmask.long 0x510 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x514 "INST162_1,"
|
|
hexmask.long.byte 0x514 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x514 24. "NU1," "0,1"
|
|
bitfld.long 0x514 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x514 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x514 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x514 0.--7. 1. "PARAM,"
|
|
line.long 0x518 "INST163_0,"
|
|
hexmask.long 0x518 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x51C "INST163_1,"
|
|
hexmask.long.byte 0x51C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x51C 24. "NU1," "0,1"
|
|
bitfld.long 0x51C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x51C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x51C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x51C 0.--7. 1. "PARAM,"
|
|
line.long 0x520 "INST164_0,"
|
|
hexmask.long 0x520 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x524 "INST164_1,"
|
|
hexmask.long.byte 0x524 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x524 24. "NU1," "0,1"
|
|
bitfld.long 0x524 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x524 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x524 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x524 0.--7. 1. "PARAM,"
|
|
line.long 0x528 "INST165_0,"
|
|
hexmask.long 0x528 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x52C "INST165_1,"
|
|
hexmask.long.byte 0x52C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x52C 24. "NU1," "0,1"
|
|
bitfld.long 0x52C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x52C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x52C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x52C 0.--7. 1. "PARAM,"
|
|
line.long 0x530 "INST166_0,"
|
|
hexmask.long 0x530 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x534 "INST166_1,"
|
|
hexmask.long.byte 0x534 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x534 24. "NU1," "0,1"
|
|
bitfld.long 0x534 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x534 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x534 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x534 0.--7. 1. "PARAM,"
|
|
line.long 0x538 "INST167_0,"
|
|
hexmask.long 0x538 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x53C "INST167_1,"
|
|
hexmask.long.byte 0x53C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x53C 24. "NU1," "0,1"
|
|
bitfld.long 0x53C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x53C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x53C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x53C 0.--7. 1. "PARAM,"
|
|
line.long 0x540 "INST168_0,"
|
|
hexmask.long 0x540 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x544 "INST168_1,"
|
|
hexmask.long.byte 0x544 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x544 24. "NU1," "0,1"
|
|
bitfld.long 0x544 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x544 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x544 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x544 0.--7. 1. "PARAM,"
|
|
line.long 0x548 "INST169_0,"
|
|
hexmask.long 0x548 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x54C "INST169_1,"
|
|
hexmask.long.byte 0x54C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x54C 24. "NU1," "0,1"
|
|
bitfld.long 0x54C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x54C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x54C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x54C 0.--7. 1. "PARAM,"
|
|
line.long 0x550 "INST170_0,"
|
|
hexmask.long 0x550 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x554 "INST170_1,"
|
|
hexmask.long.byte 0x554 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x554 24. "NU1," "0,1"
|
|
bitfld.long 0x554 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x554 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x554 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x554 0.--7. 1. "PARAM,"
|
|
line.long 0x558 "INST171_0,"
|
|
hexmask.long 0x558 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x55C "INST171_1,"
|
|
hexmask.long.byte 0x55C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x55C 24. "NU1," "0,1"
|
|
bitfld.long 0x55C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x55C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x55C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x55C 0.--7. 1. "PARAM,"
|
|
line.long 0x560 "INST172_0,"
|
|
hexmask.long 0x560 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x564 "INST172_1,"
|
|
hexmask.long.byte 0x564 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x564 24. "NU1," "0,1"
|
|
bitfld.long 0x564 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x564 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x564 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x564 0.--7. 1. "PARAM,"
|
|
line.long 0x568 "INST173_0,"
|
|
hexmask.long 0x568 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x56C "INST173_1,"
|
|
hexmask.long.byte 0x56C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x56C 24. "NU1," "0,1"
|
|
bitfld.long 0x56C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x56C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x56C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x56C 0.--7. 1. "PARAM,"
|
|
line.long 0x570 "INST174_0,"
|
|
hexmask.long 0x570 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x574 "INST174_1,"
|
|
hexmask.long.byte 0x574 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x574 24. "NU1," "0,1"
|
|
bitfld.long 0x574 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x574 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x574 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x574 0.--7. 1. "PARAM,"
|
|
line.long 0x578 "INST175_0,"
|
|
hexmask.long 0x578 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x57C "INST175_1,"
|
|
hexmask.long.byte 0x57C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x57C 24. "NU1," "0,1"
|
|
bitfld.long 0x57C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x57C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x57C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x57C 0.--7. 1. "PARAM,"
|
|
line.long 0x580 "INST176_0,"
|
|
hexmask.long 0x580 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x584 "INST176_1,"
|
|
hexmask.long.byte 0x584 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x584 24. "NU1," "0,1"
|
|
bitfld.long 0x584 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x584 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x584 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x584 0.--7. 1. "PARAM,"
|
|
line.long 0x588 "INST177_0,"
|
|
hexmask.long 0x588 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x58C "INST177_1,"
|
|
hexmask.long.byte 0x58C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x58C 24. "NU1," "0,1"
|
|
bitfld.long 0x58C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x58C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x58C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x58C 0.--7. 1. "PARAM,"
|
|
line.long 0x590 "INST178_0,"
|
|
hexmask.long 0x590 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x594 "INST178_1,"
|
|
hexmask.long.byte 0x594 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x594 24. "NU1," "0,1"
|
|
bitfld.long 0x594 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x594 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x594 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x594 0.--7. 1. "PARAM,"
|
|
line.long 0x598 "INST179_0,"
|
|
hexmask.long 0x598 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x59C "INST179_1,"
|
|
hexmask.long.byte 0x59C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x59C 24. "NU1," "0,1"
|
|
bitfld.long 0x59C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x59C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x59C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x59C 0.--7. 1. "PARAM,"
|
|
line.long 0x5A0 "INST180_0,"
|
|
hexmask.long 0x5A0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5A4 "INST180_1,"
|
|
hexmask.long.byte 0x5A4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5A4 24. "NU1," "0,1"
|
|
bitfld.long 0x5A4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5A4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5A4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5A4 0.--7. 1. "PARAM,"
|
|
line.long 0x5A8 "INST181_0,"
|
|
hexmask.long 0x5A8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5AC "INST181_1,"
|
|
hexmask.long.byte 0x5AC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5AC 24. "NU1," "0,1"
|
|
bitfld.long 0x5AC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5AC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5AC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5AC 0.--7. 1. "PARAM,"
|
|
line.long 0x5B0 "INST182_0,"
|
|
hexmask.long 0x5B0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5B4 "INST182_1,"
|
|
hexmask.long.byte 0x5B4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5B4 24. "NU1," "0,1"
|
|
bitfld.long 0x5B4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5B4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5B4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5B4 0.--7. 1. "PARAM,"
|
|
line.long 0x5B8 "INST183_0,"
|
|
hexmask.long 0x5B8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5BC "INST183_1,"
|
|
hexmask.long.byte 0x5BC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5BC 24. "NU1," "0,1"
|
|
bitfld.long 0x5BC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5BC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5BC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5BC 0.--7. 1. "PARAM,"
|
|
line.long 0x5C0 "INST184_0,"
|
|
hexmask.long 0x5C0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5C4 "INST184_1,"
|
|
hexmask.long.byte 0x5C4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5C4 24. "NU1," "0,1"
|
|
bitfld.long 0x5C4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5C4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5C4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5C4 0.--7. 1. "PARAM,"
|
|
line.long 0x5C8 "INST185_0,"
|
|
hexmask.long 0x5C8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5CC "INST185_1,"
|
|
hexmask.long.byte 0x5CC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5CC 24. "NU1," "0,1"
|
|
bitfld.long 0x5CC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5CC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5CC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5CC 0.--7. 1. "PARAM,"
|
|
line.long 0x5D0 "INST186_0,"
|
|
hexmask.long 0x5D0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5D4 "INST186_1,"
|
|
hexmask.long.byte 0x5D4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5D4 24. "NU1," "0,1"
|
|
bitfld.long 0x5D4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5D4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5D4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5D4 0.--7. 1. "PARAM,"
|
|
line.long 0x5D8 "INST187_0,"
|
|
hexmask.long 0x5D8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5DC "INST187_1,"
|
|
hexmask.long.byte 0x5DC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5DC 24. "NU1," "0,1"
|
|
bitfld.long 0x5DC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5DC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5DC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5DC 0.--7. 1. "PARAM,"
|
|
line.long 0x5E0 "INST188_0,"
|
|
hexmask.long 0x5E0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5E4 "INST188_1,"
|
|
hexmask.long.byte 0x5E4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5E4 24. "NU1," "0,1"
|
|
bitfld.long 0x5E4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5E4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5E4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5E4 0.--7. 1. "PARAM,"
|
|
line.long 0x5E8 "INST189_0,"
|
|
hexmask.long 0x5E8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5EC "INST189_1,"
|
|
hexmask.long.byte 0x5EC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5EC 24. "NU1," "0,1"
|
|
bitfld.long 0x5EC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5EC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5EC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5EC 0.--7. 1. "PARAM,"
|
|
line.long 0x5F0 "INST190_0,"
|
|
hexmask.long 0x5F0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5F4 "INST190_1,"
|
|
hexmask.long.byte 0x5F4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5F4 24. "NU1," "0,1"
|
|
bitfld.long 0x5F4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5F4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5F4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5F4 0.--7. 1. "PARAM,"
|
|
line.long 0x5F8 "INST191_0,"
|
|
hexmask.long 0x5F8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x5FC "INST191_1,"
|
|
hexmask.long.byte 0x5FC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x5FC 24. "NU1," "0,1"
|
|
bitfld.long 0x5FC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x5FC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x5FC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x5FC 0.--7. 1. "PARAM,"
|
|
line.long 0x600 "INST192_0,"
|
|
hexmask.long 0x600 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x604 "INST192_1,"
|
|
hexmask.long.byte 0x604 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x604 24. "NU1," "0,1"
|
|
bitfld.long 0x604 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x604 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x604 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x604 0.--7. 1. "PARAM,"
|
|
line.long 0x608 "INST193_0,"
|
|
hexmask.long 0x608 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x60C "INST193_1,"
|
|
hexmask.long.byte 0x60C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x60C 24. "NU1," "0,1"
|
|
bitfld.long 0x60C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x60C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x60C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x60C 0.--7. 1. "PARAM,"
|
|
line.long 0x610 "INST194_0,"
|
|
hexmask.long 0x610 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x614 "INST194_1,"
|
|
hexmask.long.byte 0x614 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x614 24. "NU1," "0,1"
|
|
bitfld.long 0x614 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x614 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x614 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x614 0.--7. 1. "PARAM,"
|
|
line.long 0x618 "INST195_0,"
|
|
hexmask.long 0x618 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x61C "INST195_1,"
|
|
hexmask.long.byte 0x61C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x61C 24. "NU1," "0,1"
|
|
bitfld.long 0x61C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x61C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x61C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x61C 0.--7. 1. "PARAM,"
|
|
line.long 0x620 "INST196_0,"
|
|
hexmask.long 0x620 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x624 "INST196_1,"
|
|
hexmask.long.byte 0x624 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x624 24. "NU1," "0,1"
|
|
bitfld.long 0x624 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x624 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x624 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x624 0.--7. 1. "PARAM,"
|
|
line.long 0x628 "INST197_0,"
|
|
hexmask.long 0x628 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x62C "INST197_1,"
|
|
hexmask.long.byte 0x62C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x62C 24. "NU1," "0,1"
|
|
bitfld.long 0x62C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x62C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x62C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x62C 0.--7. 1. "PARAM,"
|
|
line.long 0x630 "INST198_0,"
|
|
hexmask.long 0x630 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x634 "INST198_1,"
|
|
hexmask.long.byte 0x634 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x634 24. "NU1," "0,1"
|
|
bitfld.long 0x634 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x634 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x634 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x634 0.--7. 1. "PARAM,"
|
|
line.long 0x638 "INST199_0,"
|
|
hexmask.long 0x638 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x63C "INST199_1,"
|
|
hexmask.long.byte 0x63C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x63C 24. "NU1," "0,1"
|
|
bitfld.long 0x63C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x63C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x63C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x63C 0.--7. 1. "PARAM,"
|
|
line.long 0x640 "INST200_0,"
|
|
hexmask.long 0x640 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x644 "INST200_1,"
|
|
hexmask.long.byte 0x644 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x644 24. "NU1," "0,1"
|
|
bitfld.long 0x644 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x644 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x644 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x644 0.--7. 1. "PARAM,"
|
|
line.long 0x648 "INST201_0,"
|
|
hexmask.long 0x648 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x64C "INST201_1,"
|
|
hexmask.long.byte 0x64C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x64C 24. "NU1," "0,1"
|
|
bitfld.long 0x64C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x64C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x64C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x64C 0.--7. 1. "PARAM,"
|
|
line.long 0x650 "INST202_0,"
|
|
hexmask.long 0x650 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x654 "INST202_1,"
|
|
hexmask.long.byte 0x654 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x654 24. "NU1," "0,1"
|
|
bitfld.long 0x654 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x654 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x654 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x654 0.--7. 1. "PARAM,"
|
|
line.long 0x658 "INST203_0,"
|
|
hexmask.long 0x658 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x65C "INST203_1,"
|
|
hexmask.long.byte 0x65C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x65C 24. "NU1," "0,1"
|
|
bitfld.long 0x65C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x65C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x65C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x65C 0.--7. 1. "PARAM,"
|
|
line.long 0x660 "INST204_0,"
|
|
hexmask.long 0x660 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x664 "INST204_1,"
|
|
hexmask.long.byte 0x664 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x664 24. "NU1," "0,1"
|
|
bitfld.long 0x664 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x664 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x664 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x664 0.--7. 1. "PARAM,"
|
|
line.long 0x668 "INST205_0,"
|
|
hexmask.long 0x668 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x66C "INST205_1,"
|
|
hexmask.long.byte 0x66C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x66C 24. "NU1," "0,1"
|
|
bitfld.long 0x66C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x66C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x66C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x66C 0.--7. 1. "PARAM,"
|
|
line.long 0x670 "INST206_0,"
|
|
hexmask.long 0x670 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x674 "INST206_1,"
|
|
hexmask.long.byte 0x674 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x674 24. "NU1," "0,1"
|
|
bitfld.long 0x674 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x674 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x674 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x674 0.--7. 1. "PARAM,"
|
|
line.long 0x678 "INST207_0,"
|
|
hexmask.long 0x678 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x67C "INST207_1,"
|
|
hexmask.long.byte 0x67C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x67C 24. "NU1," "0,1"
|
|
bitfld.long 0x67C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x67C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x67C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x67C 0.--7. 1. "PARAM,"
|
|
line.long 0x680 "INST208_0,"
|
|
hexmask.long 0x680 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x684 "INST208_1,"
|
|
hexmask.long.byte 0x684 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x684 24. "NU1," "0,1"
|
|
bitfld.long 0x684 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x684 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x684 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x684 0.--7. 1. "PARAM,"
|
|
line.long 0x688 "INST209_0,"
|
|
hexmask.long 0x688 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x68C "INST209_1,"
|
|
hexmask.long.byte 0x68C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x68C 24. "NU1," "0,1"
|
|
bitfld.long 0x68C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x68C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x68C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x68C 0.--7. 1. "PARAM,"
|
|
line.long 0x690 "INST210_0,"
|
|
hexmask.long 0x690 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x694 "INST210_1,"
|
|
hexmask.long.byte 0x694 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x694 24. "NU1," "0,1"
|
|
bitfld.long 0x694 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x694 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x694 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x694 0.--7. 1. "PARAM,"
|
|
line.long 0x698 "INST211_0,"
|
|
hexmask.long 0x698 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x69C "INST211_1,"
|
|
hexmask.long.byte 0x69C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x69C 24. "NU1," "0,1"
|
|
bitfld.long 0x69C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x69C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x69C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x69C 0.--7. 1. "PARAM,"
|
|
line.long 0x6A0 "INST212_0,"
|
|
hexmask.long 0x6A0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6A4 "INST212_1,"
|
|
hexmask.long.byte 0x6A4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6A4 24. "NU1," "0,1"
|
|
bitfld.long 0x6A4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6A4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6A4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6A4 0.--7. 1. "PARAM,"
|
|
line.long 0x6A8 "INST213_0,"
|
|
hexmask.long 0x6A8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6AC "INST213_1,"
|
|
hexmask.long.byte 0x6AC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6AC 24. "NU1," "0,1"
|
|
bitfld.long 0x6AC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6AC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6AC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6AC 0.--7. 1. "PARAM,"
|
|
line.long 0x6B0 "INST214_0,"
|
|
hexmask.long 0x6B0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6B4 "INST214_1,"
|
|
hexmask.long.byte 0x6B4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6B4 24. "NU1," "0,1"
|
|
bitfld.long 0x6B4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6B4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6B4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6B4 0.--7. 1. "PARAM,"
|
|
line.long 0x6B8 "INST215_0,"
|
|
hexmask.long 0x6B8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6BC "INST215_1,"
|
|
hexmask.long.byte 0x6BC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6BC 24. "NU1," "0,1"
|
|
bitfld.long 0x6BC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6BC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6BC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6BC 0.--7. 1. "PARAM,"
|
|
line.long 0x6C0 "INST216_0,"
|
|
hexmask.long 0x6C0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6C4 "INST216_1,"
|
|
hexmask.long.byte 0x6C4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6C4 24. "NU1," "0,1"
|
|
bitfld.long 0x6C4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6C4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6C4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6C4 0.--7. 1. "PARAM,"
|
|
line.long 0x6C8 "INST217_0,"
|
|
hexmask.long 0x6C8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6CC "INST217_1,"
|
|
hexmask.long.byte 0x6CC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6CC 24. "NU1," "0,1"
|
|
bitfld.long 0x6CC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6CC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6CC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6CC 0.--7. 1. "PARAM,"
|
|
line.long 0x6D0 "INST218_0,"
|
|
hexmask.long 0x6D0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6D4 "INST218_1,"
|
|
hexmask.long.byte 0x6D4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6D4 24. "NU1," "0,1"
|
|
bitfld.long 0x6D4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6D4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6D4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6D4 0.--7. 1. "PARAM,"
|
|
line.long 0x6D8 "INST219_0,"
|
|
hexmask.long 0x6D8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6DC "INST219_1,"
|
|
hexmask.long.byte 0x6DC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6DC 24. "NU1," "0,1"
|
|
bitfld.long 0x6DC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6DC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6DC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6DC 0.--7. 1. "PARAM,"
|
|
line.long 0x6E0 "INST220_0,"
|
|
hexmask.long 0x6E0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6E4 "INST220_1,"
|
|
hexmask.long.byte 0x6E4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6E4 24. "NU1," "0,1"
|
|
bitfld.long 0x6E4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6E4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6E4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6E4 0.--7. 1. "PARAM,"
|
|
line.long 0x6E8 "INST221_0,"
|
|
hexmask.long 0x6E8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6EC "INST221_1,"
|
|
hexmask.long.byte 0x6EC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6EC 24. "NU1," "0,1"
|
|
bitfld.long 0x6EC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6EC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6EC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6EC 0.--7. 1. "PARAM,"
|
|
line.long 0x6F0 "INST222_0,"
|
|
hexmask.long 0x6F0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6F4 "INST222_1,"
|
|
hexmask.long.byte 0x6F4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6F4 24. "NU1," "0,1"
|
|
bitfld.long 0x6F4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6F4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6F4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6F4 0.--7. 1. "PARAM,"
|
|
line.long 0x6F8 "INST223_0,"
|
|
hexmask.long 0x6F8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x6FC "INST223_1,"
|
|
hexmask.long.byte 0x6FC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x6FC 24. "NU1," "0,1"
|
|
bitfld.long 0x6FC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x6FC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x6FC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x6FC 0.--7. 1. "PARAM,"
|
|
line.long 0x700 "INST224_0,"
|
|
hexmask.long 0x700 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x704 "INST224_1,"
|
|
hexmask.long.byte 0x704 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x704 24. "NU1," "0,1"
|
|
bitfld.long 0x704 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x704 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x704 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x704 0.--7. 1. "PARAM,"
|
|
line.long 0x708 "INST225_0,"
|
|
hexmask.long 0x708 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x70C "INST225_1,"
|
|
hexmask.long.byte 0x70C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x70C 24. "NU1," "0,1"
|
|
bitfld.long 0x70C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x70C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x70C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x70C 0.--7. 1. "PARAM,"
|
|
line.long 0x710 "INST226_0,"
|
|
hexmask.long 0x710 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x714 "INST226_1,"
|
|
hexmask.long.byte 0x714 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x714 24. "NU1," "0,1"
|
|
bitfld.long 0x714 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x714 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x714 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x714 0.--7. 1. "PARAM,"
|
|
line.long 0x718 "INST227_0,"
|
|
hexmask.long 0x718 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x71C "INST227_1,"
|
|
hexmask.long.byte 0x71C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x71C 24. "NU1," "0,1"
|
|
bitfld.long 0x71C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x71C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x71C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x71C 0.--7. 1. "PARAM,"
|
|
line.long 0x720 "INST228_0,"
|
|
hexmask.long 0x720 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x724 "INST228_1,"
|
|
hexmask.long.byte 0x724 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x724 24. "NU1," "0,1"
|
|
bitfld.long 0x724 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x724 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x724 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x724 0.--7. 1. "PARAM,"
|
|
line.long 0x728 "INST229_0,"
|
|
hexmask.long 0x728 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x72C "INST229_1,"
|
|
hexmask.long.byte 0x72C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x72C 24. "NU1," "0,1"
|
|
bitfld.long 0x72C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x72C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x72C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x72C 0.--7. 1. "PARAM,"
|
|
line.long 0x730 "INST230_0,"
|
|
hexmask.long 0x730 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x734 "INST230_1,"
|
|
hexmask.long.byte 0x734 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x734 24. "NU1," "0,1"
|
|
bitfld.long 0x734 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x734 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x734 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x734 0.--7. 1. "PARAM,"
|
|
line.long 0x738 "INST231_0,"
|
|
hexmask.long 0x738 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x73C "INST231_1,"
|
|
hexmask.long.byte 0x73C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x73C 24. "NU1," "0,1"
|
|
bitfld.long 0x73C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x73C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x73C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x73C 0.--7. 1. "PARAM,"
|
|
line.long 0x740 "INST232_0,"
|
|
hexmask.long 0x740 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x744 "INST232_1,"
|
|
hexmask.long.byte 0x744 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x744 24. "NU1," "0,1"
|
|
bitfld.long 0x744 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x744 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x744 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x744 0.--7. 1. "PARAM,"
|
|
line.long 0x748 "INST233_0,"
|
|
hexmask.long 0x748 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x74C "INST233_1,"
|
|
hexmask.long.byte 0x74C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x74C 24. "NU1," "0,1"
|
|
bitfld.long 0x74C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x74C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x74C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x74C 0.--7. 1. "PARAM,"
|
|
line.long 0x750 "INST234_0,"
|
|
hexmask.long 0x750 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x754 "INST234_1,"
|
|
hexmask.long.byte 0x754 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x754 24. "NU1," "0,1"
|
|
bitfld.long 0x754 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x754 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x754 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x754 0.--7. 1. "PARAM,"
|
|
line.long 0x758 "INST235_0,"
|
|
hexmask.long 0x758 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x75C "INST235_1,"
|
|
hexmask.long.byte 0x75C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x75C 24. "NU1," "0,1"
|
|
bitfld.long 0x75C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x75C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x75C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x75C 0.--7. 1. "PARAM,"
|
|
line.long 0x760 "INST236_0,"
|
|
hexmask.long 0x760 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x764 "INST236_1,"
|
|
hexmask.long.byte 0x764 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x764 24. "NU1," "0,1"
|
|
bitfld.long 0x764 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x764 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x764 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x764 0.--7. 1. "PARAM,"
|
|
line.long 0x768 "INST237_0,"
|
|
hexmask.long 0x768 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x76C "INST237_1,"
|
|
hexmask.long.byte 0x76C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x76C 24. "NU1," "0,1"
|
|
bitfld.long 0x76C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x76C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x76C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x76C 0.--7. 1. "PARAM,"
|
|
line.long 0x770 "INST238_0,"
|
|
hexmask.long 0x770 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x774 "INST238_1,"
|
|
hexmask.long.byte 0x774 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x774 24. "NU1," "0,1"
|
|
bitfld.long 0x774 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x774 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x774 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x774 0.--7. 1. "PARAM,"
|
|
line.long 0x778 "INST239_0,"
|
|
hexmask.long 0x778 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x77C "INST239_1,"
|
|
hexmask.long.byte 0x77C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x77C 24. "NU1," "0,1"
|
|
bitfld.long 0x77C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x77C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x77C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x77C 0.--7. 1. "PARAM,"
|
|
line.long 0x780 "INST240_0,"
|
|
hexmask.long 0x780 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x784 "INST240_1,"
|
|
hexmask.long.byte 0x784 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x784 24. "NU1," "0,1"
|
|
bitfld.long 0x784 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x784 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x784 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x784 0.--7. 1. "PARAM,"
|
|
line.long 0x788 "INST241_0,"
|
|
hexmask.long 0x788 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x78C "INST241_1,"
|
|
hexmask.long.byte 0x78C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x78C 24. "NU1," "0,1"
|
|
bitfld.long 0x78C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x78C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x78C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x78C 0.--7. 1. "PARAM,"
|
|
line.long 0x790 "INST242_0,"
|
|
hexmask.long 0x790 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x794 "INST242_1,"
|
|
hexmask.long.byte 0x794 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x794 24. "NU1," "0,1"
|
|
bitfld.long 0x794 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x794 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x794 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x794 0.--7. 1. "PARAM,"
|
|
line.long 0x798 "INST243_0,"
|
|
hexmask.long 0x798 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x79C "INST243_1,"
|
|
hexmask.long.byte 0x79C 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x79C 24. "NU1," "0,1"
|
|
bitfld.long 0x79C 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x79C 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x79C 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x79C 0.--7. 1. "PARAM,"
|
|
line.long 0x7A0 "INST244_0,"
|
|
hexmask.long 0x7A0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7A4 "INST244_1,"
|
|
hexmask.long.byte 0x7A4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7A4 24. "NU1," "0,1"
|
|
bitfld.long 0x7A4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7A4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7A4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7A4 0.--7. 1. "PARAM,"
|
|
line.long 0x7A8 "INST245_0,"
|
|
hexmask.long 0x7A8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7AC "INST245_1,"
|
|
hexmask.long.byte 0x7AC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7AC 24. "NU1," "0,1"
|
|
bitfld.long 0x7AC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7AC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7AC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7AC 0.--7. 1. "PARAM,"
|
|
line.long 0x7B0 "INST246_0,"
|
|
hexmask.long 0x7B0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7B4 "INST246_1,"
|
|
hexmask.long.byte 0x7B4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7B4 24. "NU1," "0,1"
|
|
bitfld.long 0x7B4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7B4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7B4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7B4 0.--7. 1. "PARAM,"
|
|
line.long 0x7B8 "INST247_0,"
|
|
hexmask.long 0x7B8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7BC "INST247_1,"
|
|
hexmask.long.byte 0x7BC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7BC 24. "NU1," "0,1"
|
|
bitfld.long 0x7BC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7BC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7BC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7BC 0.--7. 1. "PARAM,"
|
|
line.long 0x7C0 "INST248_0,"
|
|
hexmask.long 0x7C0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7C4 "INST248_1,"
|
|
hexmask.long.byte 0x7C4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7C4 24. "NU1," "0,1"
|
|
bitfld.long 0x7C4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7C4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7C4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7C4 0.--7. 1. "PARAM,"
|
|
line.long 0x7C8 "INST249_0,"
|
|
hexmask.long 0x7C8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7CC "INST249_1,"
|
|
hexmask.long.byte 0x7CC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7CC 24. "NU1," "0,1"
|
|
bitfld.long 0x7CC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7CC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7CC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7CC 0.--7. 1. "PARAM,"
|
|
line.long 0x7D0 "INST250_0,"
|
|
hexmask.long 0x7D0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7D4 "INST250_1,"
|
|
hexmask.long.byte 0x7D4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7D4 24. "NU1," "0,1"
|
|
bitfld.long 0x7D4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7D4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7D4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7D4 0.--7. 1. "PARAM,"
|
|
line.long 0x7D8 "INST251_0,"
|
|
hexmask.long 0x7D8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7DC "INST251_1,"
|
|
hexmask.long.byte 0x7DC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7DC 24. "NU1," "0,1"
|
|
bitfld.long 0x7DC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7DC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7DC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7DC 0.--7. 1. "PARAM,"
|
|
line.long 0x7E0 "INST252_0,"
|
|
hexmask.long 0x7E0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7E4 "INST252_1,"
|
|
hexmask.long.byte 0x7E4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7E4 24. "NU1," "0,1"
|
|
bitfld.long 0x7E4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7E4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7E4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7E4 0.--7. 1. "PARAM,"
|
|
line.long 0x7E8 "INST253_0,"
|
|
hexmask.long 0x7E8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7EC "INST253_1,"
|
|
hexmask.long.byte 0x7EC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7EC 24. "NU1," "0,1"
|
|
bitfld.long 0x7EC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7EC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7EC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7EC 0.--7. 1. "PARAM,"
|
|
line.long 0x7F0 "INST254_0,"
|
|
hexmask.long 0x7F0 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7F4 "INST254_1,"
|
|
hexmask.long.byte 0x7F4 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7F4 24. "NU1," "0,1"
|
|
bitfld.long 0x7F4 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7F4 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7F4 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7F4 0.--7. 1. "PARAM,"
|
|
line.long 0x7F8 "INST255_0,"
|
|
hexmask.long 0x7F8 0.--31. 1. "CONFIG_VALUE,"
|
|
line.long 0x7FC "INST255_1,"
|
|
hexmask.long.byte 0x7FC 25.--31. 1. "NU2,"
|
|
rbitfld.long 0x7FC 24. "NU1," "0,1"
|
|
bitfld.long 0x7FC 23. "CHIRP_BRK," "0,1"
|
|
hexmask.long.byte 0x7FC 16.--22. 1. "SKIP_SAMPLES,"
|
|
newline
|
|
hexmask.long.byte 0x7FC 8.--15. 1. "COLLECT_SAMPLES,"
|
|
hexmask.long.byte 0x7FC 0.--7. 1. "PARAM,"
|
|
tree.end
|
|
tree "MSS_GPADC_REG"
|
|
base ad:0x3F79800
|
|
group.long 0x0++0x33
|
|
line.long 0x0 "REG0,gpadc modes and enable"
|
|
hexmask.long.word 0x0 17.--31. 1. "NU3,TI reserved"
|
|
bitfld.long 0x0 16. "GPADC_DEBUG_MODE_ENABLE,1:GPADC raw samples will be collected in the Output RAM in IFM mode" "?,1: GPADC raw samples will be collected in the.."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "NU2,TI reserved"
|
|
bitfld.long 0x0 9.--11. "GPADC2ADCBUF_PATH_EN,TI reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8. "GPADC_FSM_CLK_ENABLE,Enable the clock to gpadc fsm" "0,1"
|
|
hexmask.long.byte 0x0 2.--7. 1. "NU1,TI reserved"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "DCBIST_MODE,0:Disable 1:IFM Mode enable 2:CTM mode enable" "0: Disable,1: IFM Mode enable,2: CTM mode enable,?"
|
|
line.long 0x4 "REG1,gpadc start trigger for Inter frame mode"
|
|
hexmask.long.byte 0x4 25.--31. 1. "NU4,TI reserved"
|
|
bitfld.long 0x4 24. "GPADC_START_BYP_VAL," "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 17.--23. 1. "NU3,TI reserved"
|
|
bitfld.long 0x4 16. "GPADC_FSM_BYPASS,1:Bypass gpadc control .When bypassed start = gpadc_start_byp_val config_val = config_value_ifm param_val = param_val_ifm" "?,1: Bypass gpadc control"
|
|
newline
|
|
hexmask.long.byte 0x4 9.--15. 1. "NU2,TI reserved"
|
|
bitfld.long 0x4 8. "GPADC_INIT,Resets the FSM and clears the data RAM" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 1.--7. 1. "NU1,TI reserved"
|
|
bitfld.long 0x4 0. "GPADC_TRIGGER,Generates a single cycle pulse to trigger the IFM mode" "0,1"
|
|
line.long 0x8 "REG2,gpadc config for IFM"
|
|
hexmask.long 0x8 0.--31. 1. "CONFIG_VALUE_IFM,Configuration value to be passed to analog in IFM mode"
|
|
line.long 0xC "REG3,gpadc param. skip samples and collect samples for IFM"
|
|
hexmask.long.word 0xC 23.--31. 1. "NU,"
|
|
hexmask.long.byte 0xC 16.--22. 1. "SKIP_SAMPLES_IFM,number of GPADC clocks to skip after trigger . Number of samples to skip = skip_samples_ifm[3:0]x(2skip_samples_ifm[6:4])"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "COLLECT_SAMPLES_IFM,number of GPADC readings to collect"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PARAM_VAL_IFM,Param value to be passed to analog in IFM mode(after one hot encoding)"
|
|
line.long 0x10 "REG4,Base address for Chirp profile 0 in instruction packet RAM"
|
|
hexmask.long.byte 0x10 24.--31. 1. "PKT_RAM_BASE_ADDR_CP3,TI reserved"
|
|
hexmask.long.byte 0x10 16.--23. 1. "PKT_RAM_BASE_ADDR_CP2,TI reserved"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "PKT_RAM_BASE_ADDR_CP1,(End-Address + 1) of instruction-ram in CTM mode"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PKT_RAM_BASE_ADDR_CP0,Start Address of instruction-ram in CTM mode"
|
|
line.long 0x14 "REG5,Base address for Chirp profile 1 in instruction packet RAM"
|
|
hexmask.long.byte 0x14 24.--31. 1. "PKT_RAM_BASE_ADDR_CP7,TI reserved"
|
|
hexmask.long.byte 0x14 16.--23. 1. "PKT_RAM_BASE_ADDR_CP6,TI reserved"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "PKT_RAM_BASE_ADDR_CP5,TI reserved"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PKT_RAM_BASE_ADDR_CP4,TI reserved"
|
|
line.long 0x18 "REG6,Base address for Chirp profile 2 in instruction packet RAM"
|
|
hexmask.long.byte 0x18 24.--31. 1. "PKT_RAM_BASE_ADDR_CP11,TI reserved"
|
|
hexmask.long.byte 0x18 16.--23. 1. "PKT_RAM_BASE_ADDR_CP10,TI reserved"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "PKT_RAM_BASE_ADDR_CP9,TI reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PKT_RAM_BASE_ADDR_CP8,TI reserved"
|
|
line.long 0x1C "REG7,Base address for Chirp profile 3 in instruction packet RAM"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "PKT_RAM_BASE_ADDR_CP15,TI reserved"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "PKT_RAM_BASE_ADDR_CP14,TI reserved"
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--15. 1. "PKT_RAM_BASE_ADDR_CP13,TI reserved"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PKT_RAM_BASE_ADDR_CP12,TI reserved"
|
|
line.long 0x20 "REG8,"
|
|
hexmask.long.tbyte 0x20 9.--31. 1. "NU,"
|
|
bitfld.long 0x20 8. "GPADC_CLK_ENABLE,TI reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--7. 1. "GPADC_CLK_DIV,TI reserved"
|
|
line.long 0x24 "REG9,"
|
|
hexmask.long 0x24 0.--31. 1. "PARAM_NOT_USED_TX_ENA1_OFF,TI reserved"
|
|
line.long 0x28 "REG10,"
|
|
hexmask.long 0x28 0.--31. 1. "PARAM_NOT_USED_TX_ENA2_OFF,TI reserved"
|
|
line.long 0x2C "REG11,"
|
|
hexmask.long 0x2C 0.--31. 1. "PARAM_NOT_USED_TX_ENA3_OFF,TI reserved"
|
|
line.long 0x30 "REG12,"
|
|
hexmask.long.byte 0x30 24.--31. 1. "DRAM_REPAIRED_BIT,TI reserved"
|
|
hexmask.long.byte 0x30 16.--23. 1. "DRAM_ECC_ERR_ADDR,TI reserved"
|
|
newline
|
|
hexmask.long.byte 0x30 9.--15. 1. "NU2,TI reserved"
|
|
bitfld.long 0x30 8. "DRAM_ECC_ERR_CLR,TI reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x30 1.--7. 1. "NU1,TI reserved"
|
|
bitfld.long 0x30 0. "DRAM_ECC_ENABLE," "0,1"
|
|
repeat 2. (list 0xD 0x16)(list 0x0 0x24)
|
|
group.long ($2+0x34)++0x3
|
|
line.long 0x0 "REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "SPARE_WR2,TI reserved"
|
|
repeat.end
|
|
rgroup.long 0x38++0xF
|
|
line.long 0x0 "REG14,Sum of GP ADC readings"
|
|
hexmask.long.word 0x0 20.--31. 1. "NU,TI reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "SUM_IFM,Sum of GP ADC readings"
|
|
line.long 0x4 "REG15,Min and Max of GP ADC readings"
|
|
hexmask.long.byte 0x4 26.--31. 1. "NU2,TI reserved"
|
|
hexmask.long.word 0x4 16.--25. 1. "MAX_GPADC,Max of GPADC readings"
|
|
newline
|
|
hexmask.long.byte 0x4 10.--15. 1. "NU1,TI reserved"
|
|
hexmask.long.word 0x4 0.--9. 1. "MIN_GPADC,Min of GPADC readings"
|
|
line.long 0x8 "REG16,"
|
|
hexmask.long 0x8 1.--31. 1. "NU,TI reserved"
|
|
bitfld.long 0x8 0. "GPADC_MEM_INIT_DONE_STAT,Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress" "0,1"
|
|
line.long 0xC "REG17,"
|
|
hexmask.long 0xC 1.--31. 1. "NU,TI reserved"
|
|
bitfld.long 0xC 0. "GPADC_IFM_DONE_STATUS,Test completion status in IFM mode.Used for FW polling" "0,1"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "REG18,"
|
|
hexmask.long 0x0 1.--31. 1. "NU,TI reserved"
|
|
bitfld.long 0x0 0. "GPADC_IFM_DONE_CLR,Clear 'ifm_done_status'" "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "REG19,"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU,TI reserved"
|
|
hexmask.long.word 0x0 0.--15. 1. "GPADC_SAMPLES_FRAME,Total number of GPADC samples collected in a frame"
|
|
repeat 2. (list 0x14 0x15)(list 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "SPARE_RD1,TI reserved"
|
|
repeat.end
|
|
tree.end
|
|
tree "MSS_I2C"
|
|
base ad:0x2F7B000
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "ICOAR,I2C Own Address register"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU,Reserved"
|
|
hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system."
|
|
line.long 0x4 "ICIMR,I2C Interrupt Mask/Status register"
|
|
hexmask.long 0x4 7.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x4 6. "AAS,Address As Slave interrupt mask bit. Setting a'1' to this bit unmasks the Address As Slave interrupt. Setting a'0' to this bit masks the Address As Slave interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1"
|
|
bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1"
|
|
bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1"
|
|
bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1"
|
|
line.long 0x8 "ICSTR,I2C Interrupt Status register"
|
|
hexmask.long.tbyte 0x8 15.--31. 1. "NU2,Reserved"
|
|
bitfld.long 0x8 14. "SDIR,Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent"
|
|
bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied"
|
|
newline
|
|
bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1"
|
|
bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "AAS,Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )" "0,1"
|
|
bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a'start' or'stop' condition is detected. - (RW )" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "NU1,Reserved" "0,1,2,3"
|
|
bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1"
|
|
bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1"
|
|
bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010).." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1"
|
|
line.long 0xC "ICCLKL,I2C Clock Divider Low register"
|
|
hexmask.long.word 0xC 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."
|
|
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
|
|
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)."
|
|
line.long 0x14 "ICCNT,I2C Data Count register"
|
|
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.."
|
|
line.long 0x18 "ICDRR,I2C Data Receive register"
|
|
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
|
|
line.long 0x1C "ICSAR,I2C Slave Address register"
|
|
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
|
|
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address. Use in both 7- and 10-bit address mode."
|
|
line.long 0x20 "ICDXR,I2C Data Transmit register"
|
|
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
|
|
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
|
|
line.long 0x24 "ICMDR,I2C Mode register"
|
|
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
|
|
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1"
|
|
newline
|
|
bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If.." "?,1: The I2C runs free"
|
|
bitfld.long 0x24 13. "STT,Start Condition (Master only mode). This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1"
|
|
newline
|
|
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509). - (RW )" "0,1"
|
|
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only). This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1"
|
|
newline
|
|
bitfld.long 0x24 10. "MST,Master. MST=0: The I2C peripheral is in the 'slave' mode and clock is received from the 'master' device. MST=1: The I2C peripheral is in the 'master' mode and it generates the clock. This bit is clear when the transfer completed." "0: The I2C peripheral is in the 'slave' mode and..,1: The I2C peripheral is in the 'master' mode and.."
|
|
bitfld.long 0x24 9. "TRX,Transmitter. TRX=0: The I2C is in the 'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I2C is in the 'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes.." "0: The I2C is in the 'receiver' mode and data on..,1: The I2C is in the 'transmitter' mode and the.."
|
|
newline
|
|
bitfld.long 0x24 8. "XA,Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode." "0,1"
|
|
bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only). This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via.." "0,1"
|
|
bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "STB,Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001' regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1"
|
|
bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________ FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode.." "0,1"
|
|
newline
|
|
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
|
|
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved."
|
|
hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing."
|
|
newline
|
|
hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved."
|
|
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "ICEMDR,I2C Extended Mode register"
|
|
hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - (RW )"
|
|
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK.." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1"
|
|
line.long 0x30 "ICPSC,I2C Prescaler register"
|
|
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved."
|
|
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_."
|
|
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
|
|
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved."
|
|
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - (RW )"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )"
|
|
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
|
|
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved."
|
|
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - (RW )"
|
|
line.long 0x3C "ICDMAC,I2C DMA Control Register"
|
|
hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - (RW )"
|
|
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0: DMA transmit event is disabled,1: DMA transmit event is enabled"
|
|
newline
|
|
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0: DMA receive event is disabled,1: DMA receive event is enabled"
|
|
repeat 2. (list 0x1 0x2)(list 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "I2C_RESERVED$1,Reserved"
|
|
hexmask.long 0x0 0.--31. 1. "NU,Reserved."
|
|
repeat.end
|
|
group.long 0x48++0x1B
|
|
line.long 0x0 "ICPFUNC,I2C Pin Function register"
|
|
hexmask.long 0x0 1.--31. 1. "NU,Reserved."
|
|
bitfld.long 0x0 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.."
|
|
line.long 0x4 "ICPDIR,I2C Pin Direction register"
|
|
hexmask.long 0x4 2.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x4 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output"
|
|
newline
|
|
bitfld.long 0x4 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output"
|
|
line.long 0x8 "ICPDIN,I2C Pin Data In register"
|
|
hexmask.long 0x8 2.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x8 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.."
|
|
newline
|
|
bitfld.long 0x8 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.."
|
|
line.long 0xC "ICPDOUT,I2C Pin Data Out register"
|
|
hexmask.long 0xC 2.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xC 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high"
|
|
newline
|
|
bitfld.long 0xC 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.."
|
|
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
|
|
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high"
|
|
newline
|
|
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high"
|
|
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
|
|
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low"
|
|
newline
|
|
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low"
|
|
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
|
|
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode"
|
|
newline
|
|
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode"
|
|
tree.end
|
|
tree "MSS_IOMUX"
|
|
base ad:0x20C0000
|
|
group.long 0x0++0x1DF
|
|
line.long 0x0 "PADAA_cfg_reg,"
|
|
hexmask.long.tbyte 0x0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x4 "PADAB_cfg_reg,"
|
|
hexmask.long.tbyte 0x4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x8 "PADAC_cfg_reg,"
|
|
hexmask.long.tbyte 0x8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xC "PADAD_cfg_reg,"
|
|
hexmask.long.tbyte 0xC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x10 "PADAE_cfg_reg,"
|
|
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x10 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x10 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x10 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x10 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x10 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x10 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x10 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x14 "PADAF_cfg_reg,"
|
|
hexmask.long.tbyte 0x14 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x14 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x14 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x14 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x14 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x14 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x14 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x14 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x18 "PADAG_cfg_reg,"
|
|
hexmask.long.tbyte 0x18 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x18 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x18 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x18 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x18 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x18 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x18 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x18 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1C "PADAH_cfg_reg,"
|
|
hexmask.long.tbyte 0x1C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x20 "PADAI_cfg_reg,"
|
|
hexmask.long.tbyte 0x20 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x20 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x20 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x20 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x20 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x20 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x20 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x20 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x24 "PADAJ_cfg_reg,"
|
|
hexmask.long.tbyte 0x24 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x24 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x24 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x24 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x24 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x24 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x24 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x24 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x28 "PADAK_cfg_reg,"
|
|
hexmask.long.tbyte 0x28 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x28 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x28 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x28 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x28 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x28 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x28 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x28 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x2C "PADAL_cfg_reg,"
|
|
hexmask.long.tbyte 0x2C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x2C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x2C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x2C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x2C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x2C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x2C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x2C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x30 "PADAM_cfg_reg,"
|
|
hexmask.long.tbyte 0x30 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x30 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x30 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x30 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x30 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x30 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x30 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x30 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x34 "PADAN_cfg_reg,"
|
|
hexmask.long.tbyte 0x34 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x34 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x34 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x34 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x34 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x34 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x34 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x34 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x38 "PADAO_cfg_reg,"
|
|
hexmask.long.tbyte 0x38 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x38 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x38 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x38 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x38 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x38 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x38 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x38 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x3C "PADAP_cfg_reg,"
|
|
hexmask.long.tbyte 0x3C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x3C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x3C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x3C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x3C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x3C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x3C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x3C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x40 "PADAQ_cfg_reg,"
|
|
hexmask.long.tbyte 0x40 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x40 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x40 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x40 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x40 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x40 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x40 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x40 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x44 "PADAR_cfg_reg,"
|
|
hexmask.long.tbyte 0x44 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x44 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x44 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x44 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x44 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x44 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x44 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x44 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x48 "PADAS_cfg_reg,"
|
|
hexmask.long.tbyte 0x48 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x48 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x48 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x48 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x48 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x48 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x48 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x48 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x48 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x4C "PADAT_cfg_reg,"
|
|
hexmask.long.tbyte 0x4C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x4C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x4C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x4C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x4C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x4C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x4C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x4C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x50 "PADAU_cfg_reg,"
|
|
hexmask.long.tbyte 0x50 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x50 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x50 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x50 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x50 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x50 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x50 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x50 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x50 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x54 "PADAV_cfg_reg,"
|
|
hexmask.long.tbyte 0x54 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x54 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x54 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x54 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x54 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x54 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x54 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x54 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x58 "PADAW_cfg_reg,"
|
|
hexmask.long.tbyte 0x58 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x58 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x58 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x58 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x58 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x58 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x58 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x58 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x5C "PADAX_cfg_reg,"
|
|
hexmask.long.tbyte 0x5C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x5C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x5C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x5C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x5C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x5C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x5C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x5C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x60 "PADAY_cfg_reg,"
|
|
hexmask.long.tbyte 0x60 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x60 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x60 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x60 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x60 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x60 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x60 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x60 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x60 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x64 "PADAZ_cfg_reg,"
|
|
hexmask.long.tbyte 0x64 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x64 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x64 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x64 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x64 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x64 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x64 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x64 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x68 "PADBA_cfg_reg,"
|
|
hexmask.long.tbyte 0x68 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x68 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x68 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x68 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x68 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x68 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x68 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x68 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x68 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x6C "PADBB_cfg_reg,"
|
|
hexmask.long.tbyte 0x6C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x6C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x6C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x6C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x6C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x6C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x6C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x6C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x70 "PADBC_cfg_reg,"
|
|
hexmask.long.tbyte 0x70 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x70 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x70 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x70 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x70 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x70 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x70 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x70 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x70 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x74 "PADBD_cfg_reg,"
|
|
hexmask.long.tbyte 0x74 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x74 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x74 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x74 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x74 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x74 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x74 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x74 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x78 "PADBE_cfg_reg,"
|
|
hexmask.long.tbyte 0x78 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x78 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x78 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x78 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x78 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x78 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x78 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x78 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x78 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x7C "PADBF_cfg_reg,"
|
|
hexmask.long.tbyte 0x7C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x7C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x7C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x7C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x7C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x7C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x7C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x7C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x80 "PADBG_cfg_reg,"
|
|
hexmask.long.tbyte 0x80 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x80 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x80 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x80 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x80 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x80 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x80 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x80 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x80 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x84 "PADBH_cfg_reg,"
|
|
hexmask.long.tbyte 0x84 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x84 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x84 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x84 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x84 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x84 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x84 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x84 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x88 "PADBI_cfg_reg,"
|
|
hexmask.long.tbyte 0x88 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x88 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x88 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x88 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x88 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x88 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x88 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x88 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x88 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x8C "PADBJ_cfg_reg,"
|
|
hexmask.long.tbyte 0x8C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x8C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x8C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x8C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x8C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x8C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x8C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x8C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x90 "PADBK_cfg_reg,"
|
|
hexmask.long.tbyte 0x90 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x90 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x90 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x90 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x90 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x90 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x90 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x90 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x90 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x94 "PADBL_cfg_reg,"
|
|
hexmask.long.tbyte 0x94 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x94 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x94 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x94 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x94 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x94 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x94 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x94 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x94 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x98 "PADBM_cfg_reg,"
|
|
hexmask.long.tbyte 0x98 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x98 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x98 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x98 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x98 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x98 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x98 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x98 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x98 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x9C "PADBN_cfg_reg,"
|
|
hexmask.long.tbyte 0x9C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x9C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x9C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x9C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x9C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x9C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x9C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x9C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xA0 "PADBO_cfg_reg,"
|
|
hexmask.long.tbyte 0xA0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xA0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xA0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xA0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xA0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xA0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xA0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xA0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xA0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xA4 "PADBP_cfg_reg,"
|
|
hexmask.long.tbyte 0xA4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xA4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xA4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xA4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xA4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xA4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xA4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xA4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xA8 "PADBQ_cfg_reg,"
|
|
hexmask.long.tbyte 0xA8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xA8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xA8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xA8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xA8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xA8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xA8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xA8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xA8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xAC "PADBR_cfg_reg,"
|
|
hexmask.long.tbyte 0xAC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xAC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xAC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xAC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xAC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xAC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xAC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xAC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xAC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xB0 "PADBS_cfg_reg,"
|
|
hexmask.long.tbyte 0xB0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xB0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xB0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xB0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xB0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xB0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xB0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xB0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xB0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xB4 "PADBT_cfg_reg,"
|
|
hexmask.long.tbyte 0xB4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xB4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xB4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xB4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xB4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xB4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xB4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xB4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xB8 "PADBU_cfg_reg,"
|
|
hexmask.long.tbyte 0xB8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xB8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xB8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xB8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xB8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xB8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xB8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xB8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xB8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xBC "PADBV_cfg_reg,"
|
|
hexmask.long.tbyte 0xBC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xBC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xBC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xBC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xBC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xBC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xBC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xBC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xC0 "PADBW_cfg_reg,"
|
|
hexmask.long.tbyte 0xC0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xC0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xC0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xC0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xC0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xC0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xC0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xC0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xC4 "PADBX_cfg_reg,"
|
|
hexmask.long.tbyte 0xC4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xC4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xC4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xC4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xC4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xC4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xC4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xC4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xC8 "PADBY_cfg_reg,"
|
|
hexmask.long.tbyte 0xC8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xC8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xC8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xC8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xC8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xC8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xC8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xC8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xCC "PADBZ_cfg_reg,"
|
|
hexmask.long.tbyte 0xCC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xCC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xCC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xCC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xCC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xCC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xCC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xCC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xD0 "PADCA_cfg_reg,"
|
|
hexmask.long.tbyte 0xD0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xD0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xD0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xD0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xD0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xD0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xD0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xD0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xD0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xD4 "PADCB_cfg_reg,"
|
|
hexmask.long.tbyte 0xD4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xD4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xD4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xD4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xD4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xD4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xD4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xD4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xD4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xD8 "PADCC_cfg_reg,"
|
|
hexmask.long.tbyte 0xD8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xD8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xD8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xD8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xD8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xD8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xD8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xD8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xD8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xDC "PADCD_cfg_reg,"
|
|
hexmask.long.tbyte 0xDC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xDC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xDC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xDC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xDC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xDC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xDC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xDC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xDC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xE0 "PADCE_cfg_reg,"
|
|
hexmask.long.tbyte 0xE0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xE0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xE0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xE0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xE0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xE0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xE0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xE0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xE0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xE4 "PADCF_cfg_reg,"
|
|
hexmask.long.tbyte 0xE4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xE4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xE4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xE4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xE4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xE4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xE4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xE4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xE4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xE8 "PADCG_cfg_reg,"
|
|
hexmask.long.tbyte 0xE8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xE8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xE8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xE8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xE8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xE8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xE8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xE8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xE8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xEC "PADCH_cfg_reg,"
|
|
hexmask.long.tbyte 0xEC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xEC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xEC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xEC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xEC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xEC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xEC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xEC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xEC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xF0 "PADCI_cfg_reg,"
|
|
hexmask.long.tbyte 0xF0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xF0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xF0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xF0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xF0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xF0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xF0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xF0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xF0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xF4 "PADCJ_cfg_reg,"
|
|
hexmask.long.tbyte 0xF4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xF4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xF4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xF4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xF4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xF4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xF4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xF4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xF4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xF8 "PADCK_cfg_reg,"
|
|
hexmask.long.tbyte 0xF8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xF8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xF8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xF8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xF8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xF8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xF8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xF8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xF8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0xFC "PADCL_cfg_reg,"
|
|
hexmask.long.tbyte 0xFC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0xFC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0xFC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0xFC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0xFC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0xFC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0xFC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0xFC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xFC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x100 "PADCM_cfg_reg,"
|
|
hexmask.long.tbyte 0x100 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x100 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x100 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x100 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x100 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x100 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x100 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x100 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x100 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x104 "PADCN_cfg_reg,"
|
|
hexmask.long.tbyte 0x104 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x104 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x104 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x104 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x104 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x104 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x104 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x104 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x104 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x108 "PADCO_cfg_reg,"
|
|
hexmask.long.tbyte 0x108 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x108 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x108 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x108 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x108 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x108 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x108 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x108 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x108 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x10C "PADCP_cfg_reg,"
|
|
hexmask.long.tbyte 0x10C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x10C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x10C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x10C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x10C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x10C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x10C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x10C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x110 "PADCQ_cfg_reg,"
|
|
hexmask.long.tbyte 0x110 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x110 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x110 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x110 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x110 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x110 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x110 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x110 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x110 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x114 "PADCR_cfg_reg,"
|
|
hexmask.long.tbyte 0x114 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x114 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x114 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x114 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x114 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x114 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x114 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x114 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x114 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x118 "PADCS_cfg_reg,"
|
|
hexmask.long.tbyte 0x118 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x118 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x118 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x118 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x118 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x118 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x118 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x118 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x118 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x11C "PADCT_cfg_reg,"
|
|
hexmask.long.tbyte 0x11C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x11C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x11C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x11C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x11C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x11C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x11C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x11C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x11C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x120 "PADCU_cfg_reg,"
|
|
hexmask.long.tbyte 0x120 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x120 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x120 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x120 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x120 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x120 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x120 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x120 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x120 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x124 "PADCV_cfg_reg,"
|
|
hexmask.long.tbyte 0x124 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x124 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x124 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x124 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x124 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x124 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x124 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x124 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x124 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x128 "PADCW_cfg_reg,"
|
|
hexmask.long.tbyte 0x128 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x128 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x128 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x128 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x128 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x128 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x128 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x128 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x128 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x12C "PADCX_cfg_reg,"
|
|
hexmask.long.tbyte 0x12C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x12C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x12C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x12C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x12C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x12C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x12C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x12C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x12C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x130 "PADCY_cfg_reg,"
|
|
hexmask.long.tbyte 0x130 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x130 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x130 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x130 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x130 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x130 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x130 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x130 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x130 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x134 "PADCZ_cfg_reg,"
|
|
hexmask.long.tbyte 0x134 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x134 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x134 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x134 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x134 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x134 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x134 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x134 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x134 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x138 "PADDA_cfg_reg,"
|
|
hexmask.long.tbyte 0x138 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x138 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x138 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x138 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x138 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x138 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x138 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x138 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x138 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x13C "PADDB_cfg_reg,"
|
|
hexmask.long.tbyte 0x13C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x13C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x13C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x13C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x13C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x13C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x13C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x13C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x13C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x140 "PADDC_cfg_reg,"
|
|
hexmask.long.tbyte 0x140 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x140 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x140 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x140 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x140 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x140 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x140 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x140 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x140 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x144 "PADDD_cfg_reg,"
|
|
hexmask.long.tbyte 0x144 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x144 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x144 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x144 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x144 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x144 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x144 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x144 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x144 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x148 "PADDE_cfg_reg,"
|
|
hexmask.long.tbyte 0x148 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x148 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x148 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x148 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x148 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x148 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x148 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x148 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x148 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x14C "PADDF_cfg_reg,"
|
|
hexmask.long.tbyte 0x14C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x14C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x14C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x14C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x14C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x14C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x14C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x14C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x150 "PADDG_cfg_reg,"
|
|
hexmask.long.tbyte 0x150 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x150 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x150 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x150 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x150 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x150 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x150 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x150 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x150 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x154 "PADDH_cfg_reg,"
|
|
hexmask.long.tbyte 0x154 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x154 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x154 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x154 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x154 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x154 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x154 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x154 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x154 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x158 "PADDI_cfg_reg,"
|
|
hexmask.long.tbyte 0x158 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x158 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x158 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x158 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x158 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x158 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x158 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x158 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x158 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x15C "PADDJ_cfg_reg,"
|
|
hexmask.long.tbyte 0x15C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x15C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x15C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x15C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x15C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x15C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x15C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x15C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x15C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x160 "PADDK_cfg_reg,"
|
|
hexmask.long.tbyte 0x160 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x160 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x160 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x160 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x160 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x160 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x160 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x160 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x160 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x164 "PADDL_cfg_reg,"
|
|
hexmask.long.tbyte 0x164 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x164 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x164 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x164 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x164 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x164 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x164 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x164 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x164 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x168 "PADDM_cfg_reg,"
|
|
hexmask.long.tbyte 0x168 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x168 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x168 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x168 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x168 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x168 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x168 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x168 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x168 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x16C "PADDN_cfg_reg,"
|
|
hexmask.long.tbyte 0x16C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x16C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x16C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x16C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x16C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x16C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x16C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x16C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x16C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x170 "PADDO_cfg_reg,"
|
|
hexmask.long.tbyte 0x170 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x170 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x170 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x170 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x170 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x170 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x170 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x170 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x170 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x174 "PADDP_cfg_reg,"
|
|
hexmask.long.tbyte 0x174 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x174 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x174 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x174 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x174 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x174 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x174 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x174 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x174 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x178 "PADDQ_cfg_reg,"
|
|
hexmask.long.tbyte 0x178 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x178 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x178 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x178 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x178 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x178 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x178 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x178 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x178 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x17C "PADDR_cfg_reg,"
|
|
hexmask.long.tbyte 0x17C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x17C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x17C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x17C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x17C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x17C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x17C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x17C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x17C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x180 "PADDS_cfg_reg,"
|
|
hexmask.long.tbyte 0x180 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x180 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x180 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x180 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x180 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x180 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x180 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x180 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x180 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x184 "PADDT_cfg_reg,"
|
|
hexmask.long.tbyte 0x184 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x184 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x184 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x184 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x184 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x184 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x184 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x184 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x184 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x188 "PADDU_cfg_reg,"
|
|
hexmask.long.tbyte 0x188 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x188 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x188 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x188 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x188 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x188 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x188 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x188 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x188 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x18C "PADDV_cfg_reg,"
|
|
hexmask.long.tbyte 0x18C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x18C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x18C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x18C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x18C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x18C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x18C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x18C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x190 "PADDW_cfg_reg,"
|
|
hexmask.long.tbyte 0x190 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x190 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x190 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x190 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x190 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x190 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x190 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x190 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x190 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x194 "PADDX_cfg_reg,"
|
|
hexmask.long.tbyte 0x194 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x194 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x194 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x194 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x194 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x194 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x194 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x194 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x194 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x198 "PADDY_cfg_reg,"
|
|
hexmask.long.tbyte 0x198 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x198 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x198 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x198 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x198 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x198 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x198 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x198 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x198 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x19C "PADDZ_cfg_reg,"
|
|
hexmask.long.tbyte 0x19C 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x19C 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x19C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x19C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x19C 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x19C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x19C 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x19C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x19C 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1A0 "PADEA_cfg_reg,"
|
|
hexmask.long.tbyte 0x1A0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1A0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1A0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1A0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1A0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1A0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1A0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1A0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1A0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1A4 "PADEB_cfg_reg,"
|
|
hexmask.long.tbyte 0x1A4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1A4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1A4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1A4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1A4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1A4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1A4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1A4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1A4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1A8 "PADEC_cfg_reg,"
|
|
hexmask.long.tbyte 0x1A8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1A8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1A8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1A8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1A8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1A8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1A8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1A8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1A8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1AC "PADED_cfg_reg,"
|
|
hexmask.long.tbyte 0x1AC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1AC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1AC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1AC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1AC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1AC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1AC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1AC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1AC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1B0 "PADEE_cfg_reg,"
|
|
hexmask.long.tbyte 0x1B0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1B0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1B0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1B0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1B0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1B0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1B0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1B0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
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|
newline
|
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hexmask.long.byte 0x1B0 0.--3. 1. "func_sel,Function select"
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|
line.long 0x1B4 "PADEF_cfg_reg,"
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|
hexmask.long.tbyte 0x1B4 11.--31. 1. "NU,Reserved"
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|
bitfld.long 0x1B4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1B4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1B4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
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bitfld.long 0x1B4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1B4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1B4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1B4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
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hexmask.long.byte 0x1B4 0.--3. 1. "func_sel,Function select"
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line.long 0x1B8 "PADEG_cfg_reg,"
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hexmask.long.tbyte 0x1B8 11.--31. 1. "NU,Reserved"
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bitfld.long 0x1B8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1B8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1B8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
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bitfld.long 0x1B8 7. "oe_override,Active Low Output Override" "0,1"
|
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bitfld.long 0x1B8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1B8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1B8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
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hexmask.long.byte 0x1B8 0.--3. 1. "func_sel,Function select"
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line.long 0x1BC "PADEH_cfg_reg,"
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|
hexmask.long.tbyte 0x1BC 11.--31. 1. "NU,Reserved"
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bitfld.long 0x1BC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1BC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1BC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
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bitfld.long 0x1BC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1BC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1BC 5. "ie_override,Active Low Input Override" "0,1"
|
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bitfld.long 0x1BC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
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hexmask.long.byte 0x1BC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1C0 "PADEI_cfg_reg,"
|
|
hexmask.long.tbyte 0x1C0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1C0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1C0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1C0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
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bitfld.long 0x1C0 7. "oe_override,Active Low Output Override" "0,1"
|
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bitfld.long 0x1C0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1C0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1C0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1C4 "PADEJ_cfg_reg,"
|
|
hexmask.long.tbyte 0x1C4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1C4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1C4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1C4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1C4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1C4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1C4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1C4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1C8 "PADEK_cfg_reg,"
|
|
hexmask.long.tbyte 0x1C8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1C8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1C8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1C8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1C8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1C8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1C8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1C8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1CC "PADEL_cfg_reg,"
|
|
hexmask.long.tbyte 0x1CC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1CC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1CC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1CC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1CC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1CC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1CC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1CC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1CC 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1D0 "PADEM_cfg_reg,"
|
|
hexmask.long.tbyte 0x1D0 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1D0 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1D0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1D0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1D0 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1D0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1D0 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1D0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1D0 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1D4 "PADEN_cfg_reg,"
|
|
hexmask.long.tbyte 0x1D4 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1D4 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1D4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1D4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1D4 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1D4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1D4 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1D4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1D4 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1D8 "PADEO_cfg_reg,"
|
|
hexmask.long.tbyte 0x1D8 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1D8 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1D8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1D8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1D8 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1D8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1D8 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1D8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1D8 0.--3. 1. "func_sel,Function select"
|
|
line.long 0x1DC "PADEP_cfg_reg,"
|
|
hexmask.long.tbyte 0x1DC 11.--31. 1. "NU,Reserved"
|
|
bitfld.long 0x1DC 10. "sc1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate"
|
|
bitfld.long 0x1DC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0: Pull Down,?"
|
|
bitfld.long 0x1DC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0: Enable,?"
|
|
newline
|
|
bitfld.long 0x1DC 7. "oe_override,Active Low Output Override" "0,1"
|
|
bitfld.long 0x1DC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
|
|
bitfld.long 0x1DC 5. "ie_override,Active Low Input Override" "0,1"
|
|
bitfld.long 0x1DC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1DC 0.--3. 1. "func_sel,Function select"
|
|
group.long 0x1F0++0xF
|
|
line.long 0x0 "USERMODEEN,"
|
|
hexmask.long 0x0 0.--31. 1. "USERMODEEN,Write 0XADADADAD to enable user mode write access to IO CFG space"
|
|
line.long 0x4 "PADGLBLCFGREG,"
|
|
hexmask.long 0x4 0.--31. 1. "PADGLBLCFGREG,2:0 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs. 3 : global_ie_n_val - Active low 10:8 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs. 11 :.."
|
|
line.long 0x8 "IOCFGKICK0,"
|
|
hexmask.long 0x8 0.--31. 1. "IOCFGKICK0,Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the above PIN MUX registers (including IOCFGKICK1)"
|
|
line.long 0xC "IOCFGKICK1,"
|
|
hexmask.long 0xC 0.--31. 1. "IOCFGKICK1,Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers (excluding IOCFGKICK0). IOCFGKICK0 has to be written with 83E70B13h to enable access to.."
|
|
tree.end
|
|
tree "MSS_MCANA_CFG"
|
|
base ad:0x2F7FC00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SS_PID,SS_PID"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SS_CTRL,SS_CTRL"
|
|
hexmask.long 0x0 7.--31. 1. "NU0,Reserved"
|
|
bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
|
|
bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
|
|
bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend"
|
|
rbitfld.long 0x0 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SS_STAT,SS_STAT"
|
|
hexmask.long 0x0 3.--31. 1. "NU1,Reserved"
|
|
bitfld.long 0x0 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
|
|
bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done"
|
|
newline
|
|
bitfld.long 0x0 0. "NU,Reserved" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SS_ICS,SS_ICS"
|
|
hexmask.long 0x0 1.--31. 1. "NU2,Reserved"
|
|
bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SS_IRS,SS_IRS"
|
|
hexmask.long 0x0 1.--31. 1. "NU3,Reserved"
|
|
bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "SS_IECS,SS_IECS"
|
|
hexmask.long 0x0 1.--31. 1. "NU4,Reserved"
|
|
bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)" "0,1"
|
|
line.long 0x4 "SS_IE,SS_IE"
|
|
hexmask.long 0x4 1.--31. 1. "NU5,Reserved"
|
|
bitfld.long 0x4 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SS_IES,SS_IES"
|
|
hexmask.long 0x0 1.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "SS_EOI,SS_EOI"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "NU7,Reserved"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS.."
|
|
line.long 0x4 "SS_EXT_TS_PS,SS_EXT_TS_PS"
|
|
hexmask.long.byte 0x4 24.--31. 1. "NU8,Reserved"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1 ."
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
|
|
hexmask.long 0x0 5.--31. 1. "NU9,Reserved"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)"
|
|
rgroup.long 0x200++0xB
|
|
line.long 0x0 "CREL,CREL"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,ENDN"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value"
|
|
line.long 0x8 "CUST,CUST"
|
|
hexmask.long 0x8 0.--31. 1. "CUST,Custom"
|
|
group.long 0x20C++0x23
|
|
line.long 0x0 "DBTP,DBTP"
|
|
hexmask.long.byte 0x0 24.--31. 1. "NU13,Reserved"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1"
|
|
rbitfld.long 0x0 21.--22. "NU12,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler"
|
|
rbitfld.long 0x0 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width"
|
|
line.long 0x4 "TEST,TEST"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "NU15,Reserved"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0,1"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "NU14,Reserved"
|
|
line.long 0x8 "RWD,RWD"
|
|
hexmask.long.word 0x8 16.--31. 1. "NU16,Reserved"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value"
|
|
line.long 0xC "CCCR,CCCR"
|
|
hexmask.long.tbyte 0xC 15.--31. 1. "NU18,Reserved"
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1"
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
rbitfld.long 0xC 10.--11. "NU17,Reserved" "0,1,2,3"
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1"
|
|
bitfld.long 0xC 7. "TEST,Test Mode enable" "0,1"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1"
|
|
rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "ASM,Restriced Operation Mode" "0,1"
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0,1"
|
|
line.long 0x10 "NBTP,NBTP"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
newline
|
|
rbitfld.long 0x10 7. "NU19,Reserved" "0,1"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,TSCC"
|
|
hexmask.long.word 0x14 20.--31. 1. "NU21,Reserved"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
hexmask.long.word 0x14 2.--15. 1. "NU20,Reserved"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
|
|
line.long 0x18 "TSCV,TSCV"
|
|
hexmask.long.word 0x18 16.--31. 1. "NU22,Reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
|
|
line.long 0x1C "TOCC,TOCC"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
hexmask.long.word 0x1C 3.--15. 1. "NU23,Reserved"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
line.long 0x20 "TOCV,TOCV"
|
|
hexmask.long.word 0x20 16.--31. 1. "NU24,Reserved"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC)
|
|
rgroup.long ($2+0x230)++0x3
|
|
line.long 0x0 "RES$1,RES00"
|
|
hexmask.long 0x0 0.--31. 1. "RES00,Reserved"
|
|
repeat.end
|
|
rgroup.long 0x2FC++0x3
|
|
line.long 0x0 "RES16,RES00"
|
|
hexmask.long 0x0 0.--31. 1. "RES00,Reserved"
|
|
rgroup.long 0x240++0x7
|
|
line.long 0x0 "ECR,ECR"
|
|
hexmask.long.byte 0x0 24.--31. 1. "NU25,Reserved"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Recieve Error Passive" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,PSR"
|
|
hexmask.long.word 0x4 23.--31. 1. "NU27,Reserved"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 15. "NU26,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "BO,Bus_Off status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x248++0x3
|
|
line.long 0x0 "TDCR,TDCR"
|
|
hexmask.long.tbyte 0x0 15.--31. 1. "NU29,Reserved"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
rbitfld.long 0x0 7. "NU28,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long 0x250++0xF
|
|
line.long 0x0 "IR,IR"
|
|
rbitfld.long 0x0 30.--31. "NU30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Complete" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "IE,IE"
|
|
rbitfld.long 0x4 30.--31. "NU31,Reserved" "0,1,2,3"
|
|
bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,ILS"
|
|
rbitfld.long 0x8 30.--31. "NU32,Reserved" "0,1,2,3"
|
|
bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1"
|
|
bitfld.long 0x8 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,ILE"
|
|
hexmask.long 0xC 2.--31. 1. "NU33,Reserved"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "GFC,GFC"
|
|
hexmask.long 0x0 6.--31. 1. "NU34,Reserved"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,reject Remote Frames Extended" "0,1"
|
|
line.long 0x4 "SIDFC,SIDFC"
|
|
hexmask.long.byte 0x4 24.--31. 1. "NU36,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
|
|
newline
|
|
rbitfld.long 0x4 0.--1. "NU35,Reserved" "0,1,2,3"
|
|
line.long 0x8 "XIDFC,XIDFC"
|
|
hexmask.long.byte 0x8 24.--31. 1. "NU38,Reserved"
|
|
hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Standard"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
|
|
newline
|
|
rbitfld.long 0x8 0.--1. "NU37,Reserved" "0,1,2,3"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "XIDAM,XIDAM"
|
|
rbitfld.long 0x0 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x294++0x3
|
|
line.long 0x0 "HPMS,HPMS"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU40,Reserved"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x298++0xB
|
|
line.long 0x0 "NDAT1,NDAT1"
|
|
hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 0-31"
|
|
line.long 0x4 "NDAT2,NDAT2"
|
|
hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 32-63"
|
|
line.long 0x8 "RXF0C,RXF0C"
|
|
bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
rbitfld.long 0x8 23. "NU42_1,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
rbitfld.long 0x8 15. "NU42,Reserved" "0,1"
|
|
hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
newline
|
|
rbitfld.long 0x8 0.--1. "NU41,Reserved" "0,1,2,3"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "RXF0S,RXF0S"
|
|
hexmask.long.byte 0x0 26.--31. 1. "NU46,Reserved"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "NU45,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
bitfld.long 0x0 14.--15. "NU44,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
bitfld.long 0x0 7. "NU43,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long 0x2A8++0xB
|
|
line.long 0x0 "RXF0A,RXF0A"
|
|
hexmask.long 0x0 6.--31. 1. "NU47,Reserved"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,RXBC"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU49,Reserved"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
rbitfld.long 0x4 0.--1. "NU48,Reserved" "0,1,2,3"
|
|
line.long 0x8 "RXF1C,RXF1C"
|
|
bitfld.long 0x8 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
|
|
rbitfld.long 0x8 23. "NU50_1,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 0 Size"
|
|
rbitfld.long 0x8 15. "NU50,Reserved" "0,1"
|
|
hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
|
|
newline
|
|
rbitfld.long 0x8 0.--1. "NU499,Reserved" "0,1,2,3"
|
|
rgroup.long 0x2B4++0x3
|
|
line.long 0x0 "RXF1S,RXF1S"
|
|
hexmask.long.byte 0x0 26.--31. 1. "NU54,Reserved"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "NU53,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 0 Put Index"
|
|
bitfld.long 0x0 14.--15. "NU52,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 0 Get Index"
|
|
bitfld.long 0x0 7. "NU51,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
|
|
group.long 0x2B8++0x7
|
|
line.long 0x0 "RXF1A,RXF1A"
|
|
hexmask.long 0x0 6.--31. 1. "NU55,Reserved"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXESC,RXESC"
|
|
hexmask.long.tbyte 0x4 11.--31. 1. "NU58,Reserved"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x4 7. "NU57,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x4 3. "NU56,Reserved" "0,1"
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C0++0x7
|
|
line.long 0x0 "TXBC,TXBC"
|
|
bitfld.long 0x0 31. "NU61,Reserved" "0,1"
|
|
bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "NU60,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "NU59,Reserved" "0,1,2,3"
|
|
line.long 0x4 "TXFQS,TXFQS"
|
|
hexmask.long.word 0x4 22.--31. 1. "NU64,Reserved"
|
|
bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index"
|
|
bitfld.long 0x4 6.--7. "NU62,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "TXESC,TXESC"
|
|
hexmask.long 0x0 3.--31. 1. "NU65,Reserved"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2CC++0x3
|
|
line.long 0x0 "TXBRP,TXBRP"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long 0x2D0++0x7
|
|
line.long 0x0 "TXBAR,TXBAR"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add request"
|
|
line.long 0x4 "TXBCR,TXBCR"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long 0x2D8++0x7
|
|
line.long 0x0 "TXBTO,TXBTO"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,TXBCF"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long 0x2E0++0x7
|
|
line.long 0x0 "TXBTIE,TXBTIE"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,TXBCIE"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long 0x2F0++0x3
|
|
line.long 0x0 "TXEFC,TXEFC"
|
|
bitfld.long 0x0 30.--31. "NU68,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
bitfld.long 0x0 22.--23. "NU67,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
bitfld.long 0x0 0.--1. "NU66,Reserved" "0,1,2,3"
|
|
rgroup.long 0x2F4++0x7
|
|
line.long 0x0 "TXEFS,TXEFS"
|
|
hexmask.long.byte 0x0 26.--31. 1. "NU72,Reserved"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
bitfld.long 0x0 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
bitfld.long 0x0 6.--7. "NU69,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level"
|
|
line.long 0x4 "TXEFA,TXEFA"
|
|
hexmask.long 0x4 5.--31. 1. "NU73,Reserved"
|
|
hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree "MSS_MCANA_ECC"
|
|
base ad:0x2F7F800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "REV,Aggregator Revision Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
|
|
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "VECTOR,ECC Vector Register"
|
|
hexmask.long.byte 0x0 25.--31. 1. "NU1,Reserved"
|
|
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address"
|
|
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "NU0,Reserved"
|
|
hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "STAT,Misc Status"
|
|
hexmask.long.tbyte 0x0 11.--31. 1. "NU2,Reserved"
|
|
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "CTRL,CTRL"
|
|
hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved"
|
|
bitfld.long 0x0 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
|
|
bitfld.long 0x0 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
|
|
bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1"
|
|
bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
|
|
bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
|
|
bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
|
|
line.long 0x4 "ERR_CTRL1,ERR_CTRL1"
|
|
hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
|
|
line.long 0x8 "ERR_CTRL2,ERR_CTRL2"
|
|
hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
|
|
hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
|
|
line.long 0xC "ERR_STAT1,ERR_STAT1"
|
|
hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
|
|
bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1"
|
|
bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1"
|
|
bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1"
|
|
bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "ERR_STAT2,ERR_STAT2"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ERR_STAT3,ERR_STAT3"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved"
|
|
bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
|
|
hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved"
|
|
bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SEC_EOI_REG,EOI Register"
|
|
hexmask.long 0x0 1.--31. 1. "NU7,Reserved"
|
|
bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "SEC_STATUS_REG0,Interrupt Status Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU8,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1"
|
|
bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU9,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU10,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
group.long 0x13C++0x3
|
|
line.long 0x0 "DED_EOI_REG,EOI Register"
|
|
hexmask.long 0x0 1.--31. 1. "NU11,Reserved"
|
|
bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DED_STATUS_REG0,Interrupt Status Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU12,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1"
|
|
bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU13,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
|
|
hexmask.long 0x0 2.--31. 1. "NU15,Reserved"
|
|
bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
line.long 0x4 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
|
|
hexmask.long 0x4 2.--31. 1. "NU16,Reserved"
|
|
bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
line.long 0x8 "AGGR_STATUS_SET,AGGR interrupt status set Register"
|
|
hexmask.long 0x8 4.--31. 1. "NU17,Reserved"
|
|
bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
line.long 0xC "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
|
|
hexmask.long 0xC 4.--31. 1. "NU18,Reserved"
|
|
bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
tree.end
|
|
tree "MSS_MCANB_CFG"
|
|
base ad:0x3F7FC00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SS_PID,SS_PID"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SS_CTRL,SS_CTRL"
|
|
hexmask.long 0x0 7.--31. 1. "NU0,Reserved"
|
|
bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
|
|
bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
|
|
bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0: Honor Debug Suspend,1: Disregard debug suspend"
|
|
rbitfld.long 0x0 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SS_STAT,SS_STAT"
|
|
hexmask.long 0x0 3.--31. 1. "NU1,Reserved"
|
|
bitfld.long 0x0 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
|
|
bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done"
|
|
newline
|
|
bitfld.long 0x0 0. "NU,Reserved" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SS_ICS,SS_ICS"
|
|
hexmask.long 0x0 1.--31. 1. "NU2,Reserved"
|
|
bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SS_IRS,SS_IRS"
|
|
hexmask.long 0x0 1.--31. 1. "NU3,Reserved"
|
|
bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "SS_IECS,SS_IECS"
|
|
hexmask.long 0x0 1.--31. 1. "NU4,Reserved"
|
|
bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)" "0,1"
|
|
line.long 0x4 "SS_IE,SS_IE"
|
|
hexmask.long 0x4 1.--31. 1. "NU5,Reserved"
|
|
bitfld.long 0x4 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SS_IES,SS_IES"
|
|
hexmask.long 0x0 1.--31. 1. "NU6,Reserved"
|
|
bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "SS_EOI,SS_EOI"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "NU7,Reserved"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS.."
|
|
line.long 0x4 "SS_EXT_TS_PS,SS_EXT_TS_PS"
|
|
hexmask.long.byte 0x4 24.--31. 1. "NU8,Reserved"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1 ."
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
|
|
hexmask.long 0x0 5.--31. 1. "NU9,Reserved"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)"
|
|
rgroup.long 0x200++0xB
|
|
line.long 0x0 "CREL,CREL"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,ENDN"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value"
|
|
line.long 0x8 "CUST,CUST"
|
|
hexmask.long 0x8 0.--31. 1. "CUST,Custom"
|
|
group.long 0x20C++0x23
|
|
line.long 0x0 "DBTP,DBTP"
|
|
hexmask.long.byte 0x0 24.--31. 1. "NU13,Reserved"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1"
|
|
rbitfld.long 0x0 21.--22. "NU12,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler"
|
|
rbitfld.long 0x0 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width"
|
|
line.long 0x4 "TEST,TEST"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "NU15,Reserved"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0,1"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "NU14,Reserved"
|
|
line.long 0x8 "RWD,RWD"
|
|
hexmask.long.word 0x8 16.--31. 1. "NU16,Reserved"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value"
|
|
line.long 0xC "CCCR,CCCR"
|
|
hexmask.long.tbyte 0xC 15.--31. 1. "NU18,Reserved"
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1"
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
rbitfld.long 0xC 10.--11. "NU17,Reserved" "0,1,2,3"
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1"
|
|
bitfld.long 0xC 7. "TEST,Test Mode enable" "0,1"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1"
|
|
rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "ASM,Restriced Operation Mode" "0,1"
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1"
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0,1"
|
|
line.long 0x10 "NBTP,NBTP"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
newline
|
|
rbitfld.long 0x10 7. "NU19,Reserved" "0,1"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,TSCC"
|
|
hexmask.long.word 0x14 20.--31. 1. "NU21,Reserved"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
hexmask.long.word 0x14 2.--15. 1. "NU20,Reserved"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
|
|
line.long 0x18 "TSCV,TSCV"
|
|
hexmask.long.word 0x18 16.--31. 1. "NU22,Reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
|
|
line.long 0x1C "TOCC,TOCC"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
hexmask.long.word 0x1C 3.--15. 1. "NU23,Reserved"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
line.long 0x20 "TOCV,TOCV"
|
|
hexmask.long.word 0x20 16.--31. 1. "NU24,Reserved"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC)
|
|
rgroup.long ($2+0x230)++0x3
|
|
line.long 0x0 "RES$1,RES00"
|
|
hexmask.long 0x0 0.--31. 1. "RES00,Reserved"
|
|
repeat.end
|
|
rgroup.long 0x2FC++0x3
|
|
line.long 0x0 "RES16,RES00"
|
|
hexmask.long 0x0 0.--31. 1. "RES00,Reserved"
|
|
rgroup.long 0x240++0x7
|
|
line.long 0x0 "ECR,ECR"
|
|
hexmask.long.byte 0x0 24.--31. 1. "NU25,Reserved"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Recieve Error Passive" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,PSR"
|
|
hexmask.long.word 0x4 23.--31. 1. "NU27,Reserved"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 15. "NU26,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
|
|
bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "BO,Bus_Off status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x248++0x3
|
|
line.long 0x0 "TDCR,TDCR"
|
|
hexmask.long.tbyte 0x0 15.--31. 1. "NU29,Reserved"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
rbitfld.long 0x0 7. "NU28,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long 0x250++0xF
|
|
line.long 0x0 "IR,IR"
|
|
rbitfld.long 0x0 30.--31. "NU30,Reserved" "0,1,2,3"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in data Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Complete" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0,1"
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1"
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "IE,IE"
|
|
rbitfld.long 0x4 30.--31. "NU31,Reserved" "0,1,2,3"
|
|
bitfld.long 0x4 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority message Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,ILS"
|
|
rbitfld.long 0x8 30.--31. "NU32,Reserved" "0,1,2,3"
|
|
bitfld.long 0x8 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority message Interrupt Line" "0,1"
|
|
bitfld.long 0x8 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,ILE"
|
|
hexmask.long 0xC 2.--31. 1. "NU33,Reserved"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "GFC,GFC"
|
|
hexmask.long 0x0 6.--31. 1. "NU34,Reserved"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,reject Remote Frames Extended" "0,1"
|
|
line.long 0x4 "SIDFC,SIDFC"
|
|
hexmask.long.byte 0x4 24.--31. 1. "NU36,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS_S,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
|
|
newline
|
|
rbitfld.long 0x4 0.--1. "NU35,Reserved" "0,1,2,3"
|
|
line.long 0x8 "XIDFC,XIDFC"
|
|
hexmask.long.byte 0x8 24.--31. 1. "NU38,Reserved"
|
|
hexmask.long.byte 0x8 16.--23. 1. "LSS_X,List Size Standard"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
|
|
newline
|
|
rbitfld.long 0x8 0.--1. "NU37,Reserved" "0,1,2,3"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "XIDAM,XIDAM"
|
|
rbitfld.long 0x0 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x294++0x3
|
|
line.long 0x0 "HPMS,HPMS"
|
|
hexmask.long.word 0x0 16.--31. 1. "NU40,Reserved"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x298++0xB
|
|
line.long 0x0 "NDAT1,NDAT1"
|
|
hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 0-31"
|
|
line.long 0x4 "NDAT2,NDAT2"
|
|
hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 32-63"
|
|
line.long 0x8 "RXF0C,RXF0C"
|
|
bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
rbitfld.long 0x8 23. "NU42_1,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
rbitfld.long 0x8 15. "NU42,Reserved" "0,1"
|
|
hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
newline
|
|
rbitfld.long 0x8 0.--1. "NU41,Reserved" "0,1,2,3"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "RXF0S,RXF0S"
|
|
hexmask.long.byte 0x0 26.--31. 1. "NU46,Reserved"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "NU45,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
bitfld.long 0x0 14.--15. "NU44,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
bitfld.long 0x0 7. "NU43,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long 0x2A8++0xB
|
|
line.long 0x0 "RXF0A,RXF0A"
|
|
hexmask.long 0x0 6.--31. 1. "NU47,Reserved"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,RXBC"
|
|
hexmask.long.word 0x4 16.--31. 1. "NU49,Reserved"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
rbitfld.long 0x4 0.--1. "NU48,Reserved" "0,1,2,3"
|
|
line.long 0x8 "RXF1C,RXF1C"
|
|
bitfld.long 0x8 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
|
|
rbitfld.long 0x8 23. "NU50_1,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 0 Size"
|
|
rbitfld.long 0x8 15. "NU50,Reserved" "0,1"
|
|
hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
|
|
newline
|
|
rbitfld.long 0x8 0.--1. "NU499,Reserved" "0,1,2,3"
|
|
rgroup.long 0x2B4++0x3
|
|
line.long 0x0 "RXF1S,RXF1S"
|
|
hexmask.long.byte 0x0 26.--31. 1. "NU54,Reserved"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "NU53,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 0 Put Index"
|
|
bitfld.long 0x0 14.--15. "NU52,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 0 Get Index"
|
|
bitfld.long 0x0 7. "NU51,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
|
|
group.long 0x2B8++0x7
|
|
line.long 0x0 "RXF1A,RXF1A"
|
|
hexmask.long 0x0 6.--31. 1. "NU55,Reserved"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXESC,RXESC"
|
|
hexmask.long.tbyte 0x4 11.--31. 1. "NU58,Reserved"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x4 7. "NU57,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x4 3. "NU56,Reserved" "0,1"
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C0++0x7
|
|
line.long 0x0 "TXBC,TXBC"
|
|
bitfld.long 0x0 31. "NU61,Reserved" "0,1"
|
|
bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "NU60,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "NU59,Reserved" "0,1,2,3"
|
|
line.long 0x4 "TXFQS,TXFQS"
|
|
hexmask.long.word 0x4 22.--31. 1. "NU64,Reserved"
|
|
bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index"
|
|
bitfld.long 0x4 6.--7. "NU62,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "TXESC,TXESC"
|
|
hexmask.long 0x0 3.--31. 1. "NU65,Reserved"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2CC++0x3
|
|
line.long 0x0 "TXBRP,TXBRP"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long 0x2D0++0x7
|
|
line.long 0x0 "TXBAR,TXBAR"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add request"
|
|
line.long 0x4 "TXBCR,TXBCR"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long 0x2D8++0x7
|
|
line.long 0x0 "TXBTO,TXBTO"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,TXBCF"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long 0x2E0++0x7
|
|
line.long 0x0 "TXBTIE,TXBTIE"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,TXBCIE"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long 0x2F0++0x3
|
|
line.long 0x0 "TXEFC,TXEFC"
|
|
bitfld.long 0x0 30.--31. "NU68,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
bitfld.long 0x0 22.--23. "NU67,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
bitfld.long 0x0 0.--1. "NU66,Reserved" "0,1,2,3"
|
|
rgroup.long 0x2F4++0x7
|
|
line.long 0x0 "TXEFS,TXEFS"
|
|
hexmask.long.byte 0x0 26.--31. 1. "NU72,Reserved"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
bitfld.long 0x0 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
bitfld.long 0x0 6.--7. "NU69,Reserved" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level"
|
|
line.long 0x4 "TXEFA,TXEFA"
|
|
hexmask.long 0x4 5.--31. 1. "NU73,Reserved"
|
|
hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree "MSS_MCANB_ECC"
|
|
base ad:0x3F7F800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "REV,Aggregator Revision Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID"
|
|
hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "VECTOR,ECC Vector Register"
|
|
hexmask.long.byte 0x0 25.--31. 1. "NU1,Reserved"
|
|
bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address"
|
|
bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--14. 1. "NU0,Reserved"
|
|
hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "STAT,Misc Status"
|
|
hexmask.long.tbyte 0x0 11.--31. 1. "NU2,Reserved"
|
|
hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "CTRL,CTRL"
|
|
hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved"
|
|
bitfld.long 0x0 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
|
|
bitfld.long 0x0 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
|
|
bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1"
|
|
bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
|
|
bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
|
|
bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
|
|
line.long 0x4 "ERR_CTRL1,ERR_CTRL1"
|
|
hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set"
|
|
line.long 0x8 "ERR_CTRL2,ERR_CTRL2"
|
|
hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
|
|
hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
|
|
line.long 0xC "ERR_STAT1,ERR_STAT1"
|
|
hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
|
|
bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1"
|
|
bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1"
|
|
bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1"
|
|
bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "ERR_STAT2,ERR_STAT2"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ERR_STAT3,ERR_STAT3"
|
|
hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved"
|
|
bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
|
|
hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved"
|
|
bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SEC_EOI_REG,EOI Register"
|
|
hexmask.long 0x0 1.--31. 1. "NU7,Reserved"
|
|
bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "SEC_STATUS_REG0,Interrupt Status Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU8,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1"
|
|
bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU9,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU10,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
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|
group.long 0x13C++0x3
|
|
line.long 0x0 "DED_EOI_REG,EOI Register"
|
|
hexmask.long 0x0 1.--31. 1. "NU11,Reserved"
|
|
bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1"
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|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DED_STATUS_REG0,Interrupt Status Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU12,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1"
|
|
bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1"
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU13,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x0 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
|
|
hexmask.long 0x0 2.--31. 1. "NU14,Reserved"
|
|
bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
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|
bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
group.long 0x200++0xF
|
|
line.long 0x0 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
|
|
hexmask.long 0x0 2.--31. 1. "NU15,Reserved"
|
|
bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1"
|
|
line.long 0x4 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
|
|
hexmask.long 0x4 2.--31. 1. "NU16,Reserved"
|
|
bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1"
|
|
line.long 0x8 "AGGR_STATUS_SET,AGGR interrupt status set Register"
|
|
hexmask.long 0x8 4.--31. 1. "NU17,Reserved"
|
|
bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
line.long 0xC "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
|
|
hexmask.long 0xC 4.--31. 1. "NU18,Reserved"
|
|
bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3"
|
|
tree.end
|
|
tree "MSS_MCRC"
|
|
base ad:0xC5020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
|
|
rbitfld.long 0x0 31. "NU12,Reserved" "0,1"
|
|
rbitfld.long 0x0 30. "NU11,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 29. "NU10,Reserved" "0,1"
|
|
rbitfld.long 0x0 27.--28. "NU9,Reserved" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x0 25.--26. "NU8,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x0 24. "NU7,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 23. "NU6,Reserved" "0,1"
|
|
rbitfld.long 0x0 22. "NU5,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 21. "NU4,Reserved" "0,1"
|
|
rbitfld.long 0x0 19.--20. "NU3,Reserved" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x0 17.--18. "NU2,Reserved" "0,1,2,3"
|
|
rbitfld.long 0x0 16. "NU1,Reserved" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
|
|
bitfld.long 0x0 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
|
|
bitfld.long 0x0 11.--12. "CH2_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]} 000 - CRC-64 001 - CRC-16 010 - CRC-32 100 - VDA CAN SAE-J1850 CRC-8 101 - H2F Autosar 4.0 110 - CASTAGNOLI iSCSI 111 / 011 - E2E Profile 4" "?,1: CRC-16 010 - CRC-32 100,?,?"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "CH2_DW_SEL,CRC Data Size select. 000 - 64 bit Data Size 001 - 16 bit Data Size 010 - 32 Bit Data Size" "0,1,2,3"
|
|
bitfld.long 0x0 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a '0'. 0 = PSA Signature Register.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
|
|
newline
|
|
bitfld.long 0x0 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
|
|
bitfld.long 0x0 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
|
|
bitfld.long 0x0 3.--4. "CH1_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]} 000 - CRC-64 001 - CRC-16 010 - CRC-32 100 - VDA CAN SAE-J1850 CRC-8 101 - H2F Autosar 4.0 110 - CASTAGNOLI iSCSI 111 / 011 - E2E Profile 4" "?,1: CRC-16 010 - CRC-32 100,?,?"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "CH1_DW_SEL,CRC Data Size select. 000 - 64 bit Data Size 001 - 16 bit Data Size 010 - 32 Bit Data Size" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset. When set the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore CPU is required to clear this bit by writing a '0'. 0 = PSA Signature Register.." "0: PSA Signature Register not reset,1: PSA Signature Register reset"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CRC_CTRL1,Contains power down control bit"
|
|
hexmask.long 0x0 1.--31. 1. "Reserved1,Reserved"
|
|
bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode 1 = MCRC is in power down mode" "0: MCRC is not in power down mode,1: MCRC is in power down mode"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
|
|
hexmask.long.byte 0x0 26.--31. 1. "Reserved5,Reserved"
|
|
rbitfld.long 0x0 24.--25. "NU14,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 18.--23. 1. "Reserved4,Reserved"
|
|
rbitfld.long 0x0 16.--17. "NU13,Reserved" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--15. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode: 0 0 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: reserved 1,1: Full-CPU mode,?,?"
|
|
newline
|
|
rbitfld.long 0x0 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable. When set the channel is put into data trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When.." "0: Data Trace disable,1: Data Trace enable"
|
|
newline
|
|
rbitfld.long 0x0 2.--3. "Reserved1,Reserved" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode: 0 0 = Data Capture mode. In this mode the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This.." "0: reserved 1,1: Full-CPU mode,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CRC_INTS,Write one to a bit to enable a interrupt"
|
|
rbitfld.long 0x0 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 28. "NU22,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 27. "NU21,Reserved" "0,1"
|
|
rbitfld.long 0x0 26. "NU20,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 25. "NU19,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 21.--24. 1. "Reserved4,Reserved"
|
|
newline
|
|
rbitfld.long 0x0 20. "NU18,Reserved" "0,1"
|
|
rbitfld.long 0x0 19. "NU17,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "NU16,Reserved" "0,1"
|
|
rbitfld.long 0x0 17. "NU15,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 13.--16. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
|
|
bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
|
|
hexmask.long.byte 0x0 5.--8. 1. "Reserved2,Reserved"
|
|
newline
|
|
bitfld.long 0x0 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt enable"
|
|
bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun.." "0: Has no effect,1: Underrun Interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt enable"
|
|
bitfld.long 0x0 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail.." "0: Has no effect,1: CRC Fail Interrupt enable"
|
|
newline
|
|
rbitfld.long 0x0 0. "Reserved1,Reserved" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CRC_INTR,Write one to a bit to disable a interrupt"
|
|
rbitfld.long 0x0 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 28. "NU30,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 27. "NU29,Reserved" "0,1"
|
|
rbitfld.long 0x0 26. "NU28,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 25. "NU27,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 21.--24. 1. "Reserved4,Reserved"
|
|
newline
|
|
rbitfld.long 0x0 20. "NU26,Reserved" "0,1"
|
|
rbitfld.long 0x0 19. "NU25,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "NU24,Reserved" "0,1"
|
|
rbitfld.long 0x0 17. "NU23,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 13.--16. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt disable"
|
|
newline
|
|
bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 =.." "0: Has no effect,1: Underrun Interrupt disable"
|
|
bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt disable"
|
|
newline
|
|
bitfld.long 0x0 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt disable"
|
|
hexmask.long.byte 0x0 5.--8. 1. "Reserved2,Reserved"
|
|
newline
|
|
bitfld.long 0x0 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout.." "0: Has no effect,1: Timeout Interrupt disable"
|
|
bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 =.." "0: Has no effect,1: Underrun Interrupt disable"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun.." "0: Has no effect,1: Overrun Interrupt disable"
|
|
bitfld.long 0x0 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC.." "0: Has no effect,1: CRC Fail Interrupt disable"
|
|
newline
|
|
rbitfld.long 0x0 0. "Reserved1,Reserved" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
|
|
rbitfld.long 0x0 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 28. "NU38,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 27. "NU37,Reserved" "0,1"
|
|
rbitfld.long 0x0 26. "NU36,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 25. "NU35,Reserved" "0,1"
|
|
hexmask.long.byte 0x0 21.--24. 1. "Reserved4,Reserved"
|
|
newline
|
|
rbitfld.long 0x0 20. "NU34,Reserved" "0,1"
|
|
rbitfld.long 0x0 19. "NU33,Reserved" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "NU32,Reserved" "0,1"
|
|
rbitfld.long 0x0 17. "NU31,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 13.--16. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
|
|
newline
|
|
bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
|
|
bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
|
|
newline
|
|
bitfld.long 0x0 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
|
|
hexmask.long.byte 0x0 5.--8. 1. "Reserved2,Reserved"
|
|
newline
|
|
bitfld.long 0x0 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active" "0: No timeout interrupt is active,1: Timeout interrupt is active"
|
|
bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active" "0: No underrun interrupt is active,1: Underrun interrupt is active"
|
|
newline
|
|
bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active" "0: No overrun interrupt is active,1: Overrun interrupt is active"
|
|
bitfld.long 0x0 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. Writing '0' has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active,1: CRC compare fail interrupt is active"
|
|
newline
|
|
rbitfld.long 0x0 0. "Reserved1,Reserved" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OFSTREG,CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register auto- matically clear the respective interrupt flag. Please reference Table 1-3. for details."
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "CRC_BUSY,Contains the busy flag for each channel"
|
|
hexmask.long.byte 0x0 25.--31. 1. "Reserved4,Reserved"
|
|
bitfld.long 0x0 24. "NU40,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--23. 1. "Reserved3,Reserved"
|
|
bitfld.long 0x0 16. "NU39,Reserved" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 9.--15. 1. "Reserved2,Reserved"
|
|
bitfld.long 0x0 8. "Ch2_BUSY,Ch2_BUSY. During AUTO mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 1.--7. 1. "Reserved1,Reserved"
|
|
bitfld.long 0x0 0. "CH1_BUSY,CH1_BUSY. During AUTO mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is.." "0,1"
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
|
|
hexmask.long.word 0x0 20.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."
|
|
line.long 0x4 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
|
|
hexmask.long.word 0x4 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."
|
|
line.long 0x8 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
|
|
hexmask.long.word 0x8 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.."
|
|
line.long 0xC "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
|
|
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "PSA_SIGREGL1,Channel 1 PSA signature low register"
|
|
hexmask.long 0x0 0.--31. 1. "PSASIG1_31_0,Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register."
|
|
line.long 0x4 "PSA_SIGREGH1,Channel 1 PSA signature high register"
|
|
hexmask.long 0x4 0.--31. 1. "PSA_SIG1_63_32,Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register."
|
|
line.long 0x8 "CRC_REGL1,Channel 1 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "CRC1_31_0,Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] regis- ter."
|
|
line.long 0xC "CRC_REGH1,Channel 1 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "CRC1_63_32,Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] regis- ter."
|
|
rgroup.long 0x70++0xF
|
|
line.long 0x0 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
|
|
hexmask.long 0x0 0.--31. 1. "PSASECSIG1_31_0,Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register."
|
|
line.long 0x4 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
|
|
hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register."
|
|
line.long 0x8 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
|
|
hexmask.long 0x8 0.--31. 1. "RAW_DATA1_31_0,Channel 1 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."
|
|
line.long 0xC "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
|
|
hexmask.long 0xC 0.--31. 1. "RAW_DATA1_63_32,Channel 1 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."
|
|
group.long 0x80++0x13
|
|
line.long 0x0 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
|
|
hexmask.long.word 0x0 20.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed."
|
|
line.long 0x4 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
|
|
hexmask.long.word 0x4 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory."
|
|
line.long 0x8 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
|
|
hexmask.long.word 0x8 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails the erroneous sector number.."
|
|
line.long 0xC "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0xC 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."
|
|
line.long 0x10 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated."
|
|
group.long 0xA0++0xF
|
|
line.long 0x0 "PSA_SIGREGL2,Channel 2 PSA signature low register"
|
|
hexmask.long 0x0 0.--31. 1. "PSASIG2_31_0,Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register."
|
|
line.long 0x4 "PSA_SIGREGH2,Channel 2 PSA signature high register"
|
|
hexmask.long 0x4 0.--31. 1. "PSA_SIG2_63_32,Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register."
|
|
line.long 0x8 "CRC_REGL2,Channel 2 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "CRC2_31_0,Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] regis- ter."
|
|
line.long 0xC "CRC_REGH2,Channel 2 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] regis- ter."
|
|
rgroup.long 0xB0++0x23
|
|
line.long 0x0 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
|
|
hexmask.long 0x0 0.--31. 1. "PSASECSIG2_31_0,Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register."
|
|
line.long 0x4 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
|
|
hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register."
|
|
line.long 0x8 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
|
|
hexmask.long 0x8 0.--31. 1. "RAW_DATA2_31_0,Channel 2 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data."
|
|
line.long 0xC "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
|
|
hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data."
|
|
line.long 0x10 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
|
|
hexmask.long.word 0x10 20.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x10 0.--19. 1. "NU41,Reserved"
|
|
line.long 0x14 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
|
|
hexmask.long.word 0x14 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x14 0.--15. 1. "NU42,Reserved"
|
|
line.long 0x18 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
|
|
hexmask.long.word 0x18 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x18 0.--15. 1. "NU43,Reserved"
|
|
line.long 0x1C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "NU44,Reserved"
|
|
line.long 0x20 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x20 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "NU45,Reserved"
|
|
rgroup.long 0xE0++0x33
|
|
line.long 0x0 "PSA_SIGREGL3,Channel 3 PSA signature low register"
|
|
hexmask.long 0x0 0.--31. 1. "NU46,Reserved"
|
|
line.long 0x4 "PSA_SIGREGH3,Channel 3 PSA signature high register"
|
|
hexmask.long 0x4 0.--31. 1. "NU47,Reserved"
|
|
line.long 0x8 "CRC_REGL3,Channel 3 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "NU48,Reserved"
|
|
line.long 0xC "CRC_REGH3,Channel 3 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "NU49,Reserved"
|
|
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
|
|
hexmask.long 0x10 0.--31. 1. "NU50,Reserved"
|
|
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
|
|
hexmask.long 0x14 0.--31. 1. "NU51,Reserved"
|
|
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
|
|
hexmask.long 0x18 0.--31. 1. "NU52,Reserved"
|
|
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NU53,Reserved"
|
|
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
|
|
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
|
|
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
|
|
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
|
|
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
|
|
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
|
|
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
|
|
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
|
|
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
|
|
rgroup.long 0x120++0x1F
|
|
line.long 0x0 "PSA_SIGREGL4,Channel 4 PSA signature low register"
|
|
hexmask.long 0x0 0.--31. 1. "NU59,Reserved"
|
|
line.long 0x4 "PSA_SIGREGH4,Channel 4 PSA signature high register"
|
|
hexmask.long 0x4 0.--31. 1. "NU60,Reserved"
|
|
line.long 0x8 "CRC_REGL4,Channel 4 CRC value low register"
|
|
hexmask.long 0x8 0.--31. 1. "NU61,Reserved"
|
|
line.long 0xC "CRC_REGH4,Channel 4 CRC value high register"
|
|
hexmask.long 0xC 0.--31. 1. "NU62,Reserved"
|
|
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
|
|
hexmask.long 0x10 0.--31. 1. "NU63,Reserved"
|
|
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
|
|
hexmask.long 0x14 0.--31. 1. "NU64,Reserved"
|
|
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
|
|
hexmask.long 0x18 0.--31. 1. "NU65,Reserved"
|
|
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NU66,Reserved"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
|
|
hexmask.long 0x0 3.--31. 1. "NU67,Reserved"
|
|
bitfld.long 0x0 2. "MEn,MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "DTCMEn,DTCMEn. Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0: Tracing of DTCM_ODD and DTCM_EVEN buses have..,1: Tracing of DTCM_ODD and DTCM_EVEN buses have.."
|
|
bitfld.long 0x0 0. "ITCMEn,ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled" "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled"
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x0 "MCRC_RESERVED,0x144 to 0x1FF is reserved area."
|
|
hexmask.long 0x0 0.--31. 1. "NU68,0x144 to 0x1FF is reserved area."
|
|
tree.end
|
|
repeat 2. (list 0x1 0x2)(list ad:0x2F78000 ad:0x3F78000)
|
|
tree "MSS_PCR$1"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
|
|
bitfld.long 0x0 31. "PCS31_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 30. "PCS30_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 29. "PCS29_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 28. "PCS28_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 27. "PCS27_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 26. "PCS26_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
|
|
newline
|
|
bitfld.long 0x0 25. "PCS25_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 24. "PCS24_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 23. "PCS23_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 22. "PCS22_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 21. "PCS21_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 20. "PCS20_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 19. "PCS19_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 18. "PCS18_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 17. "PCS17_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 16. "PCS16_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 15. "PCS15_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 14. "PCS14_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 13. "PCS13_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 12. "PCS12_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 11. "PCS11_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 10. "PCS10_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 9. "PCS9_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 8. "PCS8_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 7. "PCS7_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 6. "PCS6_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 5. "PCS5_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 4. "PCS4_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 3. "PCS3_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 2. "PCS2_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 1. "PCS1_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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newline
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bitfld.long 0x0 0. "PCS0_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect Only those bits which have a slave..,1: Sets the corresponding bit in PMPROTSET0 and.."
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line.long 0x4 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
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bitfld.long 0x4 31. "PCS63_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 30. "PCS62_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 29. "PCS61_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 28. "PCS60_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 27. "PCS59_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 26. "PCS58_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 25. "PCS57_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 24. "PCS56_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 23. "PCS55_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 22. "PCS54_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 21. "PCS53_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 20. "PCS52_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 19. "PCS51_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 18. "PCS50_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 17. "PCS49_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 16. "PCS48_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 15. "PCS47_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 14. "PCS46_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 13. "PCS45_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 12. "PCS44_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 11. "PCS43_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 10. "PCS42_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 9. "PCS41_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 8. "PCS40_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 7. "PCS39_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 6. "PCS38_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 5. "PCS37_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 4. "PCS36_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 3. "PCS35_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 2. "PCS34_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 1. "PCS33_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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newline
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bitfld.long 0x4 0. "PCS32_PROT_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Sets the corresponding bit in PMPROTSET1 and.."
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group.long ($2+0x10)++0x7
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line.long 0x0 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
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bitfld.long 0x0 31. "PCS31_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 30. "PCS30_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 29. "PCS29_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 28. "PCS28_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 27. "PCS27_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 26. "PCS26_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 25. "PCS25_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 24. "PCS24_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 23. "PCS23_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 22. "PCS22_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 21. "PCS21_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 20. "PCS20_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 19. "PCS19_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 18. "PCS18_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 17. "PCS17_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 16. "PCS16_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 15. "PCS15_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 14. "PCS14_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 13. "PCS13_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 12. "PCS12_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 11. "PCS11_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 10. "PCS10_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 9. "PCS9_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 8. "PCS8_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 7. "PCS7_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 6. "PCS6_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 5. "PCS5_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 4. "PCS4_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 3. "PCS3_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 2. "PCS2_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 1. "PCS1_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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newline
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bitfld.long 0x0 0. "PCS0_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written to.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR0 and.."
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line.long 0x4 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
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bitfld.long 0x4 31. "PCS63_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 30. "PCS62_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 29. "PCS61_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 28. "PCS60_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 27. "PCS59_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 26. "PCS58_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 25. "PCS57_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 24. "PCS56_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 23. "PCS55_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 22. "PCS54_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 21. "PCS53_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 20. "PCS52_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 19. "PCS51_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 18. "PCS50_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 17. "PCS49_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 16. "PCS48_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 15. "PCS47_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 14. "PCS46_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 13. "PCS45_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 12. "PCS44_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 11. "PCS43_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 10. "PCS42_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 9. "PCS41_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 8. "PCS40_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 7. "PCS39_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 6. "PCS38_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 5. "PCS37_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 4. "PCS36_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 3. "PCS35_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 2. "PCS34_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 1. "PCS33_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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newline
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bitfld.long 0x4 0. "PCS32_PROT_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory frame can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory frame can be written.." "0: Has no effect,1: Clears the corresponding bit in PMPROTCLR1 and.."
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group.long ($2+0x20)++0xF
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line.long 0x0 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET0 and.."
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line.long 0x4 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET1 and.."
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line.long 0x8 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET2 and.."
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line.long 0xC "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Sets the corresponding bit in PPROTSET3 and.."
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group.long ($2+0x40)++0xF
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line.long 0x0 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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newline
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bitfld.long 0x0 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET0 and.."
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line.long 0x4 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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newline
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bitfld.long 0x4 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET1 and.."
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line.long 0x8 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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newline
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bitfld.long 0x8 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET2 and.."
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line.long 0xC "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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newline
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bitfld.long 0xC 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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bitfld.long 0xC 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes. 1 = The quadrant 'm' of the peripheral frame 'n' can be written to only in privileged mode but can be read in both user and privileged modes. 0 = The corresponding peripheral memory.." "0: Has no effect,1: Clears the corresponding bit in PPROTSET3 and.."
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group.long ($2+0x60)++0x7
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line.long 0x0 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
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bitfld.long 0x0 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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bitfld.long 0x0 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET0 and.."
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line.long 0x4 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
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bitfld.long 0x4 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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bitfld.long 0x4 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Sets the.." "0: Has no effect,1: Sets the corresponding bit in PCSPWRDWNSET1 and.."
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group.long ($2+0x70)++0x7
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line.long 0x0 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
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bitfld.long 0x0 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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bitfld.long 0x0 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET0.."
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line.long 0x4 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
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bitfld.long 0x4 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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bitfld.long 0x4 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes 1 = The corresponding peripheral memory clock needs to be powered down. 0 = The corresponding peripheral memory clock is not to be powered down. Writable only in privileged mode 1 = Clears the.." "0: Has no effect,1: Clears the corresponding bit in PCSPWRDWNSET1.."
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group.long ($2+0x80)++0xF
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line.long 0x0 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET0 and.."
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line.long 0x4 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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bitfld.long 0x4 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET1 and.."
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line.long 0x8 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET2 and.."
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line.long 0xC "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Sets the corresponding bit in PSPWRDWNSET3 and.."
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group.long ($2+0xA0)++0xF
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line.long 0x0 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
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bitfld.long 0x0 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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bitfld.long 0x0 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET0 and.."
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line.long 0x4 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
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bitfld.long 0x4 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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bitfld.long 0x4 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNCLR1 and.."
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line.long 0x8 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
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bitfld.long 0x8 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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bitfld.long 0x8 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET2 and.."
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line.long 0xC "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
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bitfld.long 0xC 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
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bitfld.long 0xC 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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bitfld.long 0xC 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the peripheral starting at quadrant 'm' of the peripheral frame 'n' needs to be powered down. 0 = The clock to the peripheral starting at quadrant 'm' of the.." "0: Has no effect,1: Clears the corresponding bit in PSPWRDWNSET3 and.."
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group.long ($2+0xC0)++0x7
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line.long 0x0 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
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hexmask.long 0x0 1.--31. 1. "Reserved,Reserved"
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bitfld.long 0x0 0. "PD_PWRDWN_SET,Readable in both user and privileged modes. 1 = Clock to the debug frame needs to be powered down. 0 = Clock to the debug frame needs to be powered up. Writable only in privileged mode 1 = Bit 0 when written 1 will get set in both.." "0: Has no effect,1: Bit 0 when written 1"
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line.long 0x4 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
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hexmask.long 0x4 1.--31. 1. "Reserved,Reserved"
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bitfld.long 0x4 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes. 1 = The clock to the debug frame needs to be powered down. 0 = The clock to the debug frame needs to be powered up. Writable only in privileged mode 1 = Bit 0 when written 1 will get cleared in.." "0: Has no effect,1: Bit 0 when written 1"
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group.long ($2+0x200)++0xB
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line.long 0x0 "MSTIDWRENA,MasterID Protection Write Enable Register"
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hexmask.long 0x0 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x0 0.--3. 1. "MSTIDREG_WRENA,Readable in both user and privileged modes. 1010 = All master-id registers are unlocked and available for write. others = Writes to all master-id registers are locked. Writable only in privileged mode 1010 = Writes to master-id registers.."
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line.long 0x4 "MSTIDENA,MasterID Protection Enable Register"
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hexmask.long 0x4 4.--31. 1. "Reserved,Reserved"
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hexmask.long.byte 0x4 0.--3. 1. "MSTID_CHK_EN,Readable in both user and privileged modes. Writable only in privileged mode 1010 = Enable the master-id feature check. others = Master-id check is disabled."
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line.long 0x8 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
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hexmask.long.tbyte 0x8 12.--31. 1. "Reserved2,Reserved"
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hexmask.long.byte 0x8 8.--11. 1. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode. Any error in compare logic is indicated through AERROR output from PCR. Readable in both.."
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hexmask.long.byte 0x8 4.--7. 1. "Reserved1,Reserved"
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hexmask.long.byte 0x8 0.--3. 1. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic. Readable in both user and privileged modes. Writable only in privileged mode 1010 = Master-id compare diagnostic mode is.."
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group.long ($2+0x300)++0x2E3
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line.long 0x0 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
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hexmask.long.word 0x0 16.--31. 1. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x0 0.--15. 1. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x4 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
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hexmask.long.word 0x4 16.--31. 1. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x4 0.--15. 1. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x8 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
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hexmask.long.word 0x8 16.--31. 1. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x8 0.--15. 1. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0xC "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
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hexmask.long.word 0xC 16.--31. 1. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0xC 0.--15. 1. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
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hexmask.long.word 0x10 16.--31. 1. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x10 0.--15. 1. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
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hexmask.long.word 0x14 16.--31. 1. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x14 0.--15. 1. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
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hexmask.long.word 0x18 16.--31. 1. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x18 0.--15. 1. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
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hexmask.long.word 0x1C 16.--31. 1. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x1C 0.--15. 1. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
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hexmask.long.word 0x20 16.--31. 1. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x20 0.--15. 1. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
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hexmask.long.word 0x24 16.--31. 1. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x24 0.--15. 1. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
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hexmask.long.word 0x28 16.--31. 1. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x28 0.--15. 1. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
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hexmask.long.word 0x2C 16.--31. 1. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x2C 0.--15. 1. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
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hexmask.long.word 0x30 16.--31. 1. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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hexmask.long.word 0x30 0.--15. 1. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
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hexmask.long.word 0x34 16.--31. 1. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x34 0.--15. 1. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
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hexmask.long.word 0x38 16.--31. 1. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x38 0.--15. 1. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
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hexmask.long.word 0x3C 16.--31. 1. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x3C 0.--15. 1. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
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hexmask.long.word 0x40 16.--31. 1. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x40 0.--15. 1. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
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hexmask.long.word 0x44 16.--31. 1. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x44 0.--15. 1. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
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hexmask.long.word 0x48 16.--31. 1. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x48 0.--15. 1. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
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hexmask.long.word 0x4C 16.--31. 1. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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newline
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hexmask.long.word 0x4C 0.--15. 1. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If bits.."
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line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
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hexmask.long.word 0x50 16.--31. 1. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x50 0.--15. 1. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
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hexmask.long.word 0x54 16.--31. 1. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x54 0.--15. 1. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
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hexmask.long.word 0x58 16.--31. 1. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x58 0.--15. 1. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
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hexmask.long.word 0x5C 16.--31. 1. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x5C 0.--15. 1. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
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hexmask.long.word 0x60 16.--31. 1. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x60 0.--15. 1. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
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hexmask.long.word 0x64 16.--31. 1. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x64 0.--15. 1. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
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hexmask.long.word 0x68 16.--31. 1. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x68 0.--15. 1. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
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hexmask.long.word 0x6C 16.--31. 1. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x6C 0.--15. 1. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
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hexmask.long.word 0x70 16.--31. 1. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x70 0.--15. 1. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
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hexmask.long.word 0x74 16.--31. 1. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x74 0.--15. 1. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
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hexmask.long.word 0x78 16.--31. 1. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x78 0.--15. 1. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
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hexmask.long.word 0x7C 16.--31. 1. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x7C 0.--15. 1. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
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hexmask.long.word 0x80 16.--31. 1. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x80 0.--15. 1. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
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hexmask.long.word 0x84 16.--31. 1. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x84 0.--15. 1. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
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hexmask.long.word 0x88 16.--31. 1. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x88 0.--15. 1. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
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hexmask.long.word 0x8C 16.--31. 1. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x8C 0.--15. 1. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
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hexmask.long.word 0x90 16.--31. 1. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x90 0.--15. 1. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
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hexmask.long.word 0x94 16.--31. 1. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x94 0.--15. 1. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
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hexmask.long.word 0x98 16.--31. 1. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x98 0.--15. 1. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
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hexmask.long.word 0x9C 16.--31. 1. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0x9C 0.--15. 1. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
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hexmask.long.word 0xA0 16.--31. 1. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xA0 0.--15. 1. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
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hexmask.long.word 0xA4 16.--31. 1. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xA4 0.--15. 1. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
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hexmask.long.word 0xA8 16.--31. 1. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xA8 0.--15. 1. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
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hexmask.long.word 0xAC 16.--31. 1. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xAC 0.--15. 1. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
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hexmask.long.word 0xB0 16.--31. 1. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xB0 0.--15. 1. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
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hexmask.long.word 0xB4 16.--31. 1. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xB4 0.--15. 1. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
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hexmask.long.word 0xB8 16.--31. 1. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xB8 0.--15. 1. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
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hexmask.long.word 0xBC 16.--31. 1. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xBC 0.--15. 1. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
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hexmask.long.word 0xC0 16.--31. 1. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xC0 0.--15. 1. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
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hexmask.long.word 0xC4 16.--31. 1. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xC4 0.--15. 1. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
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hexmask.long.word 0xC8 16.--31. 1. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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newline
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hexmask.long.word 0xC8 0.--15. 1. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
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hexmask.long.word 0xCC 16.--31. 1. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xCC 0.--15. 1. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
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hexmask.long.word 0xD0 16.--31. 1. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xD0 0.--15. 1. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
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hexmask.long.word 0xD4 16.--31. 1. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xD4 0.--15. 1. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
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hexmask.long.word 0xD8 16.--31. 1. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xD8 0.--15. 1. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
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hexmask.long.word 0xDC 16.--31. 1. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xDC 0.--15. 1. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
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hexmask.long.word 0xE0 16.--31. 1. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xE0 0.--15. 1. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
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hexmask.long.word 0xE4 16.--31. 1. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xE4 0.--15. 1. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
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hexmask.long.word 0xE8 16.--31. 1. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xE8 0.--15. 1. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
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hexmask.long.word 0xEC 16.--31. 1. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xEC 0.--15. 1. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
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hexmask.long.word 0xF0 16.--31. 1. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xF0 0.--15. 1. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
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hexmask.long.word 0xF4 16.--31. 1. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xF4 0.--15. 1. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
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hexmask.long.word 0xF8 16.--31. 1. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xF8 0.--15. 1. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
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hexmask.long.word 0xFC 16.--31. 1. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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hexmask.long.word 0xFC 0.--15. 1. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame. These bits sets the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The following examples shows the usage of these register bits. (a) If.."
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line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
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hexmask.long.word 0x100 16.--31. 1. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x100 0.--15. 1. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
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hexmask.long.word 0x104 16.--31. 1. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x104 0.--15. 1. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
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hexmask.long.word 0x108 16.--31. 1. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x108 0.--15. 1. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
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hexmask.long.word 0x10C 16.--31. 1. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x10C 0.--15. 1. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
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hexmask.long.word 0x110 16.--31. 1. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x110 0.--15. 1. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
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hexmask.long.word 0x114 16.--31. 1. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x114 0.--15. 1. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
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hexmask.long.word 0x118 16.--31. 1. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x118 0.--15. 1. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
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hexmask.long.word 0x11C 16.--31. 1. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x11C 0.--15. 1. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
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hexmask.long.word 0x120 16.--31. 1. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x120 0.--15. 1. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
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hexmask.long.word 0x124 16.--31. 1. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x124 0.--15. 1. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
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hexmask.long.word 0x128 16.--31. 1. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x128 0.--15. 1. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
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hexmask.long.word 0x12C 16.--31. 1. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x12C 0.--15. 1. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
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hexmask.long.word 0x130 16.--31. 1. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x130 0.--15. 1. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
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hexmask.long.word 0x134 16.--31. 1. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x134 0.--15. 1. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
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hexmask.long.word 0x138 16.--31. 1. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x138 0.--15. 1. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
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hexmask.long.word 0x13C 16.--31. 1. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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hexmask.long.word 0x13C 0.--15. 1. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in.."
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line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
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hexmask.long.word 0x140 16.--31. 1. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x140 0.--15. 1. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
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hexmask.long.word 0x144 16.--31. 1. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x144 0.--15. 1. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
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hexmask.long.word 0x148 16.--31. 1. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x148 0.--15. 1. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
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hexmask.long.word 0x14C 16.--31. 1. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x14C 0.--15. 1. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
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hexmask.long.word 0x150 16.--31. 1. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x150 0.--15. 1. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
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hexmask.long.word 0x154 16.--31. 1. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x154 0.--15. 1. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
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hexmask.long.word 0x158 16.--31. 1. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x158 0.--15. 1. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
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hexmask.long.word 0x15C 16.--31. 1. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x15C 0.--15. 1. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
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hexmask.long.word 0x160 16.--31. 1. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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hexmask.long.word 0x160 0.--15. 1. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
|
|
hexmask.long.word 0x164 16.--31. 1. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x164 0.--15. 1. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
|
|
hexmask.long.word 0x168 16.--31. 1. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x168 0.--15. 1. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
|
|
hexmask.long.word 0x16C 16.--31. 1. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x16C 0.--15. 1. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
|
|
hexmask.long.word 0x170 16.--31. 1. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x170 0.--15. 1. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
|
|
hexmask.long.word 0x174 16.--31. 1. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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|
hexmask.long.word 0x174 0.--15. 1. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
|
|
hexmask.long.word 0x178 16.--31. 1. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x178 0.--15. 1. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
|
|
hexmask.long.word 0x17C 16.--31. 1. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x17C 0.--15. 1. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
|
|
hexmask.long.word 0x180 16.--31. 1. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x180 0.--15. 1. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
|
|
hexmask.long.word 0x184 16.--31. 1. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x184 0.--15. 1. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
|
|
hexmask.long.word 0x188 16.--31. 1. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
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|
hexmask.long.word 0x188 0.--15. 1. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
|
|
hexmask.long.word 0x18C 16.--31. 1. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x18C 0.--15. 1. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
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|
hexmask.long.word 0x190 16.--31. 1. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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|
hexmask.long.word 0x190 0.--15. 1. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
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|
hexmask.long.word 0x194 16.--31. 1. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x194 0.--15. 1. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
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|
hexmask.long.word 0x198 16.--31. 1. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x198 0.--15. 1. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
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hexmask.long.word 0x19C 16.--31. 1. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x19C 0.--15. 1. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
|
|
hexmask.long.word 0x1A0 16.--31. 1. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
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hexmask.long.word 0x1A0 0.--15. 1. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
|
|
hexmask.long.word 0x1A4 16.--31. 1. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
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hexmask.long.word 0x1A4 0.--15. 1. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
|
|
hexmask.long.word 0x1A8 16.--31. 1. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x1A8 0.--15. 1. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
|
|
hexmask.long.word 0x1AC 16.--31. 1. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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|
newline
|
|
hexmask.long.word 0x1AC 0.--15. 1. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
|
|
hexmask.long.word 0x1B0 16.--31. 1. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1B0 0.--15. 1. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
|
|
hexmask.long.word 0x1B4 16.--31. 1. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1B4 0.--15. 1. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
|
|
hexmask.long.word 0x1B8 16.--31. 1. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1B8 0.--15. 1. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
|
|
hexmask.long.word 0x1BC 16.--31. 1. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1BC 0.--15. 1. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
|
|
hexmask.long.word 0x1C0 16.--31. 1. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1C0 0.--15. 1. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
|
|
hexmask.long.word 0x1C4 16.--31. 1. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1C4 0.--15. 1. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
|
|
hexmask.long.word 0x1C8 16.--31. 1. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1C8 0.--15. 1. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
|
|
hexmask.long.word 0x1CC 16.--31. 1. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1CC 0.--15. 1. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
|
|
hexmask.long.word 0x1D0 16.--31. 1. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1D0 0.--15. 1. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
|
|
hexmask.long.word 0x1D4 16.--31. 1. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1D4 0.--15. 1. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
|
|
hexmask.long.word 0x1D8 16.--31. 1. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1D8 0.--15. 1. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
|
|
hexmask.long.word 0x1DC 16.--31. 1. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1DC 0.--15. 1. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
|
|
hexmask.long.word 0x1E0 16.--31. 1. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1E0 0.--15. 1. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
|
|
hexmask.long.word 0x1E4 16.--31. 1. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1E4 0.--15. 1. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
|
|
hexmask.long.word 0x1E8 16.--31. 1. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1E8 0.--15. 1. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
|
|
hexmask.long.word 0x1EC 16.--31. 1. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1EC 0.--15. 1. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
|
|
hexmask.long.word 0x1F0 16.--31. 1. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
newline
|
|
hexmask.long.word 0x1F0 0.--15. 1. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
|
|
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
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hexmask.long.word 0x1F4 16.--31. 1. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1F4 0.--15. 1. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
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hexmask.long.word 0x1F8 16.--31. 1. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1F8 0.--15. 1. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
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hexmask.long.word 0x1FC 16.--31. 1. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x1FC 0.--15. 1. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
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hexmask.long.word 0x200 16.--31. 1. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x200 0.--15. 1. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
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hexmask.long.word 0x204 16.--31. 1. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x204 0.--15. 1. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
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hexmask.long.word 0x208 16.--31. 1. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x208 0.--15. 1. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
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hexmask.long.word 0x20C 16.--31. 1. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x20C 0.--15. 1. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
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hexmask.long.word 0x210 16.--31. 1. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x210 0.--15. 1. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
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hexmask.long.word 0x214 16.--31. 1. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x214 0.--15. 1. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
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hexmask.long.word 0x218 16.--31. 1. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x218 0.--15. 1. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
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hexmask.long.word 0x21C 16.--31. 1. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x21C 0.--15. 1. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
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hexmask.long.word 0x220 16.--31. 1. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x220 0.--15. 1. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
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hexmask.long.word 0x224 16.--31. 1. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x224 0.--15. 1. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
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hexmask.long.word 0x228 16.--31. 1. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x228 0.--15. 1. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
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hexmask.long.word 0x22C 16.--31. 1. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x22C 0.--15. 1. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
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hexmask.long.word 0x230 16.--31. 1. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x230 0.--15. 1. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
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hexmask.long.word 0x234 16.--31. 1. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x234 0.--15. 1. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
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hexmask.long.word 0x238 16.--31. 1. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x238 0.--15. 1. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
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hexmask.long.word 0x23C 16.--31. 1. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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newline
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hexmask.long.word 0x23C 0.--15. 1. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID in section.."
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line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
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hexmask.long.word 0x240 16.--31. 1. "PCS1MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x240 0.--15. 1. "PCS0MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
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hexmask.long.word 0x244 16.--31. 1. "PCS3MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x244 0.--15. 1. "PCS2MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
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hexmask.long.word 0x248 16.--31. 1. "PCS5MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x248 0.--15. 1. "PCS4MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
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hexmask.long.word 0x24C 16.--31. 1. "PCS7MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x24C 0.--15. 1. "PCS6MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
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hexmask.long.word 0x250 16.--31. 1. "PCS9MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x250 0.--15. 1. "PCS8MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
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hexmask.long.word 0x254 16.--31. 1. "PCS11MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x254 0.--15. 1. "PCS10MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
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hexmask.long.word 0x258 16.--31. 1. "PCS13MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x258 0.--15. 1. "PCS12MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
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hexmask.long.word 0x25C 16.--31. 1. "PCS15MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x25C 0.--15. 1. "PCS14MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
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hexmask.long.word 0x260 16.--31. 1. "PCS17MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x260 0.--15. 1. "PCS16MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
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hexmask.long.word 0x264 16.--31. 1. "PCS19MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x264 0.--15. 1. "PCS18MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
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hexmask.long.word 0x268 16.--31. 1. "PCS21MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x268 0.--15. 1. "PCS20MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
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hexmask.long.word 0x26C 16.--31. 1. "PCS23MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x26C 0.--15. 1. "PCS22MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
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hexmask.long.word 0x270 16.--31. 1. "PCS25MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x270 0.--15. 1. "PCS24MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
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hexmask.long.word 0x274 16.--31. 1. "PCS27MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x274 0.--15. 1. "PCS26MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
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hexmask.long.word 0x278 16.--31. 1. "PCS29MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x278 0.--15. 1. "PCS28MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
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hexmask.long.word 0x27C 16.--31. 1. "PCS31MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x27C 0.--15. 1. "PCS30MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
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hexmask.long.word 0x280 16.--31. 1. "PCS33MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x280 0.--15. 1. "PCS32MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
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hexmask.long.word 0x284 16.--31. 1. "PCS35MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x284 0.--15. 1. "PCS34MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
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hexmask.long.word 0x288 16.--31. 1. "PCS37MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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newline
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hexmask.long.word 0x288 0.--15. 1. "PCS36MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
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hexmask.long.word 0x28C 16.--31. 1. "PCS39MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x28C 0.--15. 1. "PCS38MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
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hexmask.long.word 0x290 16.--31. 1. "PCS41MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x290 0.--15. 1. "PCS40MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
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hexmask.long.word 0x294 16.--31. 1. "PCS43MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x294 0.--15. 1. "PCS42MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
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hexmask.long.word 0x298 16.--31. 1. "PCS45MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x298 0.--15. 1. "PCS44MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
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hexmask.long.word 0x29C 16.--31. 1. "PCS47MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x29C 0.--15. 1. "PCS46MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
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hexmask.long.word 0x2A0 16.--31. 1. "PCS49MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2A0 0.--15. 1. "PCS48MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
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hexmask.long.word 0x2A4 16.--31. 1. "PCS51MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2A4 0.--15. 1. "PCS50MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
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hexmask.long.word 0x2A8 16.--31. 1. "PCS53MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2A8 0.--15. 1. "PCS52MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
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hexmask.long.word 0x2AC 16.--31. 1. "PCS55MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2AC 0.--15. 1. "PCS54MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
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hexmask.long.word 0x2B0 16.--31. 1. "PCS57MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2B0 0.--15. 1. "PCS56MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
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hexmask.long.word 0x2B4 16.--31. 1. "PCS59MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2B4 0.--15. 1. "PCS58MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
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hexmask.long.word 0x2B8 16.--31. 1. "PCS61MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2B8 0.--15. 1. "PCS60MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
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hexmask.long.word 0x2BC 16.--31. 1. "PCS63MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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hexmask.long.word 0x2BC 0.--15. 1. "PCS62MSTID,There are 16 bits for each frame in PCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The following examples shows the usage of these register bits. (a) If bits 15:0 is.."
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line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
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hexmask.long.word 0x2C0 16.--31. 1. "PPCS1MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2C0 0.--15. 1. "PPCS0MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
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hexmask.long.word 0x2C4 16.--31. 1. "PPCS3MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2C4 0.--15. 1. "PPCS2MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
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hexmask.long.word 0x2C8 16.--31. 1. "PPCS5MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2C8 0.--15. 1. "PPCS4MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
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hexmask.long.word 0x2CC 16.--31. 1. "PPCS7MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2CC 0.--15. 1. "PPCS6MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
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hexmask.long.word 0x2D0 16.--31. 1. "PPCS9MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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hexmask.long.word 0x2D0 0.--15. 1. "PPCS8MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both.."
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line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
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hexmask.long.word 0x2D4 16.--31. 1. "PPCS11MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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hexmask.long.word 0x2D4 0.--15. 1. "PPCS10MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
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hexmask.long.word 0x2D8 16.--31. 1. "PPCS13MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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hexmask.long.word 0x2D8 0.--15. 1. "PPCS12MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
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hexmask.long.word 0x2DC 16.--31. 1. "PPCS15MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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hexmask.long.word 0x2DC 0.--15. 1. "PPCS14MSTID,There are 16 bits for each frame in PPCS. These bits sets the permission for maximum of 16 masters to address the memory mapped in each of the frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in.."
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line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
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hexmask.long 0x2E0 0.--31. 1. "PCREXT_MSTID,These bits sets the permission for maximum of 16 masters to address the external PCR frame. The scheme is similar to the one described for PCSm MSTID in section 1.7.33. Readable in both user and privileged modes. 1 = The memory mapped in.."
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tree.end
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repeat.end
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base ad:0x2F78000
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tree "MSS_QSPI"
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base ad:0xC8000000
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rgroup.long 0x0++0x3
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line.long 0x0 "PID,PID"
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bitfld.long 0x0 30.--31. "SCHEME,The scheme of the register used. This indicates the PDR3.5 Method" "0,1,2,3"
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bitfld.long 0x0 28.--29. "Reserved,Always read as 0" "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "FUNC,The function of the module being used"
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hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Release Version The PDR release number of this IP"
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bitfld.long 0x0 8.--10. "MAJOR,Major Release Number" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Custom IP" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Release Number"
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repeat 9. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list 0x0 0x4 0x8 0x10 0x14 0x18 0x30 0x34 0x38)
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "MSS_QSPI_Reserved$1,Reserved"
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hexmask.long 0x0 0.--31. 1. "Reserved_1,Reserved"
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repeat.end
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group.long 0x10++0x3
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line.long 0x0 "SYSCONFIG,SYSCONFIG"
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hexmask.long 0x0 6.--31. 1. "Reserved3,Always read as 0"
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rbitfld.long 0x0 4.--5. "Reserved2,Always read as 0" "0,1,2,3"
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bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle.." "0: Force-idle mode: local target's idle state..,1: No-idle mode: local target never enters idle state,2: Smart-idle mode: local target's idle state..,3: Smart-idle wakeup-capable mode: local target's.."
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rbitfld.long 0x0 0.--1. "Reserved1,Always read as 0" "0,1,2,3"
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group.long 0x20++0x13
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line.long 0x0 "INTR_STATUS_RAW_SET,INTR Interrupt Status Raw/Set Register"
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hexmask.long 0x0 2.--31. 1. "Reserved,Always read as 0"
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bitfld.long 0x0 1. "WIRQ_RAW,Word Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0: inactive,1: active Writing 1 will set status Writing 0 has.."
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bitfld.long 0x0 0. "FIRQ_RAW,Frame Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0: inactive,1: active Writing 1 will set status Writing 0 has.."
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line.long 0x4 "INTR_STATUS_ENABLED_CLEAR,INTR Interrupt Status Enabled/Clear Register"
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hexmask.long 0x4 2.--31. 1. "Reserved,Always read as 0"
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bitfld.long 0x4 1. "WIRQ_ENA,Word Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0: inactive,1: active Writing 1 will clear interrupt Writing 0.."
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bitfld.long 0x4 0. "FIRQ_ENA,Frame Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0: inactive,1: active Writing 1 will clear interrupt Writing 0.."
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line.long 0x8 "INTR_ENABLE_SET,INTR Interrupt Enable/Set Register"
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hexmask.long 0x8 2.--31. 1. "Reserved,Always read as 0"
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bitfld.long 0x8 1. "WIRQ_ENA_SET,Word Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0: disabled,1: enabled Writing 1 will set interrupt enabled.."
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bitfld.long 0x8 0. "FIRQ_ENA_SET,Frame Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0: disabled,1: enabled Writing 1 will set interrupt enabled.."
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line.long 0xC "INTR_ENABLE_CLEAR,INTR Interrupt Enable/Clear Register"
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hexmask.long 0xC 2.--31. 1. "Reserved,Always read as 0"
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bitfld.long 0xC 1. "WIRQ_ENA_CLR,Word Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0: disabled,1: enabled Writing 1 will clear interrupt enabled.."
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bitfld.long 0xC 0. "FIRQ_ENA_CLR,Frame Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0: disabled,1: enabled Writing 1 will clear interrupt enabled.."
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line.long 0x10 "INTC_EOI,EOI Register"
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hexmask.long 0x10 0.--31. 1. "EOI_VECTOR,Number associated with the ipgenericirq for intr output. There are 1 interrupt outputs Write 0x0 : Write to intr IP Generic Any other write value is ignored."
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group.long 0x40++0xB
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line.long 0x0 "SPI_CLOCK_CNTRL,SPI Clock Control Register (SPICC)"
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bitfld.long 0x0 31. "CLKEN,Clock Enable. 0- Data clock is turned off 1- Data clock is enabled" "0: Data clock is turned off 1,?"
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hexmask.long.word 0x0 16.--30. 1. "Reserved,Always read as 0"
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hexmask.long.word 0x0 0.--15. 1. "DCLK_DIV,Serial data clock divide by ratio"
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line.long 0x4 "SPI_DC,SPI Data Control Register (SPIDC)"
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rbitfld.long 0x4 29.--31. "Reserved4,Always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 27.--28. "DD3,Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles.." "0: Data is output on the same cycle as the CS_N..,?,?,?"
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bitfld.long 0x4 26. "CKPH3,Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data.." "0: Data shifted out on falling edge; input on..,1: Data shifted out on falling edge; input on.."
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bitfld.long 0x4 25. "CSP3,Chip select polarity for chip select 3 0- Active low 1- Active high" "0: Active low 1,?"
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bitfld.long 0x4 24. "CKP3,Clock polarity for chip select 3 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0: When data is not being transferred,1: When data is not being transferred"
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rbitfld.long 0x4 21.--23. "Reserved3,Always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 19.--20. "DD2,Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles.." "0: Data is output on the same cycle as the CS_N..,?,?,?"
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bitfld.long 0x4 18. "CKPH2,Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data.." "0: Data shifted out on falling edge; input on..,1: Data shifted out on falling edge; input on.."
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bitfld.long 0x4 17. "CSP2,Chip select polarity for chip select 2 0- Active low 1- Active high" "0: Active low 1,?"
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bitfld.long 0x4 16. "CKP2,Clock polarity for chip select 2 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0: When data is not being transferred,1: When data is not being transferred"
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rbitfld.long 0x4 13.--15. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 11.--12. "DD1,Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles.." "0: Data is output on the same cycle as the CS_N..,?,?,?"
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bitfld.long 0x4 10. "CKPH1,Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data.." "0: Data shifted out on falling edge; input on..,1: Data shifted out on falling edge; input on.."
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bitfld.long 0x4 9. "CSP1,Chip select polarity for chip select 1 0- Active low 1- Active high" "0: Active low 1,?"
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bitfld.long 0x4 8. "CKP1,Clock polarity for chip select 1 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0: When data is not being transferred,1: When data is not being transferred"
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rbitfld.long 0x4 5.--7. "Reserved1,Always read as 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 3.--4. "DD0,Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles.." "0: Data is output on the same cycle as the CS_N..,?,?,?"
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bitfld.long 0x4 2. "CKPH0,Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data.." "0: Data shifted out on falling edge; input on..,1: Data shifted out on falling edge; input on.."
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bitfld.long 0x4 1. "CSP0,Chip select polarity for chip select 0 0- Active low 1- Active high" "0: Active low 1,?"
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bitfld.long 0x4 0. "CKP0,Clock polarity for chip select 0 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0: When data is not being transferred,1: When data is not being transferred"
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line.long 0x8 "SPI_CMD,SPI Command Register (SPICR)"
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rbitfld.long 0x8 30.--31. "Reserved3,Always read as 0" "0,1,2,3"
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bitfld.long 0x8 28.--29. "CSNUM,Device select. Sets the active chip select for the transfer 00- Chip Select 0 active 01- Chip Select 1 active 10- Chip Select 2 active 11- Chip Select 3 active" "0: Chip Select 0 active 01,?,?,?"
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rbitfld.long 0x8 26.--27. "Reserved2,Always read as 0" "0,1,2,3"
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hexmask.long.byte 0x8 19.--25. 1. "WLEN,Word length. Sets the size of the individual transfers from 1 - 128 bits 0- 1 bit 1- 2 bits ... 127 - 128 bits"
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bitfld.long 0x8 16.--18. "CMD,Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 - Reserved 101 - 3 pin Read Single 110 - 3 pin Write Single 111 - 6 pin Read Quad" "0: Reserved 001,?,?,?,?,?,?,?"
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bitfld.long 0x8 15. "FIRQ,Frame count interrupt enable" "0,1"
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bitfld.long 0x8 14. "WIRQ,Word count interrupt enable" "0,1"
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rbitfld.long 0x8 12.--13. "Reserved1,Always read as 0" "0,1,2,3"
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hexmask.long.word 0x8 0.--11. 1. "FLEN,Frame Length 0- 1 word 1- 2 words ... 4095 - 4096 words"
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rgroup.long 0x4C++0x3
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line.long 0x0 "SPI_STATUS,SPI Status Register (SPISR)"
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hexmask.long.byte 0x0 28.--31. 1. "Reserved2,Always read as 0"
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hexmask.long.word 0x0 16.--27. 1. "WDCNT,Word count. This field will reflect the 1-4096 words transferred"
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hexmask.long.word 0x0 3.--15. 1. "Reserved1,Always read as 0"
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bitfld.long 0x0 2. "FC,Frame complete. This bit is set after all of the requested words have been transmitted. 0- Transfer is not complete 1- Transfer is complete This bit is reset when the SPI Status Register is read" "0: Transfer is not complete 1,?"
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bitfld.long 0x0 1. "WC,Word complete. This bit is set after each word transfer is completed. 0- Word transfer is not complete 1- Word transfer is complete This bit is reset when the SPI Status Register is read" "0: Word transfer is not complete 1,?"
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bitfld.long 0x0 0. "BUSY,Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words the bit will clear to signal that it is ok to read/write the data registers. 0- Idle 1- Busy" "0: Idle 1,?"
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group.long 0x50++0x17
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line.long 0x0 "SPI_DATA,SPI Data Register (SPIDR)"
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hexmask.long 0x0 0.--31. 1. "DATA,Data register for read and write operations"
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line.long 0x4 "SPI_SETUP0,Memory Mapped SPI Setup0 Register"
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rbitfld.long 0x4 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0"
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hexmask.long.byte 0x4 16.--23. 1. "WCMD,Write Command"
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rbitfld.long 0x4 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
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bitfld.long 0x4 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad.." "0,1,2,3"
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bitfld.long 0x4 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS,1: use 8 bits;,2: use 16 bits;,3: use 24 bits"
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bitfld.long 0x4 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0,1,2,3"
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hexmask.long.byte 0x4 0.--7. 1. "RCMD,Read Command"
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line.long 0x8 "SPI_SETUP1,Memory Mapped SPI Setup1 Register"
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rbitfld.long 0x8 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0"
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hexmask.long.byte 0x8 16.--23. 1. "WCMD,Write Command"
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rbitfld.long 0x8 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
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bitfld.long 0x8 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad.." "0,1,2,3"
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bitfld.long 0x8 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS,1: use 8 bits;,2: use 16 bits;,3: use 24 bits"
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bitfld.long 0x8 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0,1,2,3"
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hexmask.long.byte 0x8 0.--7. 1. "RCMD,Read Command"
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line.long 0xC "SPI_SETUP2,Memory Mapped SPI Setup2 Register"
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rbitfld.long 0xC 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0xC 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0"
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hexmask.long.byte 0xC 16.--23. 1. "WCMD,Write Command"
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rbitfld.long 0xC 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
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bitfld.long 0xC 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad.." "0,1,2,3"
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bitfld.long 0xC 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS,1: use 8 bits;,2: use 16 bits;,3: use 24 bits"
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bitfld.long 0xC 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0,1,2,3"
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hexmask.long.byte 0xC 0.--7. 1. "RCMD,Read Command"
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line.long 0x10 "SPI_SETUP3,Memory Mapped SPI Setup3 Register"
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rbitfld.long 0x10 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0"
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hexmask.long.byte 0x10 16.--23. 1. "WCMD,Write Command"
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rbitfld.long 0x10 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
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bitfld.long 0x10 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad.." "0,1,2,3"
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bitfld.long 0x10 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS,1: use 8 bits;,2: use 16 bits;,3: use 24 bits"
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bitfld.long 0x10 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0,1,2,3"
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hexmask.long.byte 0x10 0.--7. 1. "RCMD,Read Command"
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line.long 0x14 "SPI_SWITCH,Memory Mapped SPI Switch Register"
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hexmask.long 0x14 2.--31. 1. "Reserved,Always read as 0"
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bitfld.long 0x14 1. "MM_INT_EN,Memory Mapped mode interrupt enable. 0 - Interrupts are disabled during memory mapped operations 1 - Word Count interrupt is enabled for memory mapped operations" "0,1"
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bitfld.long 0x14 0. "MMPT_S,MMPT select. If 0 (default) config port has is selected to control config of core SPI module. If 1 Memory Mapped Protocol Translator is selected to control config port of core SPI module." "0,1"
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repeat 3. (list 0x1 0x2 0x3)(list 0x0 0x4 0x8)
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group.long ($2+0x68)++0x3
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line.long 0x0 "SPI_DATA$1,SPI Data Register (SPIDR1)"
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hexmask.long 0x0 0.--31. 1. "DATA,Data register for read and write operations"
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repeat.end
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tree.end
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tree "MSS_R5SS_STC"
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base ad:0x2F79800
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group.long 0x0++0xB
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line.long 0x0 "STCGCR0,Self test Global control Reg0. *NOT BYTE ACCESSIBLE"
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hexmask.long.word 0x0 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run. The selftest controller sends out 'complete' indication once it runs all of the.."
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hexmask.long.byte 0x0 11.--15. 1. "NU0,Reserved bits"
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bitfld.long 0x0 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock. This value is used to insert that many idle cycles in the Capture phase. Programmable idle cycles allow.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only). *NOT BYTE ACCESSIBLE Idle Cycles between scan_en going high to func_clk_en generation and scan_en going high to misr_log_en generation. This.." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval. This bit.." "0: Continue NSTC run from previous interval,1: Restart NSTC run from ROM address 0 1X = Start..,?,?"
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line.long 0x4 "STCGCR1,Self test Global control Reg1"
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hexmask.long.tbyte 0x4 12.--31. 1. "NU2,Reserved bits"
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hexmask.long.byte 0x4 8.--11. 1. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test 0001 = Select CORE for selftest Other = CORE not selected."
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rbitfld.long 0x4 7. "NU3,Reserved bits" "0,1"
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bitfld.long 0x4 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode. 1 = Spread mode 0 = XOR mode" "0: XOR mode,1: Spread mode"
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bitfld.long 0x4 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration: 1 = Operates in Low Power Scan Mode. 0 = Operates in Normal Scan Mode." "0: Operates in Normal Scan Mode,1: Operates in Low Power Scan Mode"
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newline
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bitfld.long 0x4 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only) 1010 = Self test run enabled All values other than 1010 = Self test run disabled"
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line.long 0x8 "STCTPR,Time out counter preload register"
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hexmask.long 0x8 0.--31. 1. "TO_PRELOAD,Self test time out preload (RWP - Read Priviledge Mode Write only) This register contains the total number of STC clock cycles it will take before a self-test timeout error will be triggered after the initiation of the self-test run. This is.."
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rgroup.long 0xC++0xF
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line.long 0x0 "STC_CADDR,Current Address register for CORE1"
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hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE1 This register reflects the current ROM address (for micro code load) accessed during selftest for CORE1 in of case segment0 and all the remaining segmentsn where n = 1 to 3)."
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line.long 0x4 "STCCICR,Current Interval count register"
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hexmask.long.word 0x4 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well. This field is applicable only for Segment 0."
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hexmask.long.word 0x4 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run."
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line.long 0x8 "STCGSTAT,Global Status Register"
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hexmask.long.tbyte 0x8 12.--31. 1. "NU4,Reserved bits"
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newline
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hexmask.long.byte 0x8 8.--11. 1. "ST_ACTIVE,Tells whether self test is currently active or not. 1010 = Self test is active Others = SelfTest is not active Once the self-test completes and ST_ENA_B4 key is cleared this field will reflect the inactive value."
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hexmask.long.byte 0x8 2.--7. 1. "NU5,Reserved bits"
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bitfld.long 0x8 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode) 0 = Self test run has not failed 1 = SelfTest run has failed. Write Clear." "0: Self test run has not failed,1: SelfTest run has failed"
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bitfld.long 0x8 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode) 0 = Not completed 1 = SelfTest run Completed" "0: Not completed,1: SelfTest run Completed"
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line.long 0xC "STCFSTAT,Fail Status Register"
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hexmask.long 0xC 5.--31. 1. "NU6,Reserved bits"
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newline
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bitfld.long 0xC 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur. 00 = Failure on Segment 0 01 = Failure on Segment 1.." "0: Failure on Segment 0,1: Failure on Segment 1,?,?"
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bitfld.long 0xC 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode) 0 = No time out error occurred 1 = SelfTest run failed due to a timeout error" "0: No time out error occurred,1: SelfTest run failed due to a timeout error"
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bitfld.long 0xC 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode) 0 = No MISR mismatch for CORE2 1 = Self test run failed due to MISR mismatch for CORE2" "0: No MISR mismatch for CORE2,1: Self test run failed due to MISR mismatch for.."
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bitfld.long 0xC 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments. 0 = No MISR mismatch for CORE1 1 = Self test run failed due to MISR mismatch for CORE1" "0: No MISR mismatch for CORE1,1: Self test run failed due to MISR mismatch for.."
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group.long 0x1C++0x3
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line.long 0x0 "STCSCSCR,Signature compare Self Check Register"
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hexmask.long 0x0 5.--31. 1. "NU7,Reserved bits"
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bitfld.long 0x0 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only) 0 = No fault insertion. 1 = Inserts fault in the logic unedr test which will make signature compare fail. This feature is used as diagnostic check of the STC IP." "0: No fault insertion,1: Inserts fault in the logic unedr test which will.."
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hexmask.long.byte 0x0 0.--3. 1. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only) 1010 = Signature compare logic Self Check is enabled All values other than 1010 = Signature compare logic Self Check is disabled"
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rgroup.long 0x20++0x3
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line.long 0x0 "STC_CADDR2,Current Address register for CORE2"
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hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE2 This register reflects the current ROM address(for micro code load) accessed during selftest for CORE2 in of case segment0."
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group.long 0x24++0x17
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line.long 0x0 "STC_CLKDIV,Clock Divider Register"
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hexmask.long.byte 0x0 27.--31. 1. "NU8,Reserved bits"
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newline
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bitfld.long 0x0 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 19.--23. 1. "NU9,Reserved bits"
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newline
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bitfld.long 0x0 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 11.--15. 1. "NU10,Reserved bits"
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newline
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bitfld.long 0x0 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 3.--7. 1. "NU11,Reserved bits"
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newline
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bitfld.long 0x0 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
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line.long 0x4 "STC_SEGPLR,Segment 1st interval Preload Register"
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hexmask.long 0x4 2.--31. 1. "NU12,Reserved bits"
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bitfld.long 0x4 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter. The 1st address of each.." "0: Preload the address of the 1st interval of..,1: Preload the address of the 1st interval of..,?,?"
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line.long 0x8 "SEG0_START_ADDR,ROM Start address for Segment0"
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hexmask.long.word 0x8 20.--31. 1. "NU13,Reserved bits"
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hexmask.long.tbyte 0x8 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
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line.long 0xC "SEG1_START_ADDR,ROM Start address for Segment1"
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hexmask.long.word 0xC 20.--31. 1. "NU14,Reserved bits"
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hexmask.long.tbyte 0xC 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
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line.long 0x10 "SEG2_START_ADDR,ROM Start address for Segment2"
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hexmask.long.word 0x10 20.--31. 1. "NU15,Reserved bits"
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newline
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hexmask.long.tbyte 0x10 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
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line.long 0x14 "SEG3_START_ADDR,ROM Start address for Segment3"
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hexmask.long.word 0x14 20.--31. 1. "NU16,Reserved bits"
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newline
|
|
hexmask.long.tbyte 0x14 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment. When STC_GCR0.RS_CNT_B1 field is set to (1x) 'PRELOAD' option this register is used.."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "CORE1_CURMISR_$1,Holds the MISR signature for CORE1"
|
|
hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1 This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.."
|
|
repeat.end
|
|
repeat 12. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C)
|
|
rgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "CORE1_CURMISR_$1,Holds the MISR signature for CORE1"
|
|
hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1 This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.."
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0xAC)++0x3
|
|
line.long 0x0 "CORE2_CURMISR_$1,Holds the MISR signature for CORE2"
|
|
hexmask.long 0x0 0.--31. 1. "C2MISR0,MISR Signature for CORE2 This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.."
|
|
repeat.end
|
|
repeat 12. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C)
|
|
rgroup.long ($2+0xAC)++0x3
|
|
line.long 0x0 "CORE2_CURMISR_$1,Holds the MISR signature for CORE2"
|
|
hexmask.long 0x0 0.--31. 1. "C2MISR0,MISR Signature for CORE2 This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.."
|
|
repeat.end
|
|
tree.end
|
|
tree "MSS_RCM"
|
|
base ad:0x2100000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MSS_RST_CAUSE_CLR,"
|
|
bitfld.long 0x0 0.--2. "clr,Write pulse bit field: Clear bit for rst cause register (writing '111' will clear the rst cause register)" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "MSS_RST_STATUS,"
|
|
hexmask.long.word 0x0 0.--15. 1. "cause,Has the status because of which reset has happened. Bit0: POR Reset Bit1: Warm Reset Bit2: STC Reset Bit3 Reset for CR5A and MSS_CR5A_VIM using MSS_RCM::MSS_CR5SSA_RST_CTRL Bit4: Reset for CR5B and.."
|
|
group.long 0xC++0xD7
|
|
line.long 0x0 "SYSRST_BY_DBG_RST,"
|
|
bitfld.long 0x0 16.--18. "r5b,writing '111' will block debug reset request from CR5B toggling globally reset for CR5B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "r5a,writing '111' will block debug reset request from CR5A toggling globally reset for CR5A" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RST_ASSERDLY,"
|
|
hexmask.long.byte 0x4 0.--7. 1. "common,Value decides number of cycles reset should be asserted for CR5SS related resets"
|
|
line.long 0x8 "RST2ASSERTDLY,"
|
|
hexmask.long.byte 0x8 24.--31. 1. "r5b,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5B"
|
|
hexmask.long.byte 0x8 16.--23. 1. "r5a,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5A"
|
|
hexmask.long.byte 0x8 8.--15. 1. "r5ssb,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5B"
|
|
hexmask.long.byte 0x8 0.--7. 1. "r5ssa,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5A."
|
|
line.long 0xC "RST_WFICHECK,"
|
|
bitfld.long 0xC 24.--26. "r5b,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 16.--18. "r5a,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "r5ssb,writing '000' will disable check for WFI before global reset assertion of CR5B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "r5ssa,writing '000' will disable check for WFI before global reset assertion of CR5A" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "MSS_MCANA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x14 "MSS_MCANB_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANB.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x18 "MSS_QSPI_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x18 0.--11. 1. "clksrcsel,Select line for selecting source clock for QSPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x1C "MSS_RTIA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x20 "MSS_RTIB_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIB.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x24 "MSS_RTIC_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIC.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x28 "MSS_WDT_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x28 0.--11. 1. "clksrcsel,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x2C "MSS_SPIA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x2C 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x30 "MSS_SPIB_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x30 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIB.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x34 "MSS_I2C_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x34 0.--11. 1. "clksrcsel,Select line for selecting source clock for I2C.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x38 "MSS_SCIA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x38 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x3C "MSS_SCIB_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x3C 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIB.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x40 "MSS_CPTS_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x40 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPTS.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x44 "MSS_CPSW_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x44 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPSW.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x48 "MSS_MCANA_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x48 0.--11. 1. "clkdivr,Divider value MCANA selected clock.Data should be loaded as multibit. For example: if divider value of 8(1000) should be selected then '100010001000' should be configured to the register. Refer to TPR12 clock planner for clock reference"
|
|
line.long 0x4C "MSS_MCANB_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x4C 0.--11. 1. "clkdivr,Divider value MCANB selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x50 "MSS_QSPI_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x50 0.--11. 1. "clkdivr,Divider value QSPI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x54 "MSS_RTIA_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x54 0.--11. 1. "clkdivr,Divider value RTIA selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x58 "MSS_RTIB_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x58 0.--11. 1. "clkdivr,Divider value RTIB selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x5C "MSS_RTIC_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x5C 0.--11. 1. "clkdivr,Divider value RTIC selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x60 "MSS_WDT_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x60 0.--11. 1. "clkdivr,Divider value WDT selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x64 "MSS_SPIA_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x64 0.--11. 1. "clkdivr,Divider value SPIA selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x68 "MSS_SPIB_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x68 0.--11. 1. "clkdivr,Divider value SPIB selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x6C "MSS_I2C_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x6C 0.--11. 1. "clkdivr,Divider value I2C selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x70 "MSS_SCIA_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x70 0.--11. 1. "clkdivr,Divider value SCIA selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x74 "MSS_SCIB_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x74 0.--11. 1. "clkdivr,Divider value SCIB selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x78 "MSS_CPTS_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x78 0.--11. 1. "clkdivr,Divider value CPTS selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x7C "MSS_CPSW_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x7C 0.--11. 1. "clkdivr,Divider value CPSW selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x80 "MSS_RGMII_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x80 0.--11. 1. "clkdivr,Divider value RGMII selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x84 "MSS_MII100_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x84 0.--11. 1. "clkdivr,Divider value MII100 selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x88 "MSS_MII10_CLK_DIV_VAL,"
|
|
hexmask.long.tbyte 0x88 0.--23. 1. "clkdivr,Divider value MII10 selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x8C "MSS_GPADC_CLK_DIV_VAL,"
|
|
hexmask.long.tbyte 0x8C 0.--23. 1. "clkdivr,Divider value GPADC selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x90 "MSS_MCANA_CLK_GATE,"
|
|
bitfld.long 0x90 0.--2. "gated,writing '111' will gate clock for MCANA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x94 "MSS_MCANB_CLK_GATE,"
|
|
bitfld.long 0x94 0.--2. "gated,writing '111' will gate clock for MCANB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x98 "MSS_QSPI_CLK_GATE,"
|
|
bitfld.long 0x98 0.--2. "gated,writing '111' will gate clock for QSPI" "0,1,2,3,4,5,6,7"
|
|
line.long 0x9C "MSS_RTIA_CLK_GATE,"
|
|
bitfld.long 0x9C 0.--2. "gated,writing '111' will gate clock for RTIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0xA0 "MSS_RTIB_CLK_GATE,"
|
|
bitfld.long 0xA0 0.--2. "gated,writing '111' will gate clock for RTIB" "0,1,2,3,4,5,6,7"
|
|
line.long 0xA4 "MSS_RTIC_CLK_GATE,"
|
|
bitfld.long 0xA4 0.--2. "gated,writing '111' will gate clock for RTIC" "0,1,2,3,4,5,6,7"
|
|
line.long 0xA8 "MSS_WDT_CLK_GATE,"
|
|
bitfld.long 0xA8 0.--2. "gated,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7"
|
|
line.long 0xAC "MSS_SPIA_CLK_GATE,"
|
|
bitfld.long 0xAC 0.--2. "gated,writing '111' will gate clock for SPIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0xB0 "MSS_SPIB_CLK_GATE,"
|
|
bitfld.long 0xB0 0.--2. "gated,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7"
|
|
line.long 0xB4 "MSS_I2C_CLK_GATE,"
|
|
bitfld.long 0xB4 0.--2. "gated,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7"
|
|
line.long 0xB8 "MSS_SCIA_CLK_GATE,"
|
|
bitfld.long 0xB8 0.--2. "gated,writing '111' will gate clock for SCIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0xBC "MSS_SCIB_CLK_GATE,"
|
|
bitfld.long 0xBC 0.--2. "gated,writing '111' will gate clock for SCIB" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC0 "MSS_CPTS_CLK_GATE,"
|
|
bitfld.long 0xC0 0.--2. "gated,writing '111' will gate clock for CPTS" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC4 "MSS_CPSW_CLK_GATE,"
|
|
bitfld.long 0xC4 0.--2. "gated,writing '111' will gate clock for CPSW" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC8 "MSS_RGMII_CLK_GATE,"
|
|
bitfld.long 0xC8 0.--2. "gated,writing '111' will gate clock for RGMII" "0,1,2,3,4,5,6,7"
|
|
line.long 0xCC "MSS_MII100_CLK_GATE,"
|
|
bitfld.long 0xCC 0.--2. "gated,writing '111' will gate clock for MII100" "0,1,2,3,4,5,6,7"
|
|
line.long 0xD0 "MSS_MII10_CLK_GATE,"
|
|
bitfld.long 0xD0 0.--2. "gated,writing '111' will gate clock for MII10" "0,1,2,3,4,5,6,7"
|
|
line.long 0xD4 "MSS_GPADC_CLK_GATE,"
|
|
bitfld.long 0xD4 0.--2. "gated,writing '111' will gate clock for MSS GPADC" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xE4++0x47
|
|
line.long 0x0 "MSS_MCANA_CLK_STATUS,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANA"
|
|
hexmask.long.byte 0x0 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANA"
|
|
line.long 0x4 "MSS_MCANB_CLK_STATUS,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANB"
|
|
hexmask.long.byte 0x4 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANB"
|
|
line.long 0x8 "MSS_QSPI_CLK_STATUS,"
|
|
hexmask.long.byte 0x8 8.--15. 1. "currdivider,Status shows the current divider value choosen for QSPI"
|
|
hexmask.long.byte 0x8 0.--7. 1. "clkinuse,Status shows the source clock slected for QSPI"
|
|
line.long 0xC "MSS_RTIA_CLK_STATUS,"
|
|
hexmask.long.byte 0xC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIA"
|
|
hexmask.long.byte 0xC 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIA"
|
|
line.long 0x10 "MSS_RTIB_CLK_STATUS,"
|
|
hexmask.long.byte 0x10 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIB"
|
|
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIB"
|
|
line.long 0x14 "MSS_RTIC_CLK_STATUS,"
|
|
hexmask.long.byte 0x14 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIC"
|
|
hexmask.long.byte 0x14 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIC"
|
|
line.long 0x18 "MSS_WDT_CLK_STATUS,"
|
|
hexmask.long.byte 0x18 8.--15. 1. "currdivider,Status shows the current divider value choosen for WDT"
|
|
hexmask.long.byte 0x18 0.--7. 1. "clkinuse,Status shows the source clock slected for WDT"
|
|
line.long 0x1C "MSS_SPIA_CLK_STATUS,"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIA"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIA"
|
|
line.long 0x20 "MSS_SPIB_CLK_STATUS,"
|
|
hexmask.long.byte 0x20 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIB"
|
|
hexmask.long.byte 0x20 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIB"
|
|
line.long 0x24 "MSS_I2C_CLK_STATUS,"
|
|
hexmask.long.byte 0x24 8.--15. 1. "currdivider,Status shows the current divider value choosen for I2C"
|
|
hexmask.long.byte 0x24 0.--7. 1. "clkinuse,Status shows the source clock slected for I2C"
|
|
line.long 0x28 "MSS_SCIA_CLK_STATUS,"
|
|
hexmask.long.byte 0x28 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIA"
|
|
hexmask.long.byte 0x28 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIA"
|
|
line.long 0x2C "MSS_SCIB_CLK_STATUS,"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIB"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIB"
|
|
line.long 0x30 "MSS_CPTS_CLK_STATUS,"
|
|
hexmask.long.byte 0x30 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPTS"
|
|
hexmask.long.byte 0x30 0.--7. 1. "clkinuse,Status shows the source clock slected for CPTS"
|
|
line.long 0x34 "MSS_CPSW_CLK_STATUS,"
|
|
hexmask.long.byte 0x34 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPSW"
|
|
hexmask.long.byte 0x34 0.--7. 1. "clkinuse,Status shows the source clock slected for CPSW"
|
|
line.long 0x38 "MSS_RGMII_CLK_STATUS,"
|
|
hexmask.long.byte 0x38 8.--15. 1. "currdivider,Status shows the current divider value choosen for RGMII"
|
|
line.long 0x3C "MSS_MII100_CLK_STATUS,"
|
|
hexmask.long.byte 0x3C 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII100"
|
|
line.long 0x40 "MSS_MII10_CLK_STATUS,"
|
|
hexmask.long.byte 0x40 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII10"
|
|
line.long 0x44 "MSS_GPADC_CLK_STATUS,"
|
|
hexmask.long.byte 0x44 8.--15. 1. "currdivider,Status shows the current divider value choosen for GPADC"
|
|
group.long 0x12C++0x97
|
|
line.long 0x0 "MSS_CR5SS_POR_RST_CTRL,"
|
|
bitfld.long 0x0 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. write pulse bit field: writing '111' will assert por reset to R5SS" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CR5SSA_RST_CTRL,"
|
|
bitfld.long 0x4 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. write pulse bit field: writing '111' will reset CR5A and MSS_CR5A_VIM" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "MSS_CR5SSB_RST_CTRL,"
|
|
bitfld.long 0x8 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. write pulse bit field: writing '111' will reset CR5B and MSS_CR5B_VIM" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "MSS_CR5A_RST_CTRL,"
|
|
bitfld.long 0xC 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. write pulse bit field: writing '111' will reset CR5A only" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "MSS_CR5B_RST_CTRL,"
|
|
bitfld.long 0x10 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. write pulse bit field: writing '111' will reset CR5B only" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "MSS_VIMA_RST_CTRL,"
|
|
bitfld.long 0x14 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_CR5A_VIM" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "MSS_VIMB_RST_CTRL,"
|
|
bitfld.long 0x18 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_CR5B_VIM" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "MSS_CRC_RST_CTRL,"
|
|
bitfld.long 0x1C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MCRC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "MSS_RTIA_RST_CTRL,"
|
|
bitfld.long 0x20 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset RTIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "MSS_RTIB_RST_CTRL,"
|
|
bitfld.long 0x24 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset RTIB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "MSS_RTIC_RST_CTRL,"
|
|
bitfld.long 0x28 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset RTIC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "MSS_WDT_RST_CTRL,"
|
|
bitfld.long 0x2C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset WDT" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "MSS_ESM_RST_CTRL,"
|
|
bitfld.long 0x30 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset ESM" "0,1,2,3,4,5,6,7"
|
|
line.long 0x34 "MSS_DCCA_RST_CTRL,"
|
|
bitfld.long 0x34 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "MSS_DCCB_RST_CTRL,"
|
|
bitfld.long 0x38 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x3C "MSS_DCCC_RST_CTRL,"
|
|
bitfld.long 0x3C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x40 "MSS_DCCD_RST_CTRL,"
|
|
bitfld.long 0x40 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCD" "0,1,2,3,4,5,6,7"
|
|
line.long 0x44 "MSS_GIO_RST_CTRL,"
|
|
bitfld.long 0x44 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset GIO" "0,1,2,3,4,5,6,7"
|
|
line.long 0x48 "MSS_SPIA_RST_CTRL,"
|
|
bitfld.long 0x48 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset SPIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4C "MSS_SPIB_RST_CTRL,"
|
|
bitfld.long 0x4C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset SPIB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x50 "MSS_QSPI_RST_CTRL,"
|
|
bitfld.long 0x50 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset QSPI" "0,1,2,3,4,5,6,7"
|
|
line.long 0x54 "MSS_PWM1_RST_CTRL,"
|
|
bitfld.long 0x54 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset EPWM1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x58 "MSS_PWM2_RST_CTRL,"
|
|
bitfld.long 0x58 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset EPWM2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x5C "MSS_PWM3_RST_CTRL,"
|
|
bitfld.long 0x5C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset EPWM3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x60 "MSS_MCANA_RST_CTRL,"
|
|
bitfld.long 0x60 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MCANA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x64 "MSS_MCANB_RST_CTRL,"
|
|
bitfld.long 0x64 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MCANB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x68 "MSS_I2C_RST_CTRL,"
|
|
bitfld.long 0x68 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset I2C" "0,1,2,3,4,5,6,7"
|
|
line.long 0x6C "MSS_SCIA_RST_CTRL,"
|
|
bitfld.long 0x6C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset SCIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x70 "MSS_SCIB_RST_CTRL,"
|
|
bitfld.long 0x70 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset SCIB" "0,1,2,3,4,5,6,7"
|
|
line.long 0x74 "MSS_EDMA_RST_CTRL,"
|
|
bitfld.long 0x74 24.--26. "tptcb0_assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPTCB0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x74 16.--18. "tpccb_assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPCCB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x74 12.--14. "tptca1_assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPTCA1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x74 8.--10. "tptca0_assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPTCA0" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x74 4.--6. "tpcca_assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPCCA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x74 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset EDMA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x78 "MSS_INFRA_RST_CTRL,"
|
|
bitfld.long 0x78 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS INFRA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x7C "MSS_CPSW_RST_CTRL,"
|
|
bitfld.long 0x7C 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS CPSW" "0,1,2,3,4,5,6,7"
|
|
line.long 0x80 "MSS_GPADC_RST_CTRL,"
|
|
bitfld.long 0x80 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS GPADC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x84 "MSS_DMM_RST_CTRL,"
|
|
bitfld.long 0x84 0.--2. "assert,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS DMMA/B" "0,1,2,3,4,5,6,7"
|
|
line.long 0x88 "R5_COREA_GATE,"
|
|
bitfld.long 0x88 0.--2. "clkgate,writing '111' will gate clock to CR5A related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8C "R5_COREB_GATE,"
|
|
bitfld.long 0x8C 0.--2. "clkgate,writing '111' will gate clock to CR5B related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
|
|
line.long 0x90 "MSS_L2_BANKA_PD_CTRL,"
|
|
bitfld.long 0x90 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x90 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x90 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x94 "MSS_L2_BANKB_PD_CTRL,"
|
|
bitfld.long 0x94 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x94 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x94 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C4++0x7
|
|
line.long 0x0 "MSS_L2_BANKA_PD_STATUS,"
|
|
bitfld.long 0x0 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKA" "0,1"
|
|
bitfld.long 0x0 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKA" "0,1"
|
|
line.long 0x4 "MSS_L2_BANKB_PD_STATUS,"
|
|
bitfld.long 0x4 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKB" "0,1"
|
|
bitfld.long 0x4 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKB" "0,1"
|
|
repeat 3. (list 0x0 0x1 0x3)(list 0x0 0x4 0xC)
|
|
group.long ($2+0x1CC)++0x3
|
|
line.long 0x0 "HW_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser"
|
|
repeat.end
|
|
group.long 0x1D4++0x3
|
|
line.long 0x0 "PREVIOUS_NAME,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser"
|
|
group.long 0x1DC++0x7
|
|
line.long 0x0 "MSS_CR5F_CLK_SRC_SEL_CTRL,"
|
|
bitfld.long 0x0 0.--2. "clksrcsel,writing 3'b111 ensures R5 to be same as BUS_CLK writing 3'b000 ensures R5 clock will be same as CR5_CLK from top_rcm" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "MSS_CPSW_MII_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x4 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPSW_MII.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
rgroup.long 0x1E4++0x3
|
|
line.long 0x0 "MSS_CPSW_MII_CLK_STATUS,"
|
|
hexmask.long.byte 0x0 0.--7. 1. "clkinuse,Status shows the source clock slected for CPSW_MII"
|
|
group.long 0x400++0x3B
|
|
line.long 0x0 "HSM_RTIA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x0 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTIA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x4 "HSM_WDT_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x4 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x8 "HSM_RTC_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x8 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTC.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0xC "HSM_DMTA_CLK_SRC_SEL,"
|
|
hexmask.long.word 0xC 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x10 "HSM_DMTB_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTB.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x14 "HSM_RTI_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x14 0.--11. 1. "clkdivr,Divider value HSM RTI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x18 "HSM_WDT_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x18 0.--11. 1. "clkdivr,Divider value HSM WDT selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x1C "HSM_RTC_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x1C 0.--11. 1. "clkdivr,Divider value HSM RTC selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x20 "HSM_DMTA_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x20 0.--11. 1. "clkdivr,Divider value HSM DMTA selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x24 "HSM_DMTB_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x24 0.--11. 1. "clkdivr,Divider value HSM DMTB selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. Refer to TPR12 clock spec for clock reference"
|
|
line.long 0x28 "HSM_RTI_CLK_GATE,"
|
|
bitfld.long 0x28 0.--2. "gated,writing '111' will gate clock for HSM RTI" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "HSM_WDT_CLK_GATE,"
|
|
bitfld.long 0x2C 0.--2. "gated,writing '111' will gate clock for HSM WDT" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "HSM_RTC_CLK_GATE,"
|
|
bitfld.long 0x30 0.--2. "gated,writing '111' will gate clock for HSM RTC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x34 "HSM_DMTA_CLK_GATE,"
|
|
bitfld.long 0x34 0.--2. "gated,writing '111' will gate clock for HSM DMTA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "HSM_DMTB_CLK_GATE,"
|
|
bitfld.long 0x38 0.--2. "gated,writing '111' will gate clock for HSM DMTB" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x43C++0x13
|
|
line.long 0x0 "HSM_RTI_CLK_STATUS,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTI"
|
|
hexmask.long.byte 0x0 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTI"
|
|
line.long 0x4 "HSM_WDT_CLK_STATUS,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_WDT"
|
|
hexmask.long.byte 0x4 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_WDT"
|
|
line.long 0x8 "HSM_RTC_CLK_STATUS,"
|
|
hexmask.long.byte 0x8 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTC"
|
|
hexmask.long.byte 0x8 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTC"
|
|
line.long 0xC "HSM_DMTA_CLK_STATUS,"
|
|
hexmask.long.byte 0xC 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTA"
|
|
hexmask.long.byte 0xC 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTA"
|
|
line.long 0x10 "HSM_DMTB_CLK_STATUS,"
|
|
hexmask.long.byte 0x10 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTB"
|
|
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTB"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_wph,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MSS_RTIA"
|
|
base ad:0x2F7A000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "RTIGCTRL,Global Control Register starts / stops the counters"
|
|
hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved. Reads return 0 and writes have no effect"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.."
|
|
newline
|
|
bitfld.long 0x0 15. "COS,COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while.." "0: stop counters in debug mode,1: continue counting in debug mode"
|
|
hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved. Reads return 0 and writes have no effect"
|
|
newline
|
|
bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bit.."
|
|
bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bits source.."
|
|
line.long 0x4 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
|
|
hexmask.long 0x4 2.--31. 1. "RESERVED3,Reserved"
|
|
bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
|
|
newline
|
|
bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
|
|
line.long 0x8 "RTICAPCTRL,Capture Control controls the capture source for the counters"
|
|
hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1. This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
|
|
newline
|
|
bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
|
|
line.long 0xC "RTICOMPCTRL,Compare Control controls the source for the compare registers"
|
|
hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
newline
|
|
bitfld.long 0xC 9.--11. "RESERVED7,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
newline
|
|
bitfld.long 0xC 5.--7. "RESERVED6,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
newline
|
|
bitfld.long 0xC 1.--3. "RESERVED5,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
|
|
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
|
|
hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
|
|
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
|
|
hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.."
|
|
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
|
|
hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
|
|
hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0.."
|
|
line.long 0x4 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
|
|
hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0."
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
|
|
hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
|
|
line.long 0x4 "RTIUC1,Up Counter 1 current value of prescale counter 1"
|
|
hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.."
|
|
line.long 0x8 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
|
|
hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
|
|
hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1.."
|
|
line.long 0x4 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
|
|
hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1."
|
|
group.long 0x50++0x27
|
|
line.long 0x0 "RTICOMP0,Compare 0 compare value to be compared with the counters"
|
|
hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
|
|
line.long 0x4 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
|
|
hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
|
|
line.long 0x8 "RTICOMP1,Compare 1 compare value to be compared with the counters"
|
|
hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
|
|
line.long 0xC "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
|
|
hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register. This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
|
|
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
|
|
hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
|
|
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
|
|
hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
|
|
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
|
|
hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
|
|
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
|
|
hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
|
|
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
|
|
hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when.."
|
|
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
|
|
hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.."
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
|
|
hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
|
|
bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved. Reads return 0 and writes have no effect"
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|
bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,1: interrupt is enabled Privilege mode"
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bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
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bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
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hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
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hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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group.long 0x90++0x2F
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line.long 0x0 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
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hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled).."
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line.long 0x4 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
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hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts.."
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line.long 0x8 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
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hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read):.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 -> 1 threshold not exceeded 1 = AWD pin 0 -> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
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line.long 0xC "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
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hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.."
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line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
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hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved. Reads return 0 and writes have no effect"
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hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.."
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line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
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hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.."
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line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
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hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read) privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital.."
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line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
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hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled."
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hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled."
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hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled."
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hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled."
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line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
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hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.."
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line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
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hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.."
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line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
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hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.."
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line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
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hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.."
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tree.end
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tree "MSS_RTIB"
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base ad:0x2F7A100
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group.long 0x0++0x1B
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line.long 0x0 "RTIGCTRL,Global Control Register starts / stops the counters"
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hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.."
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bitfld.long 0x0 15. "COS,COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while.." "0: stop counters in debug mode,1: continue counting in debug mode"
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hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved. Reads return 0 and writes have no effect"
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newline
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bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bit.."
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bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bits source.."
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line.long 0x4 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
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hexmask.long 0x4 2.--31. 1. "RESERVED3,Reserved"
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bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
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newline
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bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
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line.long 0x8 "RTICAPCTRL,Capture Control controls the capture source for the counters"
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hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1. This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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newline
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bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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line.long 0xC "RTICOMPCTRL,Compare Control controls the source for the compare registers"
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hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 9.--11. "RESERVED7,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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newline
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bitfld.long 0xC 5.--7. "RESERVED6,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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newline
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bitfld.long 0xC 1.--3. "RESERVED5,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
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hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
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hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
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hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
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group.long 0x20++0x7
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line.long 0x0 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0.."
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line.long 0x4 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0."
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group.long 0x30++0xB
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line.long 0x0 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
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hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x4 "RTIUC1,Up Counter 1 current value of prescale counter 1"
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hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x8 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
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hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
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group.long 0x40++0x7
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line.long 0x0 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1.."
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line.long 0x4 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1."
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group.long 0x50++0x27
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line.long 0x0 "RTICOMP0,Compare 0 compare value to be compared with the counters"
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hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x4 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
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hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x8 "RTICOMP1,Compare 1 compare value to be compared with the counters"
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hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0xC "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
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hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register. This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
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hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
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hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
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hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
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hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
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hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when.."
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line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
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hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.."
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group.long 0x80++0xB
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line.long 0x0 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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newline
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bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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newline
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bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved. Reads return 0 and writes have no effect"
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newline
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bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,1: interrupt is enabled Privilege mode"
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bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
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bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
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bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
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bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved. Reads return 0 and writes have no effect"
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newline
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bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
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bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
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hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
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hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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group.long 0x90++0x2F
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line.long 0x0 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
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hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled).."
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line.long 0x4 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
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hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts.."
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line.long 0x8 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
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hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read):.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 -> 1 threshold not exceeded 1 = AWD pin 0 -> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
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line.long 0xC "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
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hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.."
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line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
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hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved. Reads return 0 and writes have no effect"
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hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.."
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line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
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hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.."
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line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
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hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read) privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital.."
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line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
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hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled."
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newline
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hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled."
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newline
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hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled."
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newline
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hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled."
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line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
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hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.."
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line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
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hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.."
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line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
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hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.."
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line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
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hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.."
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tree.end
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tree "MSS_RTIC"
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base ad:0x2F7A200
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group.long 0x0++0x1B
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line.long 0x0 "RTIGCTRL,Global Control Register starts / stops the counters"
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hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.."
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newline
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bitfld.long 0x0 15. "COS,COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while.." "0: stop counters in debug mode,1: continue counting in debug mode"
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hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved. Reads return 0 and writes have no effect"
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newline
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bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bit.."
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bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bits source.."
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line.long 0x4 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
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hexmask.long 0x4 2.--31. 1. "RESERVED3,Reserved"
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bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
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newline
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bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
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line.long 0x8 "RTICAPCTRL,Capture Control controls the capture source for the counters"
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hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1. This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
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line.long 0xC "RTICOMPCTRL,Compare Control controls the source for the compare registers"
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hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 9.--11. "RESERVED7,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 5.--7. "RESERVED6,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 1.--3. "RESERVED5,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
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hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
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hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
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hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
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group.long 0x20++0x7
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line.long 0x0 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0.."
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line.long 0x4 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0."
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group.long 0x30++0xB
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line.long 0x0 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
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hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x4 "RTIUC1,Up Counter 1 current value of prescale counter 1"
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hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x8 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
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hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
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group.long 0x40++0x7
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line.long 0x0 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1.."
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line.long 0x4 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1."
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group.long 0x50++0x27
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line.long 0x0 "RTICOMP0,Compare 0 compare value to be compared with the counters"
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hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x4 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
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hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x8 "RTICOMP1,Compare 1 compare value to be compared with the counters"
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hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0xC "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
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hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register. This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
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hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
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hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
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hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
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hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
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hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when.."
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line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
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hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.."
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group.long 0x80++0xB
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line.long 0x0 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,1: interrupt is enabled Privilege mode"
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bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
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hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
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hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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newline
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bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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group.long 0x90++0x2F
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line.long 0x0 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
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hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled).."
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line.long 0x4 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
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hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts.."
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line.long 0x8 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
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hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read):.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 -> 1 threshold not exceeded 1 = AWD pin 0 -> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
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line.long 0xC "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
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hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.."
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line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
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hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved. Reads return 0 and writes have no effect"
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hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.."
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line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
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hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.."
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line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
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hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read) privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital.."
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line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
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hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled."
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hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled."
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|
newline
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hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved. Reads return 0 and writes have no effect"
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|
hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled."
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|
newline
|
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hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled."
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line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
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hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.."
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line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
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hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.."
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line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
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hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.."
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line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
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hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.."
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tree.end
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tree "MSS_SCIA"
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base ad:0x2F7EC00
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group.long 0x0++0x7
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line.long 0x0 "SCIGCR0,The SCIGCR0 register defines the module reset"
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hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x0 0. "RESET,GIO reset" "0,1"
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line.long 0x4 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
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hexmask.long.byte 0x4 26.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x4 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
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newline
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bitfld.long 0x4 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
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newline
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hexmask.long.byte 0x4 18.--23. 1. "RESERVED3,Reserved"
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newline
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bitfld.long 0x4 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
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newline
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bitfld.long 0x4 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
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newline
|
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hexmask.long.byte 0x4 10.--15. 1. "RESERVED2,Reserved"
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newline
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bitfld.long 0x4 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
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newline
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bitfld.long 0x4 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode" "0,1"
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newline
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bitfld.long 0x4 7. "SW_nRESET,Software reset (active low)" "0,1"
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newline
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rbitfld.long 0x4 6. "RESERVED1,Reserved" "0,1"
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newline
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bitfld.long 0x4 5. "CLOCK,SCI internal clock enable" "0,1"
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newline
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bitfld.long 0x4 4. "STOP,SCI number of stop bits" "0,1"
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newline
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bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection" "0,1"
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newline
|
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bitfld.long 0x4 2. "PARITY_ENA,SCI parity enable" "0,1"
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newline
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bitfld.long 0x4 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0: Isosynchronous timing,1: Asynchronous timing)"
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newline
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bitfld.long 0x4 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0: Idle-line mode,1: Address-bit mode)"
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repeat 9. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list 0x0 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74)
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rgroup.long ($2+0x8)++0x3
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line.long 0x0 "RESERVED$1,Reserved"
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hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved"
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repeat.end
|
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group.long 0xC++0x13
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line.long 0x0 "SCISETINT,SCI Set Interrupt Register"
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hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x0 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x0 19.--23. 1. "RESERVED3,Reserved"
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newline
|
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bitfld.long 0x0 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address.." "0: leaves the corresponding bit unchanged,1: enable DMA request for address and data frames"
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newline
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bitfld.long 0x0 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set. If it is cleared interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode.." "0: leaves the corresponding bit unchanged,1: enable DMA request"
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newline
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bitfld.long 0x0 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x0 10.--15. 1. "RESERVED2,Reserved"
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newline
|
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bitfld.long 0x0 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 8. "SET_TX_INT,Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 =.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x0 2.--7. 1. "RESERVED1,Reserved"
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newline
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bitfld.long 0x0 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 0. "SET_BRKDT_INT,Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "SCICLEARINT,SCI Clear Interrupt Register"
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hexmask.long.byte 0x4 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x4 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
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bitfld.long 0x4 25. "CLR_OE_INT,Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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bitfld.long 0x4 24. "CLR_PE_INT,Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
|
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hexmask.long.byte 0x4 19.--23. 1. "RESERVED3,Reserved"
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newline
|
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bitfld.long 0x4 18. "CLR_RX_DMA_ALL,User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and.." "0: leaves the corresponding bit unchanged,1: disable DMA request for address frames"
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newline
|
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bitfld.long 0x4 17. "CLR_RX_DMA,Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
|
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bitfld.long 0x4 16. "CLR_TX_DMA,Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable DMA request"
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newline
|
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hexmask.long.byte 0x4 10.--15. 1. "RESERVED2,Reserved"
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newline
|
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bitfld.long 0x4 9. "CLR_RX_INT,Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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bitfld.long 0x4 8. "CLR_TX_INT,Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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hexmask.long.byte 0x4 2.--7. 1. "RESERVED1,Reserved"
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newline
|
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bitfld.long 0x4 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
|
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bitfld.long 0x4 0. "CLR_BRKDT_INT,Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "SCISETINTLVL,SCI Set Interrupt Level Register"
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hexmask.long.byte 0x8 27.--31. 1. "RESERVED5,Reserved"
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newline
|
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bitfld.long 0x8 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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bitfld.long 0x8 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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bitfld.long 0x8 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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hexmask.long.byte 0x8 19.--23. 1. "RESERVED4,Reserved"
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|
newline
|
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bitfld.long 0x8 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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rbitfld.long 0x8 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x8 15. "SET_INC_BR_INT_LVL," "0,1"
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|
newline
|
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hexmask.long.byte 0x8 10.--14. 1. "RESERVED2,Reserved"
|
|
newline
|
|
bitfld.long 0x8 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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bitfld.long 0x8 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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hexmask.long.byte 0x8 2.--7. 1. "RESERVED1,Reserved"
|
|
newline
|
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bitfld.long 0x8 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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newline
|
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bitfld.long 0x8 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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line.long 0xC "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
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hexmask.long.byte 0xC 27.--31. 1. "RESERVED5,Reserved"
|
|
newline
|
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bitfld.long 0xC 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
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bitfld.long 0xC 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
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newline
|
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bitfld.long 0xC 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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newline
|
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hexmask.long.byte 0xC 19.--23. 1. "RESERVED4,Reserved"
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|
newline
|
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bitfld.long 0xC 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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|
newline
|
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rbitfld.long 0xC 16.--17. "RESERVED3,Reserved" "0,1,2,3"
|
|
newline
|
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bitfld.long 0xC 15. "CLR_INC_BR_INT_LVL," "0,1"
|
|
newline
|
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hexmask.long.byte 0xC 10.--14. 1. "RESERVED2,Reserved"
|
|
newline
|
|
bitfld.long 0xC 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
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bitfld.long 0xC 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
newline
|
|
hexmask.long.byte 0xC 2.--7. 1. "RESERVED1,Reserved"
|
|
newline
|
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bitfld.long 0xC 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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newline
|
|
bitfld.long 0xC 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
|
|
line.long 0x10 "SCIFLR,SCI Flags Register"
|
|
hexmask.long.byte 0x10 27.--31. 1. "RESERVED3,Reserved"
|
|
newline
|
|
bitfld.long 0x10 26. "FE,SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0" "0: No framing error detected 1=Framing error..,?"
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|
newline
|
|
rbitfld.long 0x10 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 24. "PE,SCI parity error flag. This bit is set when a parity error is detected in the received data" "0,1"
|
|
newline
|
|
hexmask.long.word 0x10 13.--23. 1. "RESERVED2,Reserved"
|
|
newline
|
|
rbitfld.long 0x10 12. "RXWAKE,Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 11. "TX_EMPTY,Transmitter empty flag. The value of this flag indicates the contents of the transmitter's buffer register (SCITD) and shift register (SCITXSHF)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "TXWAKE,SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format" "0,1"
|
|
newline
|
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rbitfld.long 0x10 9. "RXRDY,SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 8. "TXRDY,Transmitter buffer register ready flag. When set this bit indicates that the transmit buffer register (SCITD) is ready to receive another character." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--7. 1. "RESERVED1,Reserved"
|
|
newline
|
|
rbitfld.long 0x10 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 2. "IDLE,SCI receiver in idle state. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream." "0,1"
|
|
newline
|
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rbitfld.long 0x10 1. "WAKEUP,Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "BRKDT,SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin." "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
|
|
hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTVECT0,Interrupt vector offset for INT0"
|
|
line.long 0x4 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
|
|
hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "INTVECT1,Interrupt vector offset for INT1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SCICHAR,SCI Character Control Register"
|
|
hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SCIBAUD,SCI Baud Rate Selection Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved"
|
|
newline
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hexmask.long.tbyte 0x4 0.--23. 1. "BAUD,SCI 24-bit baud selection"
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rgroup.long 0x30++0x7
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line.long 0x0 "SCIED,Receiver Emulation Data Buffer"
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|
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data Buffer"
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line.long 0x4 "SCIRD,Receiver Data Buffer"
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hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x4 0.--7. 1. "RD,Contains received data."
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group.long 0x38++0x27
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line.long 0x0 "SCITD,Transmit Data Buffer Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x0 0.--7. 1. "TD,Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."
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line.long 0x4 "SCIPIO0,SCI Pin I/O Control Register 0"
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hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4 2. "TX_FUNC,Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin. 0=SCIRX is a general-purpose digital I/O pin. 1=SCIRX is the SCI receive pin." "0: SCIRX is a general-purpose digital I/O pin,1: SCIRX is the SCI receive pin"
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bitfld.long 0x4 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin" "0: SCIRX is a general-purpose input pin,1: SCIRX is a general-purpose output pin"
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bitfld.long 0x4 0. "CLK_FUNC,Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the.." "0: SCICLK is a general-purpose digital I/O pin,1: SCICLK is the SCI serial clock pin"
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line.long 0x8 "SCIPIO1,SCI Pin I/O Control Register 1"
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hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x8 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin" "0: SCITX is a general-purpose input pin,1: SCITX is a general-purpose output pin"
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bitfld.long 0x8 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin" "0: SCIRX is a general-purpose input pin,1: SCIRX is a general-purpose output pin"
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newline
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bitfld.long 0x8 0. "CLK_DIR,Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit" "0,1"
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line.long 0xC "SCIPIO2,SCI Pin I/O Control Register 2"
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hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0xC 2. "TX_DATA_IN,Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high." "0: SCITX value is logic low,1: SCITX value is logic high"
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bitfld.long 0xC 1. "RX_DATA_IN,Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high." "0: SCIRX value is logic low,1: SCIRX value is logic high"
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bitfld.long 0xC 0. "CLK_DATA_IN,Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high." "0: Pin SCICLK value is logic low,1: Pin SCICLK value is logic high"
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line.long 0x10 "SCIPIO3,SCI Pin I/O Control Register 3"
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hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x10 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output.." "0: Output value on SCITX is a 0,1: Output value on SCITX is a 1"
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bitfld.long 0x10 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output.." "0: Output value on SCIRX is 0,1: Output value on SCIRX is 1"
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bitfld.long 0x10 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low)." "0: Output value on SCICLK is a 0,1: Output value on SCICLK is a 1"
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line.long 0x14 "SCIPIO4,SCI Pin I/O Control Register 4"
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hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x14 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x14 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x14 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
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line.long 0x18 "SCIPIO5,SCI Pin I/O Control Register 5"
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hexmask.long 0x18 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x18 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x18 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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newline
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bitfld.long 0x18 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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line.long 0x1C "SCIPIO6,SCI Pin I/O Control Register 6"
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hexmask.long 0x1C 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x1C 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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newline
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bitfld.long 0x1C 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x1C 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
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line.long 0x20 "SCIPIO7,SCI Pin I/O Control Register 7"
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hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x20 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled." "0: Pull Control on SCITX pin is enabled,1: Pull Control on SCITX pin is disabled"
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newline
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bitfld.long 0x20 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled." "0: Pull Control on SCIRX pin is enabled,1: Pull Control on SCIRX pin is disabled"
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newline
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bitfld.long 0x20 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled." "0: Pull Control on SCICLK pin is enabled,1: Pull Control on SCICLK pin is disabled"
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line.long 0x24 "SCIPIO8,SCI Pin I/O Control Register 8"
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hexmask.long 0x24 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x24 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin." "0: Pull-Down is on SCITX pin,1: Pull-Up is on SCITX pin"
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newline
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bitfld.long 0x24 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin." "0: Pull-Down is on SCIRX pin,1: Pull-Up is on SCIRX pin"
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newline
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bitfld.long 0x24 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin." "0: Pull-Down is on SCICLK pin,1: Pull-Up is on SCICLK pin"
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group.long 0x80++0x3
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line.long 0x0 "SCIPIO9,SCI Pin I/O Control Register 9"
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hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x0 2. "TX_SL,This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin." "0: The normal output buffer is used for SCITX pin..,?"
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newline
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bitfld.long 0x0 1. "RX_SL,This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin" "0: The normal output buffer is used for SCIRX pin..,?"
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newline
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bitfld.long 0x0 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin" "0: The normal output buffer is used for SCICLK pin..,?"
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group.long 0x90++0x3
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line.long 0x0 "SCIIODCTRL,SCI IO DFT Control"
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hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x0 26. "FEN,Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with '0' and passed to the stop bit check circuitry. 0 = No effect." "0: No effect,1: This bit is used to create a Frame Error"
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newline
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bitfld.long 0x0 25. "PEN,Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect" "0: No effect,1: This bit is used to create a Parity Error"
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newline
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bitfld.long 0x0 24. "BRKDT_ENA,Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error occurs. Then the RX pin is forced to.." "0: No effect,1: This bit is used to create BRKDT Error"
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rbitfld.long 0x0 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask 01 -- Invert the TX.." "0: No Mask,1: Invert the TX Pin value at 7th SCLK,?,?"
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bitfld.long 0x0 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay 001 -- Delay by 1 SCLK 010 -- Delay by 2 SCLKs 011 -- Delay by 3 SCLKs .." "0: No Delay,1: Delay by 1 SCLK,?,?,?,?,?,?"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED2,Reserved"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay 001 -- Delay by 1 SCLK 010 -- Delay by 2 SCLKs 011 -- Delay by 3 SCLKs .."
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newline
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hexmask.long.byte 0x0 2.--7. 1. "RESERVED1,Reserved"
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newline
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bitfld.long 0x0 1. "LBP_ENA,Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled." "0: Digital loopback is enabled,1: Analog loopback is enabled in module I/O DFT mode"
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newline
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bitfld.long 0x0 0. "RXP_ENA,Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin." "0: Analog loopback through transmit pin,1: Analog loopback through receive pin"
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tree.end
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tree "MSS_SCIB"
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base ad:0x2F7ED00
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group.long 0x0++0x7
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line.long 0x0 "SCIGCR0,The SCIGCR0 register defines the module reset"
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hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved"
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newline
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bitfld.long 0x0 0. "RESET,GIO reset" "0,1"
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line.long 0x4 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
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hexmask.long.byte 0x4 26.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x4 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
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newline
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bitfld.long 0x4 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
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newline
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hexmask.long.byte 0x4 18.--23. 1. "RESERVED3,Reserved"
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newline
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bitfld.long 0x4 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
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newline
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bitfld.long 0x4 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
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newline
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hexmask.long.byte 0x4 10.--15. 1. "RESERVED2,Reserved"
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newline
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bitfld.long 0x4 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
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newline
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bitfld.long 0x4 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode" "0,1"
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newline
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bitfld.long 0x4 7. "SW_nRESET,Software reset (active low)" "0,1"
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newline
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rbitfld.long 0x4 6. "RESERVED1,Reserved" "0,1"
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newline
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bitfld.long 0x4 5. "CLOCK,SCI internal clock enable" "0,1"
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newline
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bitfld.long 0x4 4. "STOP,SCI number of stop bits" "0,1"
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newline
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bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection" "0,1"
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newline
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bitfld.long 0x4 2. "PARITY_ENA,SCI parity enable" "0,1"
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newline
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bitfld.long 0x4 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0: Isosynchronous timing,1: Asynchronous timing)"
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newline
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bitfld.long 0x4 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0: Idle-line mode,1: Address-bit mode)"
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repeat 9. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list 0x0 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74)
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rgroup.long ($2+0x8)++0x3
|
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line.long 0x0 "RESERVED$1,Reserved"
|
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hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved"
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repeat.end
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group.long 0xC++0x13
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line.long 0x0 "SCISETINT,SCI Set Interrupt Register"
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hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x0 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x0 19.--23. 1. "RESERVED3,Reserved"
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newline
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bitfld.long 0x0 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address.." "0: leaves the corresponding bit unchanged,1: enable DMA request for address and data frames"
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newline
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bitfld.long 0x0 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set. If it is cleared interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode.." "0: leaves the corresponding bit unchanged,1: enable DMA request"
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newline
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bitfld.long 0x0 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x0 10.--15. 1. "RESERVED2,Reserved"
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newline
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bitfld.long 0x0 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 8. "SET_TX_INT,Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 =.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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hexmask.long.byte 0x0 2.--7. 1. "RESERVED1,Reserved"
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newline
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bitfld.long 0x0 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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bitfld.long 0x0 0. "SET_BRKDT_INT,Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "SCICLEARINT,SCI Clear Interrupt Register"
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hexmask.long.byte 0x4 27.--31. 1. "RESERVED4,Reserved"
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newline
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bitfld.long 0x4 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
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bitfld.long 0x4 25. "CLR_OE_INT,Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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newline
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bitfld.long 0x4 24. "CLR_PE_INT,Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1.." "0: leaves the corresponding bit unchanged,1: enable interrupt"
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newline
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hexmask.long.byte 0x4 19.--23. 1. "RESERVED3,Reserved"
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newline
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bitfld.long 0x4 18. "CLR_RX_DMA_ALL,User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and.." "0: leaves the corresponding bit unchanged,1: disable DMA request for address frames"
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newline
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bitfld.long 0x4 17. "CLR_RX_DMA,Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 16. "CLR_TX_DMA,Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 10.--15. 1. "RESERVED2,Reserved"
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bitfld.long 0x4 9. "CLR_RX_INT,Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 8. "CLR_TX_INT,Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 2.--7. 1. "RESERVED1,Reserved"
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bitfld.long 0x4 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 =.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLR_BRKDT_INT,Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit.." "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "SCISETINTLVL,SCI Set Interrupt Level Register"
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hexmask.long.byte 0x8 27.--31. 1. "RESERVED5,Reserved"
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bitfld.long 0x8 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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bitfld.long 0x8 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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bitfld.long 0x8 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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hexmask.long.byte 0x8 19.--23. 1. "RESERVED4,Reserved"
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bitfld.long 0x8 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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rbitfld.long 0x8 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x8 15. "SET_INC_BR_INT_LVL," "0,1"
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hexmask.long.byte 0x8 10.--14. 1. "RESERVED2,Reserved"
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bitfld.long 0x8 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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bitfld.long 0x8 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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hexmask.long.byte 0x8 2.--7. 1. "RESERVED1,Reserved"
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bitfld.long 0x8 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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bitfld.long 0x8 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear.." "0: Leaves the corresponding bit unchanged,1: Clear interrupt level to line INT1"
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line.long 0xC "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
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hexmask.long.byte 0xC 27.--31. 1. "RESERVED5,Reserved"
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bitfld.long 0xC 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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bitfld.long 0xC 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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bitfld.long 0xC 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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hexmask.long.byte 0xC 19.--23. 1. "RESERVED4,Reserved"
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bitfld.long 0xC 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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rbitfld.long 0xC 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0xC 15. "CLR_INC_BR_INT_LVL," "0,1"
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hexmask.long.byte 0xC 10.--14. 1. "RESERVED2,Reserved"
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bitfld.long 0xC 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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bitfld.long 0xC 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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hexmask.long.byte 0xC 2.--7. 1. "RESERVED1,Reserved"
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bitfld.long 0xC 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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bitfld.long 0xC 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset.." "0: Leaves the corresponding bit unchanged,1: Reset interrupt level to line INT0"
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line.long 0x10 "SCIFLR,SCI Flags Register"
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hexmask.long.byte 0x10 27.--31. 1. "RESERVED3,Reserved"
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bitfld.long 0x10 26. "FE,SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0" "0: No framing error detected 1=Framing error..,?"
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rbitfld.long 0x10 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x10 24. "PE,SCI parity error flag. This bit is set when a parity error is detected in the received data" "0,1"
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hexmask.long.word 0x10 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x10 12. "RXWAKE,Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address" "0,1"
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rbitfld.long 0x10 11. "TX_EMPTY,Transmitter empty flag. The value of this flag indicates the contents of the transmitter's buffer register (SCITD) and shift register (SCITXSHF)" "0,1"
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bitfld.long 0x10 10. "TXWAKE,SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format" "0,1"
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rbitfld.long 0x10 9. "RXRDY,SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA." "0,1"
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rbitfld.long 0x10 8. "TXRDY,Transmitter buffer register ready flag. When set this bit indicates that the transmit buffer register (SCITD) is ready to receive another character." "0,1"
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hexmask.long.byte 0x10 4.--7. 1. "RESERVED1,Reserved"
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rbitfld.long 0x10 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame." "0,1"
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rbitfld.long 0x10 2. "IDLE,SCI receiver in idle state. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream." "0,1"
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rbitfld.long 0x10 1. "WAKEUP,Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode." "0,1"
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rbitfld.long 0x10 0. "BRKDT,SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin." "0,1"
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rgroup.long 0x20++0x7
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line.long 0x0 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
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hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x0 0.--3. 1. "INTVECT0,Interrupt vector offset for INT0"
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line.long 0x4 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
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hexmask.long 0x4 4.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x4 0.--3. 1. "INTVECT1,Interrupt vector offset for INT1"
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group.long 0x28++0x7
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line.long 0x0 "SCICHAR,SCI Character Control Register"
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hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x0 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
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line.long 0x4 "SCIBAUD,SCI Baud Rate Selection Register"
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hexmask.long.byte 0x4 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x4 0.--23. 1. "BAUD,SCI 24-bit baud selection"
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rgroup.long 0x30++0x7
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line.long 0x0 "SCIED,Receiver Emulation Data Buffer"
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hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data Buffer"
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line.long 0x4 "SCIRD,Receiver Data Buffer"
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hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x4 0.--7. 1. "RD,Contains received data."
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group.long 0x38++0x27
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line.long 0x0 "SCITD,Transmit Data Buffer Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x0 0.--7. 1. "TD,Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register."
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line.long 0x4 "SCIPIO0,SCI Pin I/O Control Register 0"
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hexmask.long 0x4 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4 2. "TX_FUNC,Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin. 0=SCIRX is a general-purpose digital I/O pin. 1=SCIRX is the SCI receive pin." "0: SCIRX is a general-purpose digital I/O pin,1: SCIRX is the SCI receive pin"
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bitfld.long 0x4 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin" "0: SCIRX is a general-purpose input pin,1: SCIRX is a general-purpose output pin"
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bitfld.long 0x4 0. "CLK_FUNC,Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the.." "0: SCICLK is a general-purpose digital I/O pin,1: SCICLK is the SCI serial clock pin"
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line.long 0x8 "SCIPIO1,SCI Pin I/O Control Register 1"
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hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x8 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin" "0: SCITX is a general-purpose input pin,1: SCITX is a general-purpose output pin"
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bitfld.long 0x8 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin" "0: SCIRX is a general-purpose input pin,1: SCIRX is a general-purpose output pin"
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bitfld.long 0x8 0. "CLK_DIR,Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit" "0,1"
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line.long 0xC "SCIPIO2,SCI Pin I/O Control Register 2"
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hexmask.long 0xC 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0xC 2. "TX_DATA_IN,Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high." "0: SCITX value is logic low,1: SCITX value is logic high"
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bitfld.long 0xC 1. "RX_DATA_IN,Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high." "0: SCIRX value is logic low,1: SCIRX value is logic high"
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bitfld.long 0xC 0. "CLK_DATA_IN,Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high." "0: Pin SCICLK value is logic low,1: Pin SCICLK value is logic high"
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line.long 0x10 "SCIPIO3,SCI Pin I/O Control Register 3"
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hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x10 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output.." "0: Output value on SCITX is a 0,1: Output value on SCITX is a 1"
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bitfld.long 0x10 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output.." "0: Output value on SCIRX is 0,1: Output value on SCIRX is 1"
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bitfld.long 0x10 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low)." "0: Output value on SCICLK is a 0,1: Output value on SCICLK is a 1"
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line.long 0x14 "SCIPIO4,SCI Pin I/O Control Register 4"
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hexmask.long 0x14 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x14 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x14 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x14 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
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line.long 0x18 "SCIPIO5,SCI Pin I/O Control Register 5"
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hexmask.long 0x18 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x18 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x18 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x18 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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line.long 0x1C "SCIPIO6,SCI Pin I/O Control Register 6"
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hexmask.long 0x1C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x1C 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x1C 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x1C 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
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line.long 0x20 "SCIPIO7,SCI Pin I/O Control Register 7"
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hexmask.long 0x20 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled." "0: Pull Control on SCITX pin is enabled,1: Pull Control on SCITX pin is disabled"
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bitfld.long 0x20 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled." "0: Pull Control on SCIRX pin is enabled,1: Pull Control on SCIRX pin is disabled"
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bitfld.long 0x20 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled." "0: Pull Control on SCICLK pin is enabled,1: Pull Control on SCICLK pin is disabled"
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line.long 0x24 "SCIPIO8,SCI Pin I/O Control Register 8"
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hexmask.long 0x24 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin." "0: Pull-Down is on SCITX pin,1: Pull-Up is on SCITX pin"
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bitfld.long 0x24 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin." "0: Pull-Down is on SCIRX pin,1: Pull-Up is on SCIRX pin"
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bitfld.long 0x24 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin." "0: Pull-Down is on SCICLK pin,1: Pull-Up is on SCICLK pin"
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group.long 0x80++0x3
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line.long 0x0 "SCIPIO9,SCI Pin I/O Control Register 9"
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hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x0 2. "TX_SL,This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin." "0: The normal output buffer is used for SCITX pin..,?"
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bitfld.long 0x0 1. "RX_SL,This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin" "0: The normal output buffer is used for SCIRX pin..,?"
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bitfld.long 0x0 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin" "0: The normal output buffer is used for SCICLK pin..,?"
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group.long 0x90++0x3
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line.long 0x0 "SCIIODCTRL,SCI IO DFT Control"
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hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,Reserved"
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bitfld.long 0x0 26. "FEN,Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with '0' and passed to the stop bit check circuitry. 0 = No effect." "0: No effect,1: This bit is used to create a Frame Error"
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bitfld.long 0x0 25. "PEN,Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect" "0: No effect,1: This bit is used to create a Parity Error"
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bitfld.long 0x0 24. "BRKDT_ENA,Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error occurs. Then the RX pin is forced to.." "0: No effect,1: This bit is used to create BRKDT Error"
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rbitfld.long 0x0 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask 01 -- Invert the TX.." "0: No Mask,1: Invert the TX Pin value at 7th SCLK,?,?"
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bitfld.long 0x0 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay 001 -- Delay by 1 SCLK 010 -- Delay by 2 SCLKs 011 -- Delay by 3 SCLKs .." "0: No Delay,1: Delay by 1 SCLK,?,?,?,?,?,?"
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED2,Reserved"
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hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay 001 -- Delay by 1 SCLK 010 -- Delay by 2 SCLKs 011 -- Delay by 3 SCLKs .."
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hexmask.long.byte 0x0 2.--7. 1. "RESERVED1,Reserved"
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bitfld.long 0x0 1. "LBP_ENA,Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled." "0: Digital loopback is enabled,1: Analog loopback is enabled in module I/O DFT mode"
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bitfld.long 0x0 0. "RXP_ENA,Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin." "0: Analog loopback through transmit pin,1: Analog loopback through receive pin"
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tree.end
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tree "MSS_SPIA"
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base ad:0x2F7E800
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group.long 0x0++0x1B
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line.long 0x0 "SPIGCR0,SPI / MibSPI Global Control Register 0"
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hexmask.long 0x0 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect."
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bitfld.long 0x0 0. "nRESET,This is the local reset control for the module. This bit needs to be set to '1' before any operation on SPI / MibSPI can be done. Only after setting this bit to '1' the Auto Initialization of Multibuffer RAM starts. Clearing this bit to.." "0: SPI / MibSPI is in reset state,1: SPI / MibSPI is out of reset state"
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line.long 0x4 "SPIGCR1,SPI / MibSPI Global control register 1"
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hexmask.long.byte 0x4 25.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 24. "SPIEN,SPI enable. This bit enables the SPI/MibSPI transfers. This bit must be set to 1 after all other SPI / MibSPI configuration bits have been written. When SPIEN bit is 0 or cleared to 0 the following SPI/MibSPI registers get forced to their default.." "0: SPI / MibSPI is not activated for transfers,1: Activates SPI / MibSPI"
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hexmask.long.byte 0x4 17.--23. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 16. "LOOPBACK,LOOP BACK. Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. If the SPISIMO and SPISOMI pins are configured with SPI functionality then the SPISIMO pin is internally connected to the SPISOMI pin." "0: Internal loop-back test mode disabled,1: Internal loop-back test mode enabled"
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hexmask.long.byte 0x4 9.--15. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 8. "POWERDOWN,POWERDOWN. When active the SPI / MibSPI state machines enter a powerdown state. 0=MibSPI in active mode 1=MibSPI in powerdown mode" "0: MibSPI in active mode 1=MibSPI in powerdown mode,?"
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hexmask.long.byte 0x4 2.--7. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 1. "CLKMOD,CLKMOD. Clock mode Selects either an internal or external clock source. This bit also determines the I/O direction of the SPIENA and SPISCS[7:0] pins in functional mode. 0=Clock is external 1=Clock is internal" "0: Clock is external 1=Clock is internal,?"
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bitfld.long 0x4 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination. Determines the direction of the SPISIMO and SPISOMI pins. This bit determines whether the SPI/MibSPI is in Master mode or Slave mode. This bit also controls the Master-only features like the.." "0: SPISIMO pin an input,1: SPISOMI pin an input"
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line.long 0x8 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
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hexmask.long.byte 0x8 25.--31. 1. "NU5,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 24. "ENABLEHIGHZ,SPIENA pin high-z enable. When active the SPIENA pin (when it is configured as a WAIT functional output signal in a slave SPI) is forced to place it is output in high-z when not driving a low signal. If inactive then the pin will output.." "0: SPIENA pin is pulled high when not active,1: SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x8 17.--23. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 16. "DMAREQEN,DMA request enable. Enables the DMA request signal to be generated for both receive and transmit channels. Enable DMA REQ only after setting the SPIEN bit to '1'. 0=DMA is not used 1=DMA Requests will be generated. A DMA request will be.." "0: DMA is not used 1=DMA Requests will be generated,?"
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hexmask.long.byte 0x8 10.--15. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF. Setting this bit will generate an interrupt if TXINTFLG bit (SPIFLG.9) is set to '1'. 0=No interrupt will be.." "0: No interrupt will be generated upon TXINTFLG..,1: Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x8 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware. Otherwise no interrupt will be generated. 0=Interrupt will not be generated 1=Interrupt will be generated Both Transmitter Empty & Receiver Full interrupts.." "0: Interrupt will not be generated 1=Interrupt will..,?"
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rbitfld.long 0x8 7. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x8 6. "OVRNINTENA,Overrun interrupt enable. An interrupt is to be generated when the RCVR OVRN flag bit (SPIFLG.6) is set by hardware. Otherwise no interrupt will be generated. 0=Overrun interrupt will not be generated 1=Overrun interrupt will be generated" "0: Overrun interrupt will not be generated..,?"
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rbitfld.long 0x8 5. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x8 4. "BITERRENA,Enables interrupt on bit error. 1 =Enables an interrupt on a bit error (BITERR = 1). 0 =No interrupt asserted upon bit error." "0: No interrupt asserted upon bit error,1: Enables an interrupt on a bit error"
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bitfld.long 0x8 3. "DESYNCENA,Enables interrupt on de-synchronized slave. DESYNCENA is used in master mode only. 1 =Enables an interrupt on de-synchronization of the slave (DESYNC = 1). 0 =No interrupt asserted upon de-synchronization error." "0: No interrupt asserted upon de-synchronization..,1: Enables an interrupt on de-synchronization of.."
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bitfld.long 0x8 2. "PARERRENA,Enables interrupt on parity error. 1 =Enables an interrupt on a parity error (PARITYERR = 1). 0 =No interrupt asserted upon parity error." "0: No interrupt asserted upon parity error,1: Enables an interrupt on a parity error"
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bitfld.long 0x8 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out. 1 =Enables an interrupt on a time-out of the ENA signal (TIMEOUT = 1). 0 =No interrupt asserted upon ENA signal time-out." "0: No interrupt asserted upon ENA signal time-out,1: Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x8 0. "DLENERRENA,Data Length Error interrupt Enable. 1 = Enables an interrupt when Data Length Error occurs. 0 = No interrupt is generated upon Data Length Error. A Data Length Error occurs under the following conditions. Master: In a 4-pin with SPIENA mode or.." "0: No interrupt is generated upon Data Length Error,1: Enables an interrupt when Data Length Error occurs"
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line.long 0xC "SPILVL,SPI / MibSPI Interrupt Level Register"
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hexmask.long.tbyte 0xC 10.--31. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0xC 9. "TXINTLVL,Transmit Interrupt Level. 1 =Transmit interrupt is mapped to interrupt line INT1. 0 =Transmit interrupt is mapped to interrupt line INT0." "0: Transmit interrupt is mapped to interrupt line..,1: Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0xC 8. "RXINTLVL,Receive interrupt level. 1 =Receive interrupt is mapped to interrupt line INT1. 0 =Receive interrupt is mapped to interrupt line INT0." "0: Receive interrupt is mapped to interrupt line INT0,1: Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0xC 7. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0xC 6. "OVRNINTLVL,Receive Overrun interrupt level. 1 =Receive Overrun interrupt is mapped to interrupt line INT1. 0 =Receive Overrun interrupt is mapped to interrupt line INT0." "0: Receive Overrun interrupt is mapped to interrupt..,1: Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0xC 5. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0xC 4. "BITERRLVL,Bit error interrupt level. 1 =bit error interrupt is mapped to interrupt line INT1. 0 =bit error interrupt is mapped to interrupt line INT0." "0: bit error interrupt is mapped to interrupt line..,1: bit error interrupt is mapped to interrupt line.."
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bitfld.long 0xC 3. "DESYNCLVL,De-synchronized slave interrupt level. DESYNCLVL is used in master mode only. 1 =An interrupt due to de-synchronization of the slave (DESYNC = 1) is mapped to interrupt line INT1. 0 =An interrupt due to de-synchronization of the slave (DESYNC =.." "0: An interrupt due to de-synchronization of the..,1: An interrupt due to de-synchronization of the.."
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bitfld.long 0xC 2. "PARERRLVL,Parity error interrupt level. 1 =A parity error interrupt (PARITYERR = 1) is mapped to interrupt line INT1. 0 =A parity error interrupt (PARITYERR = 1) is mapped to interrupt line INT0." "0: A parity error interrupt,1: A parity error interrupt"
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bitfld.long 0xC 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level. 1 =An interrupt on a time-out of the ENA signal (TIMEOUT = 1) is mapped to interrupt line INT1. 0 =An interrupt on a time-out of the ENA signal (TIMEOUT = 1) is mapped to interrupt line INT0." "0: An interrupt on a time-out of the ENA signal,1: An interrupt on a time-out of the ENA signal"
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bitfld.long 0xC 0. "DLENERRLVL,Data Length Error interrupt Enable Level. 1 = An interrupt on Data Length Error is mapped to interrupt line INT1. 0 = An interrupt on Data Length Error is mapped to interrupt line INT0." "0: An interrupt on Data Length Error is mapped to..,1: An interrupt on Data Length Error is mapped to.."
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line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
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hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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rbitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process. Software should poll this bit to determine if it can proceed with the configuration of Multibuffer mode registers or Multibuffer RAM handling. Refer to Section 3.10.7 for details.." "0: Multibuffer RAM initialization is complete,1: Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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rbitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag. Serves as an interrupt flag indicating that Transmit Buffer (TXBUF) is empty and a new data can be written to it. This flag is set when a data is copied to the 'Shift Register' either directly or from the.." "0: Transmit Buffer is now full,1: Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag. This flag is set when a word is received and copied into the buffer register (SPIBUF). If RXINTEN is enabled an interrupt is also generated. During emulation mode however a read to the emulation register (SPIEMU).." "0: No new received data pending,1: A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag. The SPI / MibSPI hardware sets this bit when a receive operation completes before the previous character has been read from the receive buffer. The bit indicates that the last received character has been overwritten and.." "0: Overrun condition did not occur,1: Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data. 1 =A bit error occurred. The SPI / MibSPI samples the signal of the transmit pin (master: SIMO slave: SOMI) at the receive point (half clock cycle after transmit point). If the sampled.." "0: No bit error occurred,1: A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device. De-synchronization monitor is active in master mode only. 1 = A slave device is de-synchronized. The master monitors the ENAble signal coming from the slave device and sets the DESYNC flag after the last bit.." "0: No slave de-synchronization detected,1: A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit. 1 =A parity error occurred. If the parity generator is enabled (can be selected individually for each buffer) an even or odd parity bit is added at the end of a data word (see Section 8.23)." "0: No parity error detected,1: A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal. 1 =An ENA signal time-out occurred. The SPI / MibSPI generates a time-out because the slave hasn't responded in time by activating the ENA signal after the chip select signal has been activated." "0: No ENA-signal time-out occurred,1: An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag. 1 = A Data Length Error has occured. 0 = No Data Length Error has occured. This flag can be cleared by one of the following ways. Write a '1' to this bit. Set SPIEN bit to '0'. A Data Length Error occurs under.." "0: No Data Length Error has occured,1: A Data Length Error has occured"
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line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented. it is a mirror of Bit11. Any write to Bit 24 will be reflected on Bit11 and when Bit 24 & Bit 11.."
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hexmask.long.byte 0x14 24.--31. 1. "SOMIFUN,Slave out master in function. Determines whether the SPISOMIx pins are to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISOMIx pin is a GPIO 1=SPISOMIx pin is a SPI / MibSPI functional pin"
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hexmask.long.byte 0x14 16.--23. 1. "SIMOFUN,Slave in master out function. Determines whether the SPISIMOx pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISIMOx pin is a GPIO 1=SPISIMOx pin is a SPI / MibSPI functional pin Note: Generic based bit.."
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hexmask.long.byte 0x14 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function. Determines whether the SPISOMI0 pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISOMI0 pin is a GPIO 1=SPISOMI0 pin is a SPI / MibSPI functional pin Note: Bit 11 or bit 24.." "0: SPISOMI0 pin is a GPIO 1=SPISOMI0 pin is a SPI /..,?"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function. Determines whether the SPISIMO0 pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISIMO0 pin is a GPIO 1=SPISIMO0 pin is a SPI / MibSPI functional pin Note: Bit 10 or bit 16.." "0: SPISIMO0 pin is a GPIO 1=SPISIMO0 pin is a SPI /..,?"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function. Determines whether the SPICLK pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPICLK pin is a GPIO 1=SPICLK pin is a SPI / MibSPI functional pin" "0: SPICLK pin is a GPIO 1=SPICLK pin is a SPI /..,?"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function. Determines whether the SPIENA pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPIENA pin is a GPIO 1=SPIENA pin is a SPI / MibSPI functional pin" "0: SPIENA pin is a GPIO 1=SPIENA pin is a SPI /..,?"
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hexmask.long.byte 0x14 0.--7. 1. "SCSFUN,SPISCS[7:0] function. Determines whether the SPISCSx pins are to be used as a general-purpose I/O pins or as SPI functional pins. If the slave SPISCSx pins are in functional mode and receive an inactive high signal the slave SPI will place it is.."
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line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
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hexmask.long.byte 0x18 24.--31. 1. "SOMIDIR,SPISOMIx direction. Controls the direction of the SPISOMIx pin when it is used as a general-purpose I/O pin. If the SPISOMIx pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISOMIx pin is an.."
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hexmask.long.byte 0x18 16.--23. 1. "SIMODIR,SPISIMOx direction. Controls the direction of the SPISIMOx pin when it is used as a general-purpose I/O pin. If the SPISIMOx pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISIMOx pin is an.."
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hexmask.long.byte 0x18 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction. Controls the direction of the SPISOMI0 pin when it is used as a general-purpose I/O pin. If the SPISOMI0 pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISOMI0 pin is an.." "0: SPISOMI0 pin is an input 1=SPISOMI0 pin is an..,?"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction. Controls the direction of the SPISIMO0 pin when it is used as a general-purpose I/O pin. If the SPISIMO0 pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISIMO0 pin is an.." "0: SPISIMO0 pin is an input 1=SPISIMO0 pin is an..,?"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction. Controls the direction of the SPICLK pin when it is used as a general-purpose I/O pin. In functional mode the I/O direction is determined by the CLKMOD bit. 0=SPICLK pin is an input 1=SPICLK pin is an output" "0: SPICLK pin is an input 1=SPICLK pin is an output,?"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction. Controls the direction of the SPIENA pin when it is used as a general-purpose I/O. If the SPIENA pin is used as a functional pin then the I/O direction is determined by the CLKMOD bit (SPIGCR1.1). 0=SPIENA pin is an input.." "0: SPIENA pin is an input 1=SPIENA pin is an output,?"
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hexmask.long.byte 0x18 0.--7. 1. "SCSDIR,SPISCS[7:0] direction. Controls the direction of the SPISCSx pins when they are used as a general-purpose I/O pin. Each pins could be configured independently from the others If the SPISCSx is used as a SPI functional pin the I/O direction is.."
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rgroup.long 0x1C++0x3
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line.long 0x0 "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
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hexmask.long.byte 0x0 24.--31. 1. "SOMIDIN,SPISOMIx data in. Reflects the value of the SPISOMIx pin. 0=Current value on SPISOMIx pin is logic 0. 1=Current value on SPISOMIx pin is logic 1"
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hexmask.long.byte 0x0 16.--23. 1. "SIMODIN,SPISIMOx data in. Reflects the value of the SPISIMOx pin. 0=Current value on SPISIMOx pin is logic 0. 1=Current value on SPISIMOx pin is logic 1"
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hexmask.long.byte 0x0 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 11. "SOMIDIN0,SPISOMI0 data in. Reflects the value of the SPISOMI0 pin. 0=Current value on SPISOMI0 pin is logic 0. 1=Current value on SPISOMI0 pin is logic 1 Note: Bit 11 or bit 24 can be used to set the direction for pin SOMI0. If a 32 bit write is.." "0: Current value on SPISOMI0 pin is logic 0,1: Current value on SPISOMI0 pin is logic 1 Note:.."
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bitfld.long 0x0 10. "SIMODIN0,SPISIMO0 data in. Reflects the value of the SPISIMO0 pin. 0=Current value on SPISIMO0 pin is logic 0. 1=Current value on SPISIMO0 pin is logic 1. Note: Bit 10 or bit 16 can be used to set the direction for pin SIMO0. If a 32 bit write is.." "0: Current value on SPISIMO0 pin is logic 0,1: Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x0 9. "CLKDIN,Clock data in. Reflects the value of the SPICLK pin. 0=Current value on SPICLK pin is logic 0. 1=Current value on SPICLK pin is logic 1" "0: Current value on SPICLK pin is logic 0,1: Current value on SPICLK pin is logic 1"
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bitfld.long 0x0 8. "ENADIN,SPIENA data in. Reflects the value of the SPIENA pin. 0=Current value on SPIENA pin is logic 0. 1=Current value on SPIENA pin is logic 1" "0: Current value on SPIENA pin is logic 0,1: Current value on SPIENA pin is logic 1"
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hexmask.long.byte 0x0 0.--7. 1. "SCSDIN,SPISCS[7:0] data in. Reflects the value of the SPISCSx pins. 0=Current value on SPISCSx pin is logic 0. 1=Current value on SPISCSx pin is logic 1 Note: Effect of NUM_CS_PINS generic on ChipSelect bits. Actual number of bits implemented in.."
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group.long 0x20++0xF
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line.long 0x0 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
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hexmask.long.byte 0x0 24.--31. 1. "SOMIDOUT,SPISOMIx dataout write. Only active when the SPISOMIx pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISOMIx pin is logic 0."
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hexmask.long.byte 0x0 16.--23. 1. "SIMODOUT,SPISIMOx dataout write. Only active when the SPISIMOx pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISIMOx pin is logic 0."
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hexmask.long.byte 0x0 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 11. "SOMIDOUT0,SPISOMI0 dataout write. Only active when the SPISOMI0 pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISOMI0 pin is logic 0." "0: Current value on SPISOMI0 pin is logic 0,1: Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x0 10. "SIMODOUT0,SPISIMO0 dataout write. Only active when the SPISIMO0 pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISIMO0 pin is logic 0." "0: Current value on SPISIMO0 pin is logic 0,1: Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x0 9. "CLKDOUT,SPICLK dataout write. Only active when the SPICLK pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPICLK pin is logic 0. 1=Current value.." "0: Current value on SPICLK pin is logic 0,1: Current value on SPICLK pin is logic 1"
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bitfld.long 0x0 8. "ENADOUT,SPIENA dataout write. Only active when the SPIENA pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPIENA pin is logic 0. 1=Current value.." "0: Current value on SPIENA pin is logic 0,1: Current value on SPIENA pin is logic 1"
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hexmask.long.byte 0x0 0.--7. 1. "SCSDOUT,SPISCS[7:0] dataout write. Only active when the SPISCSx pins are configured as a general-purpose I/O pins and configured as an output pins. The value of these bit indicates the value sent to the pins. 0=Current value on SPISCSx pin is logic 0."
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line.long 0x4 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
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hexmask.long.byte 0x4 24.--31. 1. "SOMISET,SPISOMIx dataout set. Only active when the SPISOMIx pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISOMIDOUTx bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.."
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hexmask.long.byte 0x4 16.--23. 1. "SIMOSET,SPISIMOx dataout set. Only active when the SPISIMOx pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISIMODOUTx bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.."
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hexmask.long.byte 0x4 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 11. "SOMISET0,SPISOMI0 dataout set. Only active when the SPISOMI0 pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISOMIDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.." "0: Current value on SOMIDOUT0 is 0,1: Current value on SOMIDOUT0 is 1"
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bitfld.long 0x4 10. "SIMOSET0,SPISIMO0 dataout set. Only active when the SPISIMO0 pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISIMODOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.." "0: Current value on SIMODOUT0 is 0,1: Current value on SIMODOUT0 is 1"
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bitfld.long 0x4 9. "CLKSET,SPICLK dataout set. Only active when the SPICLK pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding CLKDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on SPICLK pin if it.." "0: Current value on CLKDOUT pin is logic 0,1: Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x4 8. "ENASET,SPIENA dataout set. Only active when the SPIENA pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding ENABLEDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on SPIENA pin if.." "0: Current value on ENADOUT is 0,1: Current value on ENADOUT is 1"
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hexmask.long.byte 0x4 0.--7. 1. "SCSSET,SPISCS[7:0] dataout set. Only active when the SPISCSx pins are configured as a general-purpose output pins. A value of '1' written to these bits set the corresponding SCSDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on SPISCSx.."
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line.long 0x8 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
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hexmask.long.byte 0x8 24.--31. 1. "SOMICLR,SPISOMIx dataout clear. Only active when the SPISOMIx pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SPISOMIDOUTx bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.."
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hexmask.long.byte 0x8 16.--23. 1. "SIMOCLR,SPISIMOx dataout clear. Only active when the SPISIMOx pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SPISIMODOUTx bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.."
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hexmask.long.byte 0x8 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 11. "SOMICLR0,SPISOMI0 dataout clear. Only active when the SPISOMI0 pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SPISOMIDOUT bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.." "0: Current value on SOMIDOUT0 is 0,1: Current value on SOMIDOUT0 is 1"
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bitfld.long 0x8 10. "SIMOCLR0,SPISIMO0 dataout clear. Only active when the SPISIMO0 pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SIMODOUT0 bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.." "0: Current value on SIMODOUT0 is 0,1: Current value on SIMODOUT0 is 1"
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bitfld.long 0x8 9. "CLKCLR,SPICLK dataout clear. Only active when the SPICLK pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding CLKDOUT bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on SPICLK pin if.." "0: Current value on CLKDOUT is 0,1: Current value on CLKDOUT is 1"
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bitfld.long 0x8 8. "ENACLR,SPIENA dataout clear. Only active when the SPIENA pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding ENABLEDOUT bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on SPIENA pin.." "0: Current value on ENADOUT is 0,1: Current value on ENADOUT is 1"
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hexmask.long.byte 0x8 0.--7. 1. "SCSCLR,SPISCS[7:0] dataout clear. Only active when the SPISCSx pins are configured as a general-purpose output pins. A value of '1' written to this bit clears the corresponding SCSDOUT bit to '0.. Write: 0= Has no effect 1= Logic 0 placed on.."
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line.long 0xC "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
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hexmask.long.byte 0xC 24.--31. 1. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met. SOMIDIRx = 1 (SPISOMI0 pin configured in GPIO mode as output pin) SOMIDOUTx = 1 0 = Output value on SPISOMIx pin is logic '1' 1 =.."
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hexmask.long.byte 0xC 16.--23. 1. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met. SIMODIRx = 1 (SPISIMOx pin configured in GPIO mode as output pin) SIMODOUTx = 1 0 = Output value on SPISIMOx pin is logic '1' 1.."
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hexmask.long.byte 0xC 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0xC 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met. SOMIDIR0 = 1 (SPISOMI0 pin configured in GPIO mode as output pin) SOMIDOUT0 = 1 0 = Output value on SPISOMI0 pin is logic '1' 1.." "0: Output value on SPISOMI0 pin is logic '1',1: Output pin SPISOMI0 is Tri-stated Note: Bit 11.."
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bitfld.long 0xC 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met. SIMODIR0 = 1 (SPISIMO pin configured in GPIO mode as output pin) SIMODOUT0 = 1 0 = Output value on SPISIMO0 pin is logic '1' 1.." "0: Output value on SPISIMO0 pin is logic '1',1: Output pin SPISIMO0 is Tri-stated Note: Bit 10.."
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bitfld.long 0xC 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met. CLKDIR = 1 (SPICLK pin configured in GPIO mode as output pin) CLKDOUT = 1 0 = Output value on SPICLK pin is logic '1' 1 = Output pin.." "0: Output value on SPICLK pin is logic '1',1: Output pin SPICLK is Tri-stated"
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bitfld.long 0xC 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met. ENABLEDIR = 1 (SPIENA pin configured in GPIO mode as output pin) ENABLEDOUT = 1 0 = Output value on SPIENA pin is logic '1' 1 =.." "0: Output value on SPIENA pin is logic '1',1: Output pin SPIENA is Tri-stated"
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hexmask.long.byte 0xC 0.--7. 1. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met. SCSDIRx = 1 (SPISCS pin configured in GPIO mode as output pin) SCSDOUTx = 1 0 = Output value on SPISCSx pin is logic '1' 1 =.."
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group.long 0x38++0xB
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line.long 0x0 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI. It is only accessible in compatibility mode."
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hexmask.long.word 0x0 16.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data. When written these bits will be copied to the Shift Register if it is empty. If the Shift Register is not empty the TXBUF will hold the written values. SPIEN (SPICGR1.24) must be set to 1 before this register can be.."
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line.long 0x4 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned."
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rbitfld.long 0x4 29.--31. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 28. "CSHOLD,Chip select hold mode. In SPI or compatibility mode MibSPI the CSHOLD bit is supported in master mode only. In slave mode this bit is ignored. CSHOLD defines the behavior of the chip select line at the end of a data transfer. 1 =The chip select.." "0: The chip select signal is deactivated at the end..,1: The chip select signal is held active at the end.."
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rbitfld.long 0x4 27. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 26. "WDEL,Enable the delay counter at the end of the current transaction. WDELAY bit is supported in Master mode only. In Slave mode this bit will be ignored. 1 = After a transaction WDELAY of the corresponding data format will be loaded into the delay.." "0: No delay will be inserted,1: After a transaction"
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bitfld.long 0x4 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x4 16.--23. 1. "CSNR,Chip select number. CSNR defines the chip select that shall be activated during the data transfer. The value of CSNR[7:0] will be driven on SPISCS[7:0] lines during the transfer. Note: Effect of NUM_CS_PINS generic on CSNR bits. Actual number of.."
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hexmask.long.word 0x4 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data. When written these bits will be copied to the Shift Register if it is empty. If the Shift Register is not empty the TXBUF will hold the written values. SPIEN must be set to 1 before this register can be written to."
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line.long 0x8 "SPIBUF,SPI / MibSPI Receive Buffer Register"
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bitfld.long 0x8 31. "RXEMPTY,Receive data buffer empty. When host reads the SPIBUF field or the whole SPIBUF register this will automatically set the RXEMPTY flag. When a data transfer is completed the received data is copied into SPIBUF the RXEMPTY flag is cleared. 1 =No.." "0: A new Data is received and copied into SPIBUF..,1: No data received since last reading of SPIBUF.."
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bitfld.long 0x8 30. "RXOVR,Receive data buffer overrun. When a data transfer is completed and the received data is copied into the RXBUF while it is already full RXOVR is set. Refer to Figure 1 for a view of internal logic diagram. An Overrun always occurs to the RXBUF and.." "0: No receive data overrun condition occurred since..,1: A receive data overrun condition occurred since.."
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rbitfld.long 0x8 29. "TXFULL,Transmit data buffer full. This flag is a read-only flag. Writing into SPIDAT0 or SPIDAT1 field while TX Shift Register is full will automatically set the TXFULL flag. Once the data is copied to the Shift Register the TXFULL flag will be cleared." "0: Transmit buffer is empty,1: Transmit buffer is full"
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bitfld.long 0x8 28. "BITERR,Mismatch of internal transmit data and transmitted data. 1 =A bit error occurred. The SPI / MibSPI samples the signal of the transmit pin (master: SIMO slave: SOMI) at the receive point (half clock cycle after transmit point). If the sampled.." "0: No bit error occurred,1: A bit error occurred"
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bitfld.long 0x8 27. "DESYNC,De-synchronization of slave device. De-synchronization monitor is active in master mode only. 1 =A slave device is de-synchronized. The master monitors the ENA signal coming from the slave device and sets the DESYNC flag if ENA is deactivated.." "0: No slave de-synchronization detected,1: A slave device is de-synchronized"
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bitfld.long 0x8 26. "PARITYERR,Calculated parity differs from received parity bit. 1 =A parity error occurred. If the parity generator is enabled (can be selected individually for each buffer) an even or odd parity bit is added at the end of a data word (see Section 8.23)." "0: No parity error detected,1: A parity error occurred"
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bitfld.long 0x8 25. "TIMEOUT,Time-out due to non-activation of ENA pin. 1 =An ENA signal time-out occurred. The SPI / MibSPI generates a time-out because the slave hasn't responded in time by activating the ENA signal after the chip select signal has been activated. If a.." "0: No ENA-pin time-out occurred,1: An ENA signal time-out occurred"
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bitfld.long 0x8 24. "DLENERR,Data Length Error flag. 1 = A Data Length Error has occured. 0 = No Data Length Error has occured. This flag is cleared to '0' when RXDATA portion of the SPIBUF register is read." "0: No Data Length Error has occured,1: A Data Length Error has occured"
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hexmask.long.byte 0x8 16.--23. 1. "LCSNR,Last Chip select number. LCSNR in the status field is a copy of CSNR in the corresponding control field. It defines the chip select that has been activated during the last data transfer from the corresponding buffer. This is the copy of CSNR bits.."
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hexmask.long.word 0x8 0.--15. 1. "RXDATA,SPI Receive Data. This is the received data transferred from the Receive Shift-Register at the end of a transfer completion. Irrespective of the programmed character length & the direction of shifting the received data is stored right-justified.."
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rgroup.long 0x44++0x3
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line.long 0x0 "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only. Read operation on this register under any mode will not have any impact on the status of this or any other registers."
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bitfld.long 0x0 31. "RXEMPTY,Receive data buffer empty. 1 = No data received since last reading of SPIBUF register. 0 = A new Data is received and copied into SPIBUF field." "0: A new Data is received and copied into SPIBUF..,1: No data received since last reading of SPIBUF.."
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bitfld.long 0x0 30. "RXOVR,Receive data buffer overrun. 1 =A receive data overrun condition occurred since last time reading the data field. 0 =No receive data overrun condition occurred since last time reading the data field." "0: No receive data overrun condition occurred since..,1: A receive data overrun condition occurred since.."
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bitfld.long 0x0 29. "TXFULL,Transmit data buffer full. 1 =Transmit buffer is full SPIDAT0/SPIDAT1 is not ready to accept a new data. 0 =Transmit buffer is empty SPIDAT0/SPIDAT1 is ready to accept a new data." "0: Transmit buffer is empty,1: Transmit buffer is full"
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bitfld.long 0x0 28. "BITERR,Mismatch of internal transmit data and transmitted data. 1 =A bit error occurred. The SPI / MibSPI samples the signal of the transmit pin (master: SIMO slave: SOMI) at the receive point (half clock cycle after transmit point). If the sampled.." "0: No bit error occurred,1: A bit error occurred"
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bitfld.long 0x0 27. "DESYNC,De-synchronization of slave device. De-synchronization monitor is active in master mode only. 1 =A slave device is de-synchronized. The master monitors the ENA signal coming from the slave device and sets the DESYNC flag if ENA is deactivated.." "0: No slave de-synchronization detected,1: A slave device is de-synchronized"
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bitfld.long 0x0 26. "PARITYERR,Calculated parity differs from received parity bit. 1 =A parity error occurred. If the parity generator is enabled (can be selected individually for each buffer) an even or odd parity bit is added at the end of a data word (see Section 8.23)." "0: No parity error detected,1: A parity error occurred"
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bitfld.long 0x0 25. "TIMEOUT,Time-out due to non-activation of ENA pin. 1 =An ENA signal time-out occurred. The SPI / MibSPI generates a time-out because the slave hasn't responded in time by activating the ENA signal after the chip select signal has been activated. If a.." "0: No ENA-pin time-out occurred,1: An ENA signal time-out occurred"
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bitfld.long 0x0 24. "DLENERR,Data Length Error flag. 1 = A Data Length Error has occured. 0 = No Data Length Error has occured." "0: No Data Length Error has occured,1: A Data Length Error has occured"
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hexmask.long.byte 0x0 16.--23. 1. "LCSNR,Last Chip select number. LCSNR in the status field is a copy of CSNR in the corresponding control field. It defines the chip select that has been activated during the last data transfer from the corresponding buffer. This is the copy of CSNR bits.."
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,SPI Receive Data. SPI / MibSPI emulation is a mirror of the SPIBUF register. The only difference between SPIEMU and SPIBUF is that a read from SPIEMU does not clear any of the status flags."
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group.long 0x48++0x7
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line.long 0x0 "SPIDELAY,SPI / MibSPI Delay Register"
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hexmask.long.byte 0x0 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay. C2TDELAY is used in master mode only. It defines a setup time for the slave device that delays the data transmission from the chip select active edge by a multiple of VBUSPCLK cycles."
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hexmask.long.byte 0x0 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay. T2CDELAY is used in master mode only. It defines a hold time for the slave device that delays the chip select deactivation by a multiple of VBUSPCLK cycles after the last bit is transferred. T2CDELAY.."
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hexmask.long.byte 0x0 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out. T2EDELAY is used in master mode only. It defines a time-out value as a multiple of SPI clock before the ENAble signal has to become inactive and after the CS becomes inactive. The SPI clock.."
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hexmask.long.byte 0x0 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response. C2EDELAY defines the maximum time between the SPI /.."
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line.long 0x4 "SPIDEF,SPI / MibSPI Default Chip select Register"
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hexmask.long.tbyte 0x4 8.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x4 0.--7. 1. "CSDEF0,Chip select default pattern. Master mode behavior. The CSDEFx bits are output to the chip select pins when no transmission are currently performed. It allows the user to set a chip select pattern which deselects all the SPI slaves. 1 =If CSDEFx is.."
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repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
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group.long ($2+0x50)++0x3
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line.long 0x0 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
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hexmask.long.byte 0x0 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3). Idle time that will be applied at the end of the current transmission if the bit WDEL is set in the current buffer. The delay to be applied is equal to: WDELAY * PVBUSPCLK + 2 *.."
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bitfld.long 0x0 23. "PARPOL,Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. It can be used for data format x (x= 0 1 2 3). 1 =An odd parity flag is added at the end of the transmit data stream. 0 =An even parity flag is added at the end of the.." "0: An even parity flag is added at the end of the..,1: An odd parity flag is added at the end of the.."
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bitfld.long 0x0 22. "PARITYENA,Parity enable for data format x. 1= A parity is transmitted at the end of each transmit data stream. At the end of a transfer the parity generator compares the received parity bit with the locally calculated parity flag. If the parity bits do.." "0: No parity generation/ verification is performed..,1: A parity is transmitted at the end of each.."
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bitfld.long 0x0 21. "WAITENA,Master waits for ENA signal from slave for data format x. WAITENA is considered in master mode only. In slave mode this bit has no meaning. WAITENA enables a flexible SPI network where slaves with ENA signal and slaves without ENA signal can be.." "0: The SPI / MibSPI does not wait for the ENA..,1: Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x0 20. "SHIFTDIR,Shift direction for data format x. With bit SHIFTDIRx the shift direction for data format x (x=0 1 2 3) can be selected. 1 =Data format x shift direction: Least significant bit is shifted out first. 0 =Data format x shift direction: Most.." "0: Data format x shift direction: Most significant..,1: Data format x shift direction: Least significant.."
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bitfld.long 0x0 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x. This bit controls the I/O function of SOMI/SIMO lines for a specific requirement where in the case of Master mode TX pin - SIMO will act as an RX pin and in the case of Slave mode RX pin.." "0: Normal Full Duplex transfer,1: If MASTER = '1'"
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bitfld.long 0x0 18. "DISCSTIMERS,Disable Chipselect Timers for this format register. The C2TDELAY & T2CDELAY timers are by default enabled for all the Data Format registers. Using this bit these timers can be disabled for particular Data Format if not required. When a.." "0: Both C2TDELAY & T2CDELAY counts are inserted for..,1: No C2TDELAY or T2CDELAY is inserted in the.."
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bitfld.long 0x0 17. "POLARITY,SPI data format x clock polarity. POLARITYx defines the clock polarity of data format x. POLARITYx can be modified in privilege mode only. 1 =If POLARITYx is set to '1' the SPI clock signal is high-inactive i.e. before and after data.." "0: If POLARITYx is set to '0' the SPI clock signal..,1: If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x0 16. "PHASE,SPI Data format x clock delay. PHASEx defines the clock delay of data format x. PHASEx can be modified in privilege mode only. 1 =If PHASEx is set to '1' the SPI clock signal is delayed by a half SPI clock cycle versus the transmit / receive.." "0: If PHASEx is set to '0' the SPI clock signal is..,1: If PHASEx is set to '1' the SPI clock signal is.."
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hexmask.long.byte 0x0 8.--15. 1. "PRESCALE,SPI data format x prescaler. PRESCALEx can be modified in privilege mode only. PRESCALEx determines the bit transfer rate of data format x if the SPI is the network master. PRESCALEx is directly derived from VBUSPCLK. If the SPI / MibSPI is.."
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rbitfld.long 0x0 5.--7. "NU,Reserved. Reads return '0' and writes have no effect." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--4. 1. "CHARLEN,SPI data format x data word length. CHARLENx defines the word length of data format x. Legal values are 0x02 (data word length = 2 bit) to 0x10 (data word length = 16). Illegal values such as 0x00 or 0x1F are not detected and their effect is.."
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rgroup.long 0x60++0x7
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line.long 0x0 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
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hexmask.long 0x0 6.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 1.--5. 1. "INTVECT0,Interrupt vector for interrupt line INT0. INTVECT0 returns the vector of the pending interrupt at interrupt line INT0. If more than one interrupts are pending INTVECT0 always references the highest priority interrupt source first. The vectors.."
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bitfld.long 0x0 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field. 1 =The interrupt type is a 'transfer suspended' interrupt. I.e." "0: The interrupt type is a 'transfer finished'..,1: The interrupt type is a 'transfer suspended'.."
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line.long 0x4 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
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hexmask.long 0x4 6.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x4 1.--5. 1. "INTVECT1,Interrupt vector for interrupt line INT1. INTVECT1 returns the vector of the pending interrupt at interrupt line INT0. If more than one interrupt is pending INTVECT1 always references the highest priority interrupt source first. The vectors.."
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bitfld.long 0x4 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field. 1 =The interrupt type is a 'transfer suspended' interrupt. I.e." "0: The interrupt type is a 'transfer finished'..,1: The interrupt type is a 'transfer suspended'.."
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group.long 0x68++0x1B
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line.long 0x0 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
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hexmask.long.byte 0x0 24.--31. 1. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select."
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hexmask.long.byte 0x0 16.--23. 1. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select."
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hexmask.long.byte 0x0 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select. Note: Bit 11 or bit 24 can be used to control the slew rate for SPISOMI0. If a 32 bit write is performed bit 11 will have priority over bit 24." "0: Normal Buffer Select,1: Slow Buffer Select"
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bitfld.long 0x0 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select. Note: Bit 10 or bit 16 can be used to control the slew rate for SPISIMO0. If a 32 bit write is performed bit 10 will have priority over bit 16." "0: Normal Buffer Select,1: Slow Buffer Select"
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bitfld.long 0x0 9. "CLKSRS,This bit controls the slew rate for SPICLK pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select." "0: Normal Buffer Select,1: Slow Buffer Select"
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bitfld.long 0x0 8. "ENASRS,This bit controls the slew rate for SPIENA pin. 0 =Fast Buffer Select. 1 =Slow Buffer Select." "0: Fast Buffer Select,1: Slow Buffer Select"
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hexmask.long.byte 0x0 0.--7. 1. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select. Note: Effect of NUM_CS_PINS generic on ChipSelect bits. Actual number of bits implemented in SCSSRS[7:0] will depend.."
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line.long 0x4 "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
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rbitfld.long 0x4 31. "NU4,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3. Controls whether the PMODE3 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE3.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only. If MODULO MODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 3.000 = Normal single dataline mode - Default (PMODE should be set to '00') 001 = 2-data line.." "0: Normal single dataline mode,?,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000') 10 =.." "0: normal operation / 1-data line,?,2: data line mode,?"
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rbitfld.long 0x4 23. "NU3,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2. Controls whether the PMODE2 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE2.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2. Determines the Polarity of the SPICLK in Modulo mode only. If MMODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2. 000 = 1-data line Mode - Default (PMODE should be set to '00') 001 = 2-data line Mode (PMODE.." "?,1: data line Mode,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000')10 = 4-data.." "0: normal operation / 1-data line,?,2: data line mode,?"
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rbitfld.long 0x4 15. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1. Controls whether the PMODE1 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE1.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1. Determines the Polarity of the SPICLK in Modulo mode only. If MMODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1. 000 = 1-data line Mode - Default (PMODE should be set to '00') 001 = 2-data line Mode (PMODE.." "?,1: data line Mode,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000') 10 =.." "0: normal operation / 1-data line,?,2: data line mode,?"
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rbitfld.long 0x4 7. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0. Controls whether the PMODE0 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE0.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0. Determines the Polarity of the SPICLK in Modulo mode only. If MMODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0. 000 = 1-data line Mode - Default (PMODE should be set to '00') 001 = 2-data line Mode (PMODE.." "?,1: data line Mode,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000') 10 =.." "0: normal operation / 1-data line,?,2: data line mode,?"
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line.long 0x8 "MIBSPIE,MibSPI Enable Register"
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hexmask.long.word 0x8 17.--31. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 16. "RXRAMACCESS,Receive RAM Access control Bit. During normal operating mode of MibSPI the Receive Data/Status portion of Multibuffer RAM is read-only. To enable testing of Data Integrity checks of Receive RAM a special read/write access control is.." "0: The RX portion of Multibuffer RAM is not..,1: The whole of Multibuffer RAM is fully accessible.."
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hexmask.long.byte 0x8 12.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x8 8.--11. 1. "EXTENDED_BUF_ENA,Enables the support for 256 buffers. By default MibSPI supports up to 128 buffers for both TX and RX. It is also possible to extend the support to 256 buffers as a parameterized implementation. This field can be used to enable/disable.."
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hexmask.long.byte 0x8 1.--7. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 0. "MSPIENA,Multibuffer mode Enable. After power-up or reset MSPIENA remains cleared which means that the MibSPI runs in compatibility mode by default. If Multibuffer mode is desired this register should be configured first after configuring the SPIGCR0.." "0: The MibSPI runs in compatibility mode,1: The MibSPI is configured to run in MibSPI mode"
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line.long 0xC "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
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hexmask.long.word 0xC 16.--31. 1. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished. Write: 1 = Enables the 'The Transfer group x completed ' interrupt Interrupt gets generated when Transfer Group x gets completed. 0 = Has no effect. Read: 1 = 'The Transfer.."
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hexmask.long.word 0xC 0.--15. 1. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write: 1 = Enables the 'The Transfer group x suspended ' interrupt Interrupt gets generated when Transfer Group x gets suspended. 0 = Has no effect. Read: 1 = 'The Transfer.."
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line.long 0x10 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
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hexmask.long.word 0x10 16.--31. 1. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished. Write: 1 = Disables the 'The Transfer group x completed ' interrupt Interrupt does not get generated when Transfer Group x gets completed. 0 = Has no effect. Read: 1 =.."
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hexmask.long.word 0x10 0.--15. 1. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write: 1 = Disables the 'The Transfer group x suspended ' interrupt Interrupt does not get generated when Transfer Group x gets suspended. 0 = Has no effect. Read: 1 =.."
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line.long 0x14 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
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hexmask.long.word 0x14 16.--31. 1. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write: 1 = Sets the 'The Transfer group x completed ' interrupt to line INT1 0 = Has no effect. Read: 1 = 'The Transfer group x completed ' interrupt is set to line INT1 0 =.."
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hexmask.long.word 0x14 0.--15. 1. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write: 1 = Sets the 'The Transfer group x suspended ' interrupt to line INT1 0 = Has no effect. Read: 1 = 'The Transfer group x suspended ' interrupt is set to line INT1 0 =.."
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line.long 0x18 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
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hexmask.long.word 0x18 16.--31. 1. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write: 1 = Sets the 'The Transfer group x completed ' interrupt to line INT0 0 = Has no effect. Read: 1 = 'The Transfer group x completed ' interrupt is set to line INT1 0 =.."
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hexmask.long.word 0x18 0.--15. 1. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write: 1 = Sets the 'The Transfer group x suspended ' interrupt to line INT0 0 = Has no effect. Read: 1 = 'The Transfer group x suspended ' interrupt is set to line INT1 0 =.."
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rgroup.long 0x84++0x3
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line.long 0x0 "TGINTFLAG,Transfer Group Interrupt Flag Register"
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hexmask.long.word 0x0 16.--31. 1. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt. Read: 1 =A 'transfer finished' interrupt from transfer group x occurred. No matter whether the interrupt is enabled or disabled (INTENRDYx = don't care) or whether the.."
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hexmask.long.word 0x0 0.--15. 1. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt. Read: 1 =A 'transfer suspended' interrupt from transfer group x occurred. No matter whether the interrupt is enabled or disabled (INTENSUSx = don't care) or whether the.."
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group.long 0x90++0x27
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line.long 0x0 "TICKCNT,Tick Count Register"
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bitfld.long 0x0 31. "TICKENA,Tick counter enable. 1 =The MibSPI internal tick counter is enabled and is clocked by the clock source selected by CLKCTRL[1:0]. When the tick counter is enabled it starts down-counting from its current value. When TICKENA goes from '0' to.." "0: The MibSPI internal tick counter is disabled,1: The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x0 30. "RELOAD,Re-load tick counter. RELOAD is a set-only bit i.e. writing a '1' to it automatically reloads the Tick Counter with the value stored in TICKVALUE. Reading RELOAD always returns a '0'. Note: When the tick counter is reloaded by the RELOAD.." "0,1"
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bitfld.long 0x0 28.--29. "CLKCTRL,Tick counter clock source control. CLKCTRL[1:0] defines the clock source that is used to clock the MibSPI internal tick counter.CLKCTRL[1:0] Description 00b SPICLK of Data word format 0 is selected as clock source of tick counter 01b SPICLK of.." "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0 0.--15. 1. "TICKVALUE,Initial value for tick counter. TICKVALUE stores the initial value for the tick counter. The tick counter is loaded with TICKVALUE every time an under-flow condition occurs and every time the RELOAD flag is set by the host"
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line.long 0x4 "LTGPEND,Last Transfer Group End Pointer"
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rbitfld.long 0x4 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 24.--28. 1. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer. Read-Only field indicating the current Transfer Group that is being serviced. This field can generally be used for code debug purpose. Read Value:TG IN SERVICE[4:0] Description 00000b.."
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hexmask.long.byte 0x4 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x4 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART). The transfer group ends at the buffer one before the next.."
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hexmask.long.byte 0x4 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16. Depending on the implementation the number of transfer groups and hence the number of transfer group control register may vary. Each.."
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bitfld.long 0x8 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x8 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x8 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x8 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x8 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x8 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x8 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x8 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x8 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0xC 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0xC 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0xC 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0xC 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0xC 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0xC 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0xC 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0xC 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0xC 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x10 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x10 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x10 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x10 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x10 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x14 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x14 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x14 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x14 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x14 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x18 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x18 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x18 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x18 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x18 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x1C 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x1C 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x1C 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x1C 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x1C 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x20 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x20 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x20 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x20 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x20 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x24 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x24 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x24 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x24 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x24 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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group.long 0xD8++0x13
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line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x0 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x0 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x0 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x0 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x0 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x0 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x0 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x0 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x0 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x0 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x4 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x4 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x4 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x4 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x4 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x4 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x4 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x4 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x4 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x4 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x4 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x8 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x8 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x8 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x8 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x8 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x8 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x8 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x8 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x8 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x8 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x8 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0xC 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0xC 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0xC 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0xC 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0xC 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0xC 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0xC 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0xC 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0xC 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0xC 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0xC 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x10 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x10 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x10 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x10 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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repeat 4. (list 0x0 0x1 0x3 0x4)(list 0x0 0x4 0xC 0x10)
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group.long ($2+0xF8)++0x3
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line.long 0x0 "ICOUNT$1,MibSPI DMAxCOUNT"
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hexmask.long.word 0x0 16.--31. 1. "ICOUNT,Initial Number of DMA transfers. ICOUNTx is used to preset the transfer counter COUNTx. Every time COUNTx hits zero it is reloaded with ICOUNTx. The real number of transfer equals ICOUNTx plus one. If ONESHOTx is set ICOUNTx defines the number of.."
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hexmask.long.word 0x0 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set. Since the real COUNTx is always ICLOUNTx +1 the 17th bit of.."
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repeat.end
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rgroup.word 0x100++0x1
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line.word 0x0 "ICOUNT2,MibSPI DMAxCOUNT"
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hexmask.word 0x0 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set. Since the real COUNTx is always ICLOUNTx +1 the 17th bit of.."
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group.long 0x118++0x3
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line.long 0x0 "DMACNTLEN,DMA LARGE COUNT register"
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hexmask.long 0x0 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 0. "LARGE_COUNT,0: Writes to the DMAxCTRL register will modify the ICOUNT value. Reading ICOUNT and COUNT can be done from the DMAxCTRL register. The DMAxCOUNT register should not be used since any write to this register will be overwritten by a subsequent.." "0: Writes to the DMAxCTRL register will modify the..,1: Writes to the DMAxCTRL register will not modify.."
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group.long 0x120++0x3
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line.long 0x0 "PAR_ECC_CTRL,Parity/ECC Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "NU4,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 24.--27. 1. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM. This signal can be used to generate interrupt if required. Write: 0101 -.."
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hexmask.long.byte 0x0 20.--23. 1. "NU3,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 16.--19. 1. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not. Write: 0101 - Disable correction of SBE detected by the SECDED block 1010 - Enable correction of SBE.."
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hexmask.long.byte 0x0 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 8. "PTESTEN,Parity/ECC memory Test Enable. This bit maps the parity/ecc bits corresponding to Multibuffer RAM locations into the peripheral RAM frame to make them accessible by the CPU. User and privilege mode (read): 0 = parity/ecc bits are not memory.." "0: disable memory mapping of Parity/ECC locations,1: enable memory mapping of Parity/ECC locations"
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hexmask.long.byte 0x0 4.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 0.--3. 1. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection. Write: 0101: Disables Parity/ECC Error Detection Logic(default) Others : Enables Parity/ECC Error Detection Logic. Read: Returns the current value of this field"
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rgroup.long 0x124++0xF
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line.long 0x0 "PAR_ECC_STAT,Parity/ECC Status Register"
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hexmask.long.tbyte 0x0 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 9. "SBE_FLG1,Single Bit Error in RXRAM. This flag indicates if a single bit ECC Error ocurred on reading RXRAM Read: 0 = No error occured. 1 = Single bit error is detected in RXRAM and the address is captured in SBERRADDR1 register. Write: 0 = No effect. 1 =.." "0: No effect,1: Clears the bit"
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bitfld.long 0x0 8. "SBE_FLG0,Single Bit Error in TXRAM. This flag indicates if a single bit ECC Error ocurred on reading TXRAM Read: 0 = No error occured. 1 = Single bit error is detected in TXRAM and the address is captured in SBERRADDR0 register. Write: 0 = No effect. 1 =.." "0: No effect,1: Clears the bit"
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hexmask.long.byte 0x0 2.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read: 0 = No error occured. 1 = Error detected and the address is captured in.." "0: No effect,1: Clears the bit"
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bitfld.long 0x0 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read: 0 = No error occured. 1 = Error detected and the address is captured in UERRADDR0 register." "0: No effect,1: Clears the bit"
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line.long 0x4 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
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hexmask.long.tbyte 0x4 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0x4 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM. The address captured is byte alligned when RAM.."
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line.long 0x8 "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
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hexmask.long.tbyte 0x8 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0x8 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM. The TXRAM can be read either by CPU or by the MibSPI Sequencer FSM logic for.."
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line.long 0xC "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
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hexmask.long.tbyte 0xC 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0xC 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured. This address value will show only the offset address of the RAM location in the Multibuffer RAM address space. Refer to the device Spec for the actual absolute address.."
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group.long 0x134++0xF
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line.long 0x0 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog ones in this test mode. In addition it contains control bits to induce some of the.."
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hexmask.long.byte 0x0 25.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode. Read 1 = A comparison between the internal CSNR field and the analog looped back value of SPISCS[7:0] pins failed. A stuck-at fault is detected.." "0: No effect,1: Clear this Flag bit"
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rbitfld.long 0x0 21.--23. "NU3,Reserved. Reads return '0' and writes have no effect." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode. 1 = The value of incoming data from the loopback Transmit pin is flipped. 0 = No affect on BIT ERROR." "0: No affect on BIT ERROR,1: The value of incoming data from the loopback.."
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bitfld.long 0x0 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode. 1 = Forces the incoming SPIENA pin (if functional) to remain '0' even after the transfer complete. This forcing will be retained until the Kernel reaches IDLE state. 0 = No.." "0: No affect on DESYNC Error,1: Forces the incoming SPIENA pin"
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bitfld.long 0x0 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode. 1 = Flips the Parity Polarity signal being used for transmit parity generation logic 0 = No affect on Parity Error" "0: No affect on Parity Error,1: Flips the Parity Polarity signal being used for.."
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bitfld.long 0x0 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode. 1 = Forces the incoming SPIENA pin (if functional) to remain '1' when transmission is initiated. The forcing will be retained until the Kernel reaches IDLE state. 0 = No.." "0: No affect on TIMEOUT Error,1: Forces the incoming SPIENA pin"
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bitfld.long 0x0 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode. 1 = When in Master mode forces the SPIENA pin(if functional) to '1' when the module starts Shifting the data. When in Slave mode forces the incoming SPISCS pin(if.." "0: No affect on Data Length Error,1: When in Master mode"
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hexmask.long.byte 0x0 12.--15. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 8.--11. 1. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads. Write access only in Privileged mode. Write: 1010 = I/O DFT is enabled All other values = I/O DFT is disabled Read: 1010 = I/O DFT is enabled All other values = I/O DFT is.."
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rbitfld.long 0x0 6.--7. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1,2,3"
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bitfld.long 0x0 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin. The value in this field is decoded to find out the ChipSelect pin on which to inject an error. During the analog loopback of IO Loopback Test mode if CTRL SCS PIN ERR bit is set to '1' then the chipselect.." "0: Select SPISCS[0] for injecting error 001,?,?,?,?,?,?,?"
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bitfld.long 0x0 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins. Individual pins of SPISCS[7:0] can be choosen using ERR SCS PIN. 1 = Enable the error inducing logic to the SPISCS pins. 0 = Disable the error inducing logic." "0: Disable the error inducing logic,1: Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x0 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital). User and Privileged mode reads. Write access only in Privileged mode. Write/Read : 1 = Analog loopback is enabled in module I/O DFT mode when IOLPBKTSTENA = 1010) 0 = Digital loopback is enabled in.." "0: Digital loopback is enabled in module I/O DFT..,1: Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x0 0. "RXPENA,Module Analog loopback through Receive Pin Enable. User and Privileged mode reads. Write only in privileged mode: Write/Read : 1 = Analog loopback through receive pin 0 = Analog loopback through transmit pin. This bit is valid only when LPBK TYPE.." "0: Analog loopback through transmit pin,1: Analog loopback through receive pin"
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line.long 0x4 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This is an extension of.."
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hexmask.long.byte 0x4 27.--31. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x4 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1. EPRESCALE_FMT1 can be modified in privilege mode only. EPRESCALE_FMT1 determines the bit transfer rate of Data Format 1 if the SPI/MibSPI is the network master. If the SPI / MibSPI is configured as.."
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hexmask.long.byte 0x4 11.--15. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x4 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only. EPRESCALE_FMT0 determines the bit transfer rate of Data Format 0 if the SPI is the network master. If the SPI / MibSPI is configured as slave this field DOES NOT NEED to be.."
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line.long 0x8 "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This register is an.."
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hexmask.long.byte 0x8 27.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x8 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only. EPRESCALE_FMT3 determines the bit transfer rate of Data Format 3 if the SPI is the network master. If the SPI / MibSPI is configured as slave this field DOES NOT NEED to be.."
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hexmask.long.byte 0x8 11.--15. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x8 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only. EPRESCALE_FMT2 determines the bit transfer rate of Data Format 2 if the SPI is the network master. If the SPI / MibSPI is configured as slave this field DOES NOT NEED to be.."
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line.long 0xC "ECCDIAG_CTRL,ECC Diagnostic Control register"
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hexmask.long 0xC 4.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0xC 0.--3. 1. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits. 0101 : Diagnostic mode is enabled. Writes and reads from ECC bits allowed from the ECC address space. Refer to Section 9 for details on ECC/Parity address space. Others : Diagnostic mode is disabled. No.."
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rgroup.long 0x144++0xB
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line.long 0x0 "ECCDIAG_STAT,ECC Diagnostic Status register"
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hexmask.long.word 0x0 18.--31. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 17. "DEFLG1,Double bit error flag for RXRAM 1 - A double bit Error is detected for RXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x0 16. "DEFLG0,Double bit error flag for TXRAM 1 - A double bit Error is detected for TXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x0 2.--15. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 1. "SEFLG1,Single bit error flag for RXRAM 1 - A Single bit Error is detected for RXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x0 0. "SEFLG0,Single bit error flag for TXRAM 1 - A Single bit Error is detected for TXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A Single bit Error is detected for TXRAM bank.."
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line.long 0x4 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
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hexmask.long.tbyte 0x4 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0x4 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM. This error address is frozen from being updated until it is read by.."
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line.long 0x8 "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
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hexmask.long.tbyte 0x8 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0x8 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM. The TXRAM can be read either by CPU or by the MibSPI Sequencer logic for.."
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rgroup.long 0x1FC++0x3
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line.long 0x0 "SPIREV,SPI / MibSPI Revision ID Register"
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bitfld.long 0x0 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes. Reads 0x01" "0,1,2,3"
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bitfld.long 0x0 28.--29. "NU,Reserved.Reads return '0' and writes have no effect." "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version number Read value will provide an approximate RTL revision number. The design release version can be obtained from the device specification"
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bitfld.long 0x0 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision number Reads 0x8"
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tree.end
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tree "MSS_SPIB"
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base ad:0x2F7EA00
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group.long 0x0++0x1B
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line.long 0x0 "SPIGCR0,SPI / MibSPI Global Control Register 0"
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hexmask.long 0x0 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect."
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bitfld.long 0x0 0. "nRESET,This is the local reset control for the module. This bit needs to be set to '1' before any operation on SPI / MibSPI can be done. Only after setting this bit to '1' the Auto Initialization of Multibuffer RAM starts. Clearing this bit to.." "0: SPI / MibSPI is in reset state,1: SPI / MibSPI is out of reset state"
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line.long 0x4 "SPIGCR1,SPI / MibSPI Global control register 1"
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hexmask.long.byte 0x4 25.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 24. "SPIEN,SPI enable. This bit enables the SPI/MibSPI transfers. This bit must be set to 1 after all other SPI / MibSPI configuration bits have been written. When SPIEN bit is 0 or cleared to 0 the following SPI/MibSPI registers get forced to their default.." "0: SPI / MibSPI is not activated for transfers,1: Activates SPI / MibSPI"
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hexmask.long.byte 0x4 17.--23. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 16. "LOOPBACK,LOOP BACK. Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. If the SPISIMO and SPISOMI pins are configured with SPI functionality then the SPISIMO pin is internally connected to the SPISOMI pin." "0: Internal loop-back test mode disabled,1: Internal loop-back test mode enabled"
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hexmask.long.byte 0x4 9.--15. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 8. "POWERDOWN,POWERDOWN. When active the SPI / MibSPI state machines enter a powerdown state. 0=MibSPI in active mode 1=MibSPI in powerdown mode" "0: MibSPI in active mode 1=MibSPI in powerdown mode,?"
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hexmask.long.byte 0x4 2.--7. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 1. "CLKMOD,CLKMOD. Clock mode Selects either an internal or external clock source. This bit also determines the I/O direction of the SPIENA and SPISCS[7:0] pins in functional mode. 0=Clock is external 1=Clock is internal" "0: Clock is external 1=Clock is internal,?"
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bitfld.long 0x4 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination. Determines the direction of the SPISIMO and SPISOMI pins. This bit determines whether the SPI/MibSPI is in Master mode or Slave mode. This bit also controls the Master-only features like the.." "0: SPISIMO pin an input,1: SPISOMI pin an input"
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line.long 0x8 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
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hexmask.long.byte 0x8 25.--31. 1. "NU5,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 24. "ENABLEHIGHZ,SPIENA pin high-z enable. When active the SPIENA pin (when it is configured as a WAIT functional output signal in a slave SPI) is forced to place it is output in high-z when not driving a low signal. If inactive then the pin will output.." "0: SPIENA pin is pulled high when not active,1: SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x8 17.--23. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 16. "DMAREQEN,DMA request enable. Enables the DMA request signal to be generated for both receive and transmit channels. Enable DMA REQ only after setting the SPIEN bit to '1'. 0=DMA is not used 1=DMA Requests will be generated. A DMA request will be.." "0: DMA is not used 1=DMA Requests will be generated,?"
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hexmask.long.byte 0x8 10.--15. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF. Setting this bit will generate an interrupt if TXINTFLG bit (SPIFLG.9) is set to '1'. 0=No interrupt will be.." "0: No interrupt will be generated upon TXINTFLG..,1: Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x8 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware. Otherwise no interrupt will be generated. 0=Interrupt will not be generated 1=Interrupt will be generated Both Transmitter Empty & Receiver Full interrupts.." "0: Interrupt will not be generated 1=Interrupt will..,?"
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rbitfld.long 0x8 7. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x8 6. "OVRNINTENA,Overrun interrupt enable. An interrupt is to be generated when the RCVR OVRN flag bit (SPIFLG.6) is set by hardware. Otherwise no interrupt will be generated. 0=Overrun interrupt will not be generated 1=Overrun interrupt will be generated" "0: Overrun interrupt will not be generated..,?"
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rbitfld.long 0x8 5. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x8 4. "BITERRENA,Enables interrupt on bit error. 1 =Enables an interrupt on a bit error (BITERR = 1). 0 =No interrupt asserted upon bit error." "0: No interrupt asserted upon bit error,1: Enables an interrupt on a bit error"
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bitfld.long 0x8 3. "DESYNCENA,Enables interrupt on de-synchronized slave. DESYNCENA is used in master mode only. 1 =Enables an interrupt on de-synchronization of the slave (DESYNC = 1). 0 =No interrupt asserted upon de-synchronization error." "0: No interrupt asserted upon de-synchronization..,1: Enables an interrupt on de-synchronization of.."
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bitfld.long 0x8 2. "PARERRENA,Enables interrupt on parity error. 1 =Enables an interrupt on a parity error (PARITYERR = 1). 0 =No interrupt asserted upon parity error." "0: No interrupt asserted upon parity error,1: Enables an interrupt on a parity error"
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bitfld.long 0x8 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out. 1 =Enables an interrupt on a time-out of the ENA signal (TIMEOUT = 1). 0 =No interrupt asserted upon ENA signal time-out." "0: No interrupt asserted upon ENA signal time-out,1: Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x8 0. "DLENERRENA,Data Length Error interrupt Enable. 1 = Enables an interrupt when Data Length Error occurs. 0 = No interrupt is generated upon Data Length Error. A Data Length Error occurs under the following conditions. Master: In a 4-pin with SPIENA mode or.." "0: No interrupt is generated upon Data Length Error,1: Enables an interrupt when Data Length Error occurs"
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line.long 0xC "SPILVL,SPI / MibSPI Interrupt Level Register"
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hexmask.long.tbyte 0xC 10.--31. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0xC 9. "TXINTLVL,Transmit Interrupt Level. 1 =Transmit interrupt is mapped to interrupt line INT1. 0 =Transmit interrupt is mapped to interrupt line INT0." "0: Transmit interrupt is mapped to interrupt line..,1: Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0xC 8. "RXINTLVL,Receive interrupt level. 1 =Receive interrupt is mapped to interrupt line INT1. 0 =Receive interrupt is mapped to interrupt line INT0." "0: Receive interrupt is mapped to interrupt line INT0,1: Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0xC 7. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0xC 6. "OVRNINTLVL,Receive Overrun interrupt level. 1 =Receive Overrun interrupt is mapped to interrupt line INT1. 0 =Receive Overrun interrupt is mapped to interrupt line INT0." "0: Receive Overrun interrupt is mapped to interrupt..,1: Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0xC 5. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0xC 4. "BITERRLVL,Bit error interrupt level. 1 =bit error interrupt is mapped to interrupt line INT1. 0 =bit error interrupt is mapped to interrupt line INT0." "0: bit error interrupt is mapped to interrupt line..,1: bit error interrupt is mapped to interrupt line.."
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bitfld.long 0xC 3. "DESYNCLVL,De-synchronized slave interrupt level. DESYNCLVL is used in master mode only. 1 =An interrupt due to de-synchronization of the slave (DESYNC = 1) is mapped to interrupt line INT1. 0 =An interrupt due to de-synchronization of the slave (DESYNC =.." "0: An interrupt due to de-synchronization of the..,1: An interrupt due to de-synchronization of the.."
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bitfld.long 0xC 2. "PARERRLVL,Parity error interrupt level. 1 =A parity error interrupt (PARITYERR = 1) is mapped to interrupt line INT1. 0 =A parity error interrupt (PARITYERR = 1) is mapped to interrupt line INT0." "0: A parity error interrupt,1: A parity error interrupt"
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bitfld.long 0xC 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level. 1 =An interrupt on a time-out of the ENA signal (TIMEOUT = 1) is mapped to interrupt line INT1. 0 =An interrupt on a time-out of the ENA signal (TIMEOUT = 1) is mapped to interrupt line INT0." "0: An interrupt on a time-out of the ENA signal,1: An interrupt on a time-out of the ENA signal"
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bitfld.long 0xC 0. "DLENERRLVL,Data Length Error interrupt Enable Level. 1 = An interrupt on Data Length Error is mapped to interrupt line INT1. 0 = An interrupt on Data Length Error is mapped to interrupt line INT0." "0: An interrupt on Data Length Error is mapped to..,1: An interrupt on Data Length Error is mapped to.."
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line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
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hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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rbitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process. Software should poll this bit to determine if it can proceed with the configuration of Multibuffer mode registers or Multibuffer RAM handling. Refer to Section 3.10.7 for details.." "0: Multibuffer RAM initialization is complete,1: Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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rbitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag. Serves as an interrupt flag indicating that Transmit Buffer (TXBUF) is empty and a new data can be written to it. This flag is set when a data is copied to the 'Shift Register' either directly or from the.." "0: Transmit Buffer is now full,1: Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag. This flag is set when a word is received and copied into the buffer register (SPIBUF). If RXINTEN is enabled an interrupt is also generated. During emulation mode however a read to the emulation register (SPIEMU).." "0: No new received data pending,1: A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag. The SPI / MibSPI hardware sets this bit when a receive operation completes before the previous character has been read from the receive buffer. The bit indicates that the last received character has been overwritten and.." "0: Overrun condition did not occur,1: Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data. 1 =A bit error occurred. The SPI / MibSPI samples the signal of the transmit pin (master: SIMO slave: SOMI) at the receive point (half clock cycle after transmit point). If the sampled.." "0: No bit error occurred,1: A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device. De-synchronization monitor is active in master mode only. 1 = A slave device is de-synchronized. The master monitors the ENAble signal coming from the slave device and sets the DESYNC flag after the last bit.." "0: No slave de-synchronization detected,1: A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit. 1 =A parity error occurred. If the parity generator is enabled (can be selected individually for each buffer) an even or odd parity bit is added at the end of a data word (see Section 8.23)." "0: No parity error detected,1: A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal. 1 =An ENA signal time-out occurred. The SPI / MibSPI generates a time-out because the slave hasn't responded in time by activating the ENA signal after the chip select signal has been activated." "0: No ENA-signal time-out occurred,1: An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag. 1 = A Data Length Error has occured. 0 = No Data Length Error has occured. This flag can be cleared by one of the following ways. Write a '1' to this bit. Set SPIEN bit to '0'. A Data Length Error occurs under.." "0: No Data Length Error has occured,1: A Data Length Error has occured"
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line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented. it is a mirror of Bit11. Any write to Bit 24 will be reflected on Bit11 and when Bit 24 & Bit 11.."
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hexmask.long.byte 0x14 24.--31. 1. "SOMIFUN,Slave out master in function. Determines whether the SPISOMIx pins are to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISOMIx pin is a GPIO 1=SPISOMIx pin is a SPI / MibSPI functional pin"
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hexmask.long.byte 0x14 16.--23. 1. "SIMOFUN,Slave in master out function. Determines whether the SPISIMOx pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISIMOx pin is a GPIO 1=SPISIMOx pin is a SPI / MibSPI functional pin Note: Generic based bit.."
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hexmask.long.byte 0x14 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function. Determines whether the SPISOMI0 pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISOMI0 pin is a GPIO 1=SPISOMI0 pin is a SPI / MibSPI functional pin Note: Bit 11 or bit 24.." "0: SPISOMI0 pin is a GPIO 1=SPISOMI0 pin is a SPI /..,?"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function. Determines whether the SPISIMO0 pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPISIMO0 pin is a GPIO 1=SPISIMO0 pin is a SPI / MibSPI functional pin Note: Bit 10 or bit 16.." "0: SPISIMO0 pin is a GPIO 1=SPISIMO0 pin is a SPI /..,?"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function. Determines whether the SPICLK pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPICLK pin is a GPIO 1=SPICLK pin is a SPI / MibSPI functional pin" "0: SPICLK pin is a GPIO 1=SPICLK pin is a SPI /..,?"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function. Determines whether the SPIENA pin is to be used as a general-purpose I/O pin or as a SPI / MibSPI functional pin. 0=SPIENA pin is a GPIO 1=SPIENA pin is a SPI / MibSPI functional pin" "0: SPIENA pin is a GPIO 1=SPIENA pin is a SPI /..,?"
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hexmask.long.byte 0x14 0.--7. 1. "SCSFUN,SPISCS[7:0] function. Determines whether the SPISCSx pins are to be used as a general-purpose I/O pins or as SPI functional pins. If the slave SPISCSx pins are in functional mode and receive an inactive high signal the slave SPI will place it is.."
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line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
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hexmask.long.byte 0x18 24.--31. 1. "SOMIDIR,SPISOMIx direction. Controls the direction of the SPISOMIx pin when it is used as a general-purpose I/O pin. If the SPISOMIx pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISOMIx pin is an.."
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hexmask.long.byte 0x18 16.--23. 1. "SIMODIR,SPISIMOx direction. Controls the direction of the SPISIMOx pin when it is used as a general-purpose I/O pin. If the SPISIMOx pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISIMOx pin is an.."
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hexmask.long.byte 0x18 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction. Controls the direction of the SPISOMI0 pin when it is used as a general-purpose I/O pin. If the SPISOMI0 pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISOMI0 pin is an.." "0: SPISOMI0 pin is an input 1=SPISOMI0 pin is an..,?"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction. Controls the direction of the SPISIMO0 pin when it is used as a general-purpose I/O pin. If the SPISIMO0 pin is used as a SPI / MibSPI functional pin the I/O direction is determined by the MASTER bit. 0=SPISIMO0 pin is an.." "0: SPISIMO0 pin is an input 1=SPISIMO0 pin is an..,?"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction. Controls the direction of the SPICLK pin when it is used as a general-purpose I/O pin. In functional mode the I/O direction is determined by the CLKMOD bit. 0=SPICLK pin is an input 1=SPICLK pin is an output" "0: SPICLK pin is an input 1=SPICLK pin is an output,?"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction. Controls the direction of the SPIENA pin when it is used as a general-purpose I/O. If the SPIENA pin is used as a functional pin then the I/O direction is determined by the CLKMOD bit (SPIGCR1.1). 0=SPIENA pin is an input.." "0: SPIENA pin is an input 1=SPIENA pin is an output,?"
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hexmask.long.byte 0x18 0.--7. 1. "SCSDIR,SPISCS[7:0] direction. Controls the direction of the SPISCSx pins when they are used as a general-purpose I/O pin. Each pins could be configured independently from the others If the SPISCSx is used as a SPI functional pin the I/O direction is.."
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rgroup.long 0x1C++0x3
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line.long 0x0 "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
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hexmask.long.byte 0x0 24.--31. 1. "SOMIDIN,SPISOMIx data in. Reflects the value of the SPISOMIx pin. 0=Current value on SPISOMIx pin is logic 0. 1=Current value on SPISOMIx pin is logic 1"
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hexmask.long.byte 0x0 16.--23. 1. "SIMODIN,SPISIMOx data in. Reflects the value of the SPISIMOx pin. 0=Current value on SPISIMOx pin is logic 0. 1=Current value on SPISIMOx pin is logic 1"
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hexmask.long.byte 0x0 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 11. "SOMIDIN0,SPISOMI0 data in. Reflects the value of the SPISOMI0 pin. 0=Current value on SPISOMI0 pin is logic 0. 1=Current value on SPISOMI0 pin is logic 1 Note: Bit 11 or bit 24 can be used to set the direction for pin SOMI0. If a 32 bit write is.." "0: Current value on SPISOMI0 pin is logic 0,1: Current value on SPISOMI0 pin is logic 1 Note:.."
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bitfld.long 0x0 10. "SIMODIN0,SPISIMO0 data in. Reflects the value of the SPISIMO0 pin. 0=Current value on SPISIMO0 pin is logic 0. 1=Current value on SPISIMO0 pin is logic 1. Note: Bit 10 or bit 16 can be used to set the direction for pin SIMO0. If a 32 bit write is.." "0: Current value on SPISIMO0 pin is logic 0,1: Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x0 9. "CLKDIN,Clock data in. Reflects the value of the SPICLK pin. 0=Current value on SPICLK pin is logic 0. 1=Current value on SPICLK pin is logic 1" "0: Current value on SPICLK pin is logic 0,1: Current value on SPICLK pin is logic 1"
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bitfld.long 0x0 8. "ENADIN,SPIENA data in. Reflects the value of the SPIENA pin. 0=Current value on SPIENA pin is logic 0. 1=Current value on SPIENA pin is logic 1" "0: Current value on SPIENA pin is logic 0,1: Current value on SPIENA pin is logic 1"
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hexmask.long.byte 0x0 0.--7. 1. "SCSDIN,SPISCS[7:0] data in. Reflects the value of the SPISCSx pins. 0=Current value on SPISCSx pin is logic 0. 1=Current value on SPISCSx pin is logic 1 Note: Effect of NUM_CS_PINS generic on ChipSelect bits. Actual number of bits implemented in.."
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group.long 0x20++0xF
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line.long 0x0 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
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hexmask.long.byte 0x0 24.--31. 1. "SOMIDOUT,SPISOMIx dataout write. Only active when the SPISOMIx pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISOMIx pin is logic 0."
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hexmask.long.byte 0x0 16.--23. 1. "SIMODOUT,SPISIMOx dataout write. Only active when the SPISIMOx pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISIMOx pin is logic 0."
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hexmask.long.byte 0x0 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 11. "SOMIDOUT0,SPISOMI0 dataout write. Only active when the SPISOMI0 pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISOMI0 pin is logic 0." "0: Current value on SPISOMI0 pin is logic 0,1: Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x0 10. "SIMODOUT0,SPISIMO0 dataout write. Only active when the SPISIMO0 pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPISIMO0 pin is logic 0." "0: Current value on SPISIMO0 pin is logic 0,1: Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x0 9. "CLKDOUT,SPICLK dataout write. Only active when the SPICLK pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPICLK pin is logic 0. 1=Current value.." "0: Current value on SPICLK pin is logic 0,1: Current value on SPICLK pin is logic 1"
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bitfld.long 0x0 8. "ENADOUT,SPIENA dataout write. Only active when the SPIENA pin is configured as a general-purpose I/O pin and configured as an output pin. The value of this bit indicates the value sent to the pin. 0=Current value on SPIENA pin is logic 0. 1=Current value.." "0: Current value on SPIENA pin is logic 0,1: Current value on SPIENA pin is logic 1"
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hexmask.long.byte 0x0 0.--7. 1. "SCSDOUT,SPISCS[7:0] dataout write. Only active when the SPISCSx pins are configured as a general-purpose I/O pins and configured as an output pins. The value of these bit indicates the value sent to the pins. 0=Current value on SPISCSx pin is logic 0."
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line.long 0x4 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
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hexmask.long.byte 0x4 24.--31. 1. "SOMISET,SPISOMIx dataout set. Only active when the SPISOMIx pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISOMIDOUTx bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.."
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hexmask.long.byte 0x4 16.--23. 1. "SIMOSET,SPISIMOx dataout set. Only active when the SPISIMOx pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISIMODOUTx bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.."
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hexmask.long.byte 0x4 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x4 11. "SOMISET0,SPISOMI0 dataout set. Only active when the SPISOMI0 pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISOMIDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.." "0: Current value on SOMIDOUT0 is 0,1: Current value on SOMIDOUT0 is 1"
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bitfld.long 0x4 10. "SIMOSET0,SPISIMO0 dataout set. Only active when the SPISIMO0 pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding SPISIMODOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on.." "0: Current value on SIMODOUT0 is 0,1: Current value on SIMODOUT0 is 1"
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bitfld.long 0x4 9. "CLKSET,SPICLK dataout set. Only active when the SPICLK pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding CLKDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on SPICLK pin if it.." "0: Current value on CLKDOUT pin is logic 0,1: Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x4 8. "ENASET,SPIENA dataout set. Only active when the SPIENA pin is configured as a general-purpose output pin. A value of '1' written to this bit sets the corresponding ENABLEDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on SPIENA pin if.." "0: Current value on ENADOUT is 0,1: Current value on ENADOUT is 1"
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hexmask.long.byte 0x4 0.--7. 1. "SCSSET,SPISCS[7:0] dataout set. Only active when the SPISCSx pins are configured as a general-purpose output pins. A value of '1' written to these bits set the corresponding SCSDOUT bit to '1'. Write: 0= Has no effect 1= Logic 1 placed on SPISCSx.."
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line.long 0x8 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
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hexmask.long.byte 0x8 24.--31. 1. "SOMICLR,SPISOMIx dataout clear. Only active when the SPISOMIx pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SPISOMIDOUTx bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.."
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hexmask.long.byte 0x8 16.--23. 1. "SIMOCLR,SPISIMOx dataout clear. Only active when the SPISIMOx pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SPISIMODOUTx bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.."
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hexmask.long.byte 0x8 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 11. "SOMICLR0,SPISOMI0 dataout clear. Only active when the SPISOMI0 pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SPISOMIDOUT bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.." "0: Current value on SOMIDOUT0 is 0,1: Current value on SOMIDOUT0 is 1"
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bitfld.long 0x8 10. "SIMOCLR0,SPISIMO0 dataout clear. Only active when the SPISIMO0 pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding SIMODOUT0 bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on.." "0: Current value on SIMODOUT0 is 0,1: Current value on SIMODOUT0 is 1"
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bitfld.long 0x8 9. "CLKCLR,SPICLK dataout clear. Only active when the SPICLK pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding CLKDOUT bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on SPICLK pin if.." "0: Current value on CLKDOUT is 0,1: Current value on CLKDOUT is 1"
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bitfld.long 0x8 8. "ENACLR,SPIENA dataout clear. Only active when the SPIENA pin is configured as a general-purpose output pin. A value of '1' written to this bit clears the corresponding ENABLEDOUT bit to '0'. Write: 0= Has no effect 1= Logic 0 placed on SPIENA pin.." "0: Current value on ENADOUT is 0,1: Current value on ENADOUT is 1"
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hexmask.long.byte 0x8 0.--7. 1. "SCSCLR,SPISCS[7:0] dataout clear. Only active when the SPISCSx pins are configured as a general-purpose output pins. A value of '1' written to this bit clears the corresponding SCSDOUT bit to '0.. Write: 0= Has no effect 1= Logic 0 placed on.."
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line.long 0xC "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
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hexmask.long.byte 0xC 24.--31. 1. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met. SOMIDIRx = 1 (SPISOMI0 pin configured in GPIO mode as output pin) SOMIDOUTx = 1 0 = Output value on SPISOMIx pin is logic '1' 1 =.."
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hexmask.long.byte 0xC 16.--23. 1. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met. SIMODIRx = 1 (SPISIMOx pin configured in GPIO mode as output pin) SIMODOUTx = 1 0 = Output value on SPISIMOx pin is logic '1' 1.."
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hexmask.long.byte 0xC 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0xC 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met. SOMIDIR0 = 1 (SPISOMI0 pin configured in GPIO mode as output pin) SOMIDOUT0 = 1 0 = Output value on SPISOMI0 pin is logic '1' 1.." "0: Output value on SPISOMI0 pin is logic '1',1: Output pin SPISOMI0 is Tri-stated Note: Bit 11.."
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bitfld.long 0xC 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met. SIMODIR0 = 1 (SPISIMO pin configured in GPIO mode as output pin) SIMODOUT0 = 1 0 = Output value on SPISIMO0 pin is logic '1' 1.." "0: Output value on SPISIMO0 pin is logic '1',1: Output pin SPISIMO0 is Tri-stated Note: Bit 10.."
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bitfld.long 0xC 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met. CLKDIR = 1 (SPICLK pin configured in GPIO mode as output pin) CLKDOUT = 1 0 = Output value on SPICLK pin is logic '1' 1 = Output pin.." "0: Output value on SPICLK pin is logic '1',1: Output pin SPICLK is Tri-stated"
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bitfld.long 0xC 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met. ENABLEDIR = 1 (SPIENA pin configured in GPIO mode as output pin) ENABLEDOUT = 1 0 = Output value on SPIENA pin is logic '1' 1 =.." "0: Output value on SPIENA pin is logic '1',1: Output pin SPIENA is Tri-stated"
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hexmask.long.byte 0xC 0.--7. 1. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met. SCSDIRx = 1 (SPISCS pin configured in GPIO mode as output pin) SCSDOUTx = 1 0 = Output value on SPISCSx pin is logic '1' 1 =.."
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group.long 0x38++0xB
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line.long 0x0 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI. It is only accessible in compatibility mode."
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hexmask.long.word 0x0 16.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data. When written these bits will be copied to the Shift Register if it is empty. If the Shift Register is not empty the TXBUF will hold the written values. SPIEN (SPICGR1.24) must be set to 1 before this register can be.."
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line.long 0x4 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned."
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rbitfld.long 0x4 29.--31. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 28. "CSHOLD,Chip select hold mode. In SPI or compatibility mode MibSPI the CSHOLD bit is supported in master mode only. In slave mode this bit is ignored. CSHOLD defines the behavior of the chip select line at the end of a data transfer. 1 =The chip select.." "0: The chip select signal is deactivated at the end..,1: The chip select signal is held active at the end.."
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rbitfld.long 0x4 27. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 26. "WDEL,Enable the delay counter at the end of the current transaction. WDELAY bit is supported in Master mode only. In Slave mode this bit will be ignored. 1 = After a transaction WDELAY of the corresponding data format will be loaded into the delay.." "0: No delay will be inserted,1: After a transaction"
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bitfld.long 0x4 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x4 16.--23. 1. "CSNR,Chip select number. CSNR defines the chip select that shall be activated during the data transfer. The value of CSNR[7:0] will be driven on SPISCS[7:0] lines during the transfer. Note: Effect of NUM_CS_PINS generic on CSNR bits. Actual number of.."
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hexmask.long.word 0x4 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data. When written these bits will be copied to the Shift Register if it is empty. If the Shift Register is not empty the TXBUF will hold the written values. SPIEN must be set to 1 before this register can be written to."
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line.long 0x8 "SPIBUF,SPI / MibSPI Receive Buffer Register"
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bitfld.long 0x8 31. "RXEMPTY,Receive data buffer empty. When host reads the SPIBUF field or the whole SPIBUF register this will automatically set the RXEMPTY flag. When a data transfer is completed the received data is copied into SPIBUF the RXEMPTY flag is cleared. 1 =No.." "0: A new Data is received and copied into SPIBUF..,1: No data received since last reading of SPIBUF.."
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bitfld.long 0x8 30. "RXOVR,Receive data buffer overrun. When a data transfer is completed and the received data is copied into the RXBUF while it is already full RXOVR is set. Refer to Figure 1 for a view of internal logic diagram. An Overrun always occurs to the RXBUF and.." "0: No receive data overrun condition occurred since..,1: A receive data overrun condition occurred since.."
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rbitfld.long 0x8 29. "TXFULL,Transmit data buffer full. This flag is a read-only flag. Writing into SPIDAT0 or SPIDAT1 field while TX Shift Register is full will automatically set the TXFULL flag. Once the data is copied to the Shift Register the TXFULL flag will be cleared." "0: Transmit buffer is empty,1: Transmit buffer is full"
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bitfld.long 0x8 28. "BITERR,Mismatch of internal transmit data and transmitted data. 1 =A bit error occurred. The SPI / MibSPI samples the signal of the transmit pin (master: SIMO slave: SOMI) at the receive point (half clock cycle after transmit point). If the sampled.." "0: No bit error occurred,1: A bit error occurred"
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bitfld.long 0x8 27. "DESYNC,De-synchronization of slave device. De-synchronization monitor is active in master mode only. 1 =A slave device is de-synchronized. The master monitors the ENA signal coming from the slave device and sets the DESYNC flag if ENA is deactivated.." "0: No slave de-synchronization detected,1: A slave device is de-synchronized"
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bitfld.long 0x8 26. "PARITYERR,Calculated parity differs from received parity bit. 1 =A parity error occurred. If the parity generator is enabled (can be selected individually for each buffer) an even or odd parity bit is added at the end of a data word (see Section 8.23)." "0: No parity error detected,1: A parity error occurred"
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bitfld.long 0x8 25. "TIMEOUT,Time-out due to non-activation of ENA pin. 1 =An ENA signal time-out occurred. The SPI / MibSPI generates a time-out because the slave hasn't responded in time by activating the ENA signal after the chip select signal has been activated. If a.." "0: No ENA-pin time-out occurred,1: An ENA signal time-out occurred"
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bitfld.long 0x8 24. "DLENERR,Data Length Error flag. 1 = A Data Length Error has occured. 0 = No Data Length Error has occured. This flag is cleared to '0' when RXDATA portion of the SPIBUF register is read." "0: No Data Length Error has occured,1: A Data Length Error has occured"
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hexmask.long.byte 0x8 16.--23. 1. "LCSNR,Last Chip select number. LCSNR in the status field is a copy of CSNR in the corresponding control field. It defines the chip select that has been activated during the last data transfer from the corresponding buffer. This is the copy of CSNR bits.."
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hexmask.long.word 0x8 0.--15. 1. "RXDATA,SPI Receive Data. This is the received data transferred from the Receive Shift-Register at the end of a transfer completion. Irrespective of the programmed character length & the direction of shifting the received data is stored right-justified.."
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rgroup.long 0x44++0x3
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line.long 0x0 "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only. Read operation on this register under any mode will not have any impact on the status of this or any other registers."
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bitfld.long 0x0 31. "RXEMPTY,Receive data buffer empty. 1 = No data received since last reading of SPIBUF register. 0 = A new Data is received and copied into SPIBUF field." "0: A new Data is received and copied into SPIBUF..,1: No data received since last reading of SPIBUF.."
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bitfld.long 0x0 30. "RXOVR,Receive data buffer overrun. 1 =A receive data overrun condition occurred since last time reading the data field. 0 =No receive data overrun condition occurred since last time reading the data field." "0: No receive data overrun condition occurred since..,1: A receive data overrun condition occurred since.."
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bitfld.long 0x0 29. "TXFULL,Transmit data buffer full. 1 =Transmit buffer is full SPIDAT0/SPIDAT1 is not ready to accept a new data. 0 =Transmit buffer is empty SPIDAT0/SPIDAT1 is ready to accept a new data." "0: Transmit buffer is empty,1: Transmit buffer is full"
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bitfld.long 0x0 28. "BITERR,Mismatch of internal transmit data and transmitted data. 1 =A bit error occurred. The SPI / MibSPI samples the signal of the transmit pin (master: SIMO slave: SOMI) at the receive point (half clock cycle after transmit point). If the sampled.." "0: No bit error occurred,1: A bit error occurred"
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bitfld.long 0x0 27. "DESYNC,De-synchronization of slave device. De-synchronization monitor is active in master mode only. 1 =A slave device is de-synchronized. The master monitors the ENA signal coming from the slave device and sets the DESYNC flag if ENA is deactivated.." "0: No slave de-synchronization detected,1: A slave device is de-synchronized"
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bitfld.long 0x0 26. "PARITYERR,Calculated parity differs from received parity bit. 1 =A parity error occurred. If the parity generator is enabled (can be selected individually for each buffer) an even or odd parity bit is added at the end of a data word (see Section 8.23)." "0: No parity error detected,1: A parity error occurred"
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bitfld.long 0x0 25. "TIMEOUT,Time-out due to non-activation of ENA pin. 1 =An ENA signal time-out occurred. The SPI / MibSPI generates a time-out because the slave hasn't responded in time by activating the ENA signal after the chip select signal has been activated. If a.." "0: No ENA-pin time-out occurred,1: An ENA signal time-out occurred"
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bitfld.long 0x0 24. "DLENERR,Data Length Error flag. 1 = A Data Length Error has occured. 0 = No Data Length Error has occured." "0: No Data Length Error has occured,1: A Data Length Error has occured"
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hexmask.long.byte 0x0 16.--23. 1. "LCSNR,Last Chip select number. LCSNR in the status field is a copy of CSNR in the corresponding control field. It defines the chip select that has been activated during the last data transfer from the corresponding buffer. This is the copy of CSNR bits.."
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,SPI Receive Data. SPI / MibSPI emulation is a mirror of the SPIBUF register. The only difference between SPIEMU and SPIBUF is that a read from SPIEMU does not clear any of the status flags."
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group.long 0x48++0x7
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line.long 0x0 "SPIDELAY,SPI / MibSPI Delay Register"
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hexmask.long.byte 0x0 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay. C2TDELAY is used in master mode only. It defines a setup time for the slave device that delays the data transmission from the chip select active edge by a multiple of VBUSPCLK cycles."
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hexmask.long.byte 0x0 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay. T2CDELAY is used in master mode only. It defines a hold time for the slave device that delays the chip select deactivation by a multiple of VBUSPCLK cycles after the last bit is transferred. T2CDELAY.."
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hexmask.long.byte 0x0 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out. T2EDELAY is used in master mode only. It defines a time-out value as a multiple of SPI clock before the ENAble signal has to become inactive and after the CS becomes inactive. The SPI clock.."
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hexmask.long.byte 0x0 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response. C2EDELAY defines the maximum time between the SPI /.."
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line.long 0x4 "SPIDEF,SPI / MibSPI Default Chip select Register"
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hexmask.long.tbyte 0x4 8.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x4 0.--7. 1. "CSDEF0,Chip select default pattern. Master mode behavior. The CSDEFx bits are output to the chip select pins when no transmission are currently performed. It allows the user to set a chip select pattern which deselects all the SPI slaves. 1 =If CSDEFx is.."
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repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
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group.long ($2+0x50)++0x3
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line.long 0x0 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
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hexmask.long.byte 0x0 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3). Idle time that will be applied at the end of the current transmission if the bit WDEL is set in the current buffer. The delay to be applied is equal to: WDELAY * PVBUSPCLK + 2 *.."
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bitfld.long 0x0 23. "PARPOL,Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. It can be used for data format x (x= 0 1 2 3). 1 =An odd parity flag is added at the end of the transmit data stream. 0 =An even parity flag is added at the end of the.." "0: An even parity flag is added at the end of the..,1: An odd parity flag is added at the end of the.."
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bitfld.long 0x0 22. "PARITYENA,Parity enable for data format x. 1= A parity is transmitted at the end of each transmit data stream. At the end of a transfer the parity generator compares the received parity bit with the locally calculated parity flag. If the parity bits do.." "0: No parity generation/ verification is performed..,1: A parity is transmitted at the end of each.."
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bitfld.long 0x0 21. "WAITENA,Master waits for ENA signal from slave for data format x. WAITENA is considered in master mode only. In slave mode this bit has no meaning. WAITENA enables a flexible SPI network where slaves with ENA signal and slaves without ENA signal can be.." "0: The SPI / MibSPI does not wait for the ENA..,1: Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x0 20. "SHIFTDIR,Shift direction for data format x. With bit SHIFTDIRx the shift direction for data format x (x=0 1 2 3) can be selected. 1 =Data format x shift direction: Least significant bit is shifted out first. 0 =Data format x shift direction: Most.." "0: Data format x shift direction: Most significant..,1: Data format x shift direction: Least significant.."
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bitfld.long 0x0 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x. This bit controls the I/O function of SOMI/SIMO lines for a specific requirement where in the case of Master mode TX pin - SIMO will act as an RX pin and in the case of Slave mode RX pin.." "0: Normal Full Duplex transfer,1: If MASTER = '1'"
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bitfld.long 0x0 18. "DISCSTIMERS,Disable Chipselect Timers for this format register. The C2TDELAY & T2CDELAY timers are by default enabled for all the Data Format registers. Using this bit these timers can be disabled for particular Data Format if not required. When a.." "0: Both C2TDELAY & T2CDELAY counts are inserted for..,1: No C2TDELAY or T2CDELAY is inserted in the.."
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bitfld.long 0x0 17. "POLARITY,SPI data format x clock polarity. POLARITYx defines the clock polarity of data format x. POLARITYx can be modified in privilege mode only. 1 =If POLARITYx is set to '1' the SPI clock signal is high-inactive i.e. before and after data.." "0: If POLARITYx is set to '0' the SPI clock signal..,1: If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x0 16. "PHASE,SPI Data format x clock delay. PHASEx defines the clock delay of data format x. PHASEx can be modified in privilege mode only. 1 =If PHASEx is set to '1' the SPI clock signal is delayed by a half SPI clock cycle versus the transmit / receive.." "0: If PHASEx is set to '0' the SPI clock signal is..,1: If PHASEx is set to '1' the SPI clock signal is.."
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hexmask.long.byte 0x0 8.--15. 1. "PRESCALE,SPI data format x prescaler. PRESCALEx can be modified in privilege mode only. PRESCALEx determines the bit transfer rate of data format x if the SPI is the network master. PRESCALEx is directly derived from VBUSPCLK. If the SPI / MibSPI is.."
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rbitfld.long 0x0 5.--7. "NU,Reserved. Reads return '0' and writes have no effect." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--4. 1. "CHARLEN,SPI data format x data word length. CHARLENx defines the word length of data format x. Legal values are 0x02 (data word length = 2 bit) to 0x10 (data word length = 16). Illegal values such as 0x00 or 0x1F are not detected and their effect is.."
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rgroup.long 0x60++0x7
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line.long 0x0 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
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hexmask.long 0x0 6.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 1.--5. 1. "INTVECT0,Interrupt vector for interrupt line INT0. INTVECT0 returns the vector of the pending interrupt at interrupt line INT0. If more than one interrupts are pending INTVECT0 always references the highest priority interrupt source first. The vectors.."
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bitfld.long 0x0 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field. 1 =The interrupt type is a 'transfer suspended' interrupt. I.e." "0: The interrupt type is a 'transfer finished'..,1: The interrupt type is a 'transfer suspended'.."
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line.long 0x4 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
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hexmask.long 0x4 6.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x4 1.--5. 1. "INTVECT1,Interrupt vector for interrupt line INT1. INTVECT1 returns the vector of the pending interrupt at interrupt line INT0. If more than one interrupt is pending INTVECT1 always references the highest priority interrupt source first. The vectors.."
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bitfld.long 0x4 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field. 1 =The interrupt type is a 'transfer suspended' interrupt. I.e." "0: The interrupt type is a 'transfer finished'..,1: The interrupt type is a 'transfer suspended'.."
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group.long 0x68++0x1B
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line.long 0x0 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
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hexmask.long.byte 0x0 24.--31. 1. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select."
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hexmask.long.byte 0x0 16.--23. 1. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select."
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hexmask.long.byte 0x0 12.--15. 1. "NU,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select. Note: Bit 11 or bit 24 can be used to control the slew rate for SPISOMI0. If a 32 bit write is performed bit 11 will have priority over bit 24." "0: Normal Buffer Select,1: Slow Buffer Select"
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bitfld.long 0x0 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select. Note: Bit 10 or bit 16 can be used to control the slew rate for SPISIMO0. If a 32 bit write is performed bit 10 will have priority over bit 16." "0: Normal Buffer Select,1: Slow Buffer Select"
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bitfld.long 0x0 9. "CLKSRS,This bit controls the slew rate for SPICLK pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select." "0: Normal Buffer Select,1: Slow Buffer Select"
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bitfld.long 0x0 8. "ENASRS,This bit controls the slew rate for SPIENA pin. 0 =Fast Buffer Select. 1 =Slow Buffer Select." "0: Fast Buffer Select,1: Slow Buffer Select"
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hexmask.long.byte 0x0 0.--7. 1. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin. 0 =Normal Buffer Select. 1 =Slow Buffer Select. Note: Effect of NUM_CS_PINS generic on ChipSelect bits. Actual number of bits implemented in SCSSRS[7:0] will depend.."
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line.long 0x4 "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
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rbitfld.long 0x4 31. "NU4,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3. Controls whether the PMODE3 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE3.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only. If MODULO MODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 3.000 = Normal single dataline mode - Default (PMODE should be set to '00') 001 = 2-data line.." "0: Normal single dataline mode,?,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000') 10 =.." "0: normal operation / 1-data line,?,2: data line mode,?"
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rbitfld.long 0x4 23. "NU3,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2. Controls whether the PMODE2 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE2.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2. Determines the Polarity of the SPICLK in Modulo mode only. If MMODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2. 000 = 1-data line Mode - Default (PMODE should be set to '00') 001 = 2-data line Mode (PMODE.." "?,1: data line Mode,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000')10 = 4-data.." "0: normal operation / 1-data line,?,2: data line mode,?"
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rbitfld.long 0x4 15. "NU2,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1. Controls whether the PMODE1 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE1.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1. Determines the Polarity of the SPICLK in Modulo mode only. If MMODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1. 000 = 1-data line Mode - Default (PMODE should be set to '00') 001 = 2-data line Mode (PMODE.." "?,1: data line Mode,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000') 10 =.." "0: normal operation / 1-data line,?,2: data line mode,?"
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rbitfld.long 0x4 7. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1"
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bitfld.long 0x4 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0. Controls whether the PMODE0 bits will result in Modulo Format data transfer or not. Refer to Section 3.26 for details about the HSM Mode. 0 = Normal mode - Normal Parallel mode if PMODE0.." "0: Normal mode,1: High Speed Modulo Mode"
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bitfld.long 0x4 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0. Determines the Polarity of the SPICLK in Modulo mode only. If MMODE[2:0] bits are '000' this bit will be ignored. 0 = Normal SPICLK in all the modes. 1 = Polarity of the SPICLK will be.." "0: Normal SPICLK in all the modes,1: Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x4 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0. 000 = 1-data line Mode - Default (PMODE should be set to '00') 001 = 2-data line Mode (PMODE.." "?,1: data line Mode,2: data line Mode,3: data line mode,4: data line mode,5: data line mode,6: data line mode,?"
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bitfld.long 0x4 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0. 00 = normal operation / 1-data line (MMODE should be set to '000') 01 = 2-data line mode (MMODE should be set to '000') 10 =.." "0: normal operation / 1-data line,?,2: data line mode,?"
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line.long 0x8 "MIBSPIE,MibSPI Enable Register"
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hexmask.long.word 0x8 17.--31. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 16. "RXRAMACCESS,Receive RAM Access control Bit. During normal operating mode of MibSPI the Receive Data/Status portion of Multibuffer RAM is read-only. To enable testing of Data Integrity checks of Receive RAM a special read/write access control is.." "0: The RX portion of Multibuffer RAM is not..,1: The whole of Multibuffer RAM is fully accessible.."
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hexmask.long.byte 0x8 12.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x8 8.--11. 1. "EXTENDED_BUF_ENA,Enables the support for 256 buffers. By default MibSPI supports up to 128 buffers for both TX and RX. It is also possible to extend the support to 256 buffers as a parameterized implementation. This field can be used to enable/disable.."
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hexmask.long.byte 0x8 1.--7. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x8 0. "MSPIENA,Multibuffer mode Enable. After power-up or reset MSPIENA remains cleared which means that the MibSPI runs in compatibility mode by default. If Multibuffer mode is desired this register should be configured first after configuring the SPIGCR0.." "0: The MibSPI runs in compatibility mode,1: The MibSPI is configured to run in MibSPI mode"
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line.long 0xC "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
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hexmask.long.word 0xC 16.--31. 1. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished. Write: 1 = Enables the 'The Transfer group x completed ' interrupt Interrupt gets generated when Transfer Group x gets completed. 0 = Has no effect. Read: 1 = 'The Transfer.."
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hexmask.long.word 0xC 0.--15. 1. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write: 1 = Enables the 'The Transfer group x suspended ' interrupt Interrupt gets generated when Transfer Group x gets suspended. 0 = Has no effect. Read: 1 = 'The Transfer.."
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line.long 0x10 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
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hexmask.long.word 0x10 16.--31. 1. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished. Write: 1 = Disables the 'The Transfer group x completed ' interrupt Interrupt does not get generated when Transfer Group x gets completed. 0 = Has no effect. Read: 1 =.."
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hexmask.long.word 0x10 0.--15. 1. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write: 1 = Disables the 'The Transfer group x suspended ' interrupt Interrupt does not get generated when Transfer Group x gets suspended. 0 = Has no effect. Read: 1 =.."
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line.long 0x14 "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
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hexmask.long.word 0x14 16.--31. 1. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write: 1 = Sets the 'The Transfer group x completed ' interrupt to line INT1 0 = Has no effect. Read: 1 = 'The Transfer group x completed ' interrupt is set to line INT1 0 =.."
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hexmask.long.word 0x14 0.--15. 1. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write: 1 = Sets the 'The Transfer group x suspended ' interrupt to line INT1 0 = Has no effect. Read: 1 = 'The Transfer group x suspended ' interrupt is set to line INT1 0 =.."
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line.long 0x18 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
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hexmask.long.word 0x18 16.--31. 1. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write: 1 = Sets the 'The Transfer group x completed ' interrupt to line INT0 0 = Has no effect. Read: 1 = 'The Transfer group x completed ' interrupt is set to line INT1 0 =.."
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hexmask.long.word 0x18 0.--15. 1. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write: 1 = Sets the 'The Transfer group x suspended ' interrupt to line INT0 0 = Has no effect. Read: 1 = 'The Transfer group x suspended ' interrupt is set to line INT1 0 =.."
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rgroup.long 0x84++0x3
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line.long 0x0 "TGINTFLAG,Transfer Group Interrupt Flag Register"
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hexmask.long.word 0x0 16.--31. 1. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt. Read: 1 =A 'transfer finished' interrupt from transfer group x occurred. No matter whether the interrupt is enabled or disabled (INTENRDYx = don't care) or whether the.."
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hexmask.long.word 0x0 0.--15. 1. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt. Read: 1 =A 'transfer suspended' interrupt from transfer group x occurred. No matter whether the interrupt is enabled or disabled (INTENSUSx = don't care) or whether the.."
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group.long 0x90++0x27
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line.long 0x0 "TICKCNT,Tick Count Register"
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bitfld.long 0x0 31. "TICKENA,Tick counter enable. 1 =The MibSPI internal tick counter is enabled and is clocked by the clock source selected by CLKCTRL[1:0]. When the tick counter is enabled it starts down-counting from its current value. When TICKENA goes from '0' to.." "0: The MibSPI internal tick counter is disabled,1: The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x0 30. "RELOAD,Re-load tick counter. RELOAD is a set-only bit i.e. writing a '1' to it automatically reloads the Tick Counter with the value stored in TICKVALUE. Reading RELOAD always returns a '0'. Note: When the tick counter is reloaded by the RELOAD.." "0,1"
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bitfld.long 0x0 28.--29. "CLKCTRL,Tick counter clock source control. CLKCTRL[1:0] defines the clock source that is used to clock the MibSPI internal tick counter.CLKCTRL[1:0] Description 00b SPICLK of Data word format 0 is selected as clock source of tick counter 01b SPICLK of.." "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0 0.--15. 1. "TICKVALUE,Initial value for tick counter. TICKVALUE stores the initial value for the tick counter. The tick counter is loaded with TICKVALUE every time an under-flow condition occurs and every time the RELOAD flag is set by the host"
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line.long 0x4 "LTGPEND,Last Transfer Group End Pointer"
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rbitfld.long 0x4 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 24.--28. 1. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer. Read-Only field indicating the current Transfer Group that is being serviced. This field can generally be used for code debug purpose. Read Value:TG IN SERVICE[4:0] Description 00000b.."
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hexmask.long.byte 0x4 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x4 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART). The transfer group ends at the buffer one before the next.."
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hexmask.long.byte 0x4 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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line.long 0x8 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16. Depending on the implementation the number of transfer groups and hence the number of transfer group control register may vary. Each.."
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bitfld.long 0x8 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x8 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x8 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x8 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x8 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x8 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x8 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x8 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x8 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0xC "TG1CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0xC 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0xC 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0xC 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0xC 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0xC 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0xC 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0xC 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0xC 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0xC 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x10 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x10 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x10 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x10 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x10 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x14 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x14 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x14 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x14 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x14 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x18 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x18 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x18 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x18 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x18 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x1C 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x1C 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x1C 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x1C 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x1C 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x20 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x20 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x20 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x20 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x20 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
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bitfld.long 0x24 31. "TGENA,Transfer Group Enable. 1 =The corresponding transfer group is enabled. If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx) a group transfer is initiated if no higher priority transfer group is in active transfer mode or if one.." "0: The corresponding transfer group is disabled,1: The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group. 1 =A transfer from the corresponding transfer group will be performed only once (= one shot) after a valid trigger event at the selected trigger source. After the transfer is finished the TGENAx.." "0: The corresponding transfer group initiates a..,1: A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode. With PRST the way of resolving trigger events during an ongoing transfer from the concerned transfer group can be configured. This bit is meaningful only for Level Triggered Transfer Groups. Edge triggered TGs.." "0: If a trigger event occurs during a transfer from..,1: The corresponding transfer group pointer"
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rbitfld.long 0x24 28. "TGTD,Transfer group triggered. This bit is read-only. 1 =The transfer group has been triggered and is either currently in service or waiting for servicing. 0 =The corresponding transfer group has not been triggered or is no more waiting for service. Use.." "0: The corresponding transfer group has not been..,1: The transfer group has been triggered and is.."
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hexmask.long.byte 0x24 24.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x24 20.--23. 1. "TRIGEVT,Type of trigger event. After reset the trigger event types of all transfer groups are set to inactive TypesTRIGEVTx[3:0] Type Description 0000b never 0001b rising edge A rising edge (0 to 1) at the selected trigger source (TRIGSRCx) initiates a.."
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hexmask.long.byte 0x24 16.--19. 1. "TRIGSRC,Trigger source. After reset the trigger sources of all transfer groups are disabled. Table 22. Trigger SourcesTRIGSRCx[3:0] Type Description 0000b disabled 0001b EXT0 MibSPI external trigger source 0. Source has to be defined individually for.."
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address. PSTARTx stores the start address of the corresponding transfer group. The corresponding end address is inherently defined by the subsequent transfer groups start address minus one (PENDx[TGx] = PSTARTx[TGx+1]-1)."
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer. PCURRENT is read-only. PCURRENTx stores the address (0...127/255) of the buffer that is currently transferred or that will be transferred after a trigger event occurs (if PRSTx=0) or after the transfer.."
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group.long 0xD8++0x13
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line.long 0x0 "DMA0CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x0 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x0 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x0 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x0 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x0 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x0 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x0 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x0 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x0 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x0 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0x4 "DMA1CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x4 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x4 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x4 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x4 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x4 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x4 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x4 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x4 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x4 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x4 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x4 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0x8 "DMA2CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x8 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x8 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x8 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x8 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x8 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x8 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x8 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x8 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x8 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x8 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x8 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0xC "DMA3CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0xC 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0xC 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0xC 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0xC 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0xC 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0xC 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0xC 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0xC 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0xC 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0xC 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0xC 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
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bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers. 1 =ONESHOTx allows a block transfer of defined length (ICOUNTx+1) mainly controlled by the MibSPI and not by the DMA controller. After ICOUNTx +1 transfers the enable bits RXDMAENAx and.." "0: The length of the block transfer is fully..,1: ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer. BUFIDx defines the buffer that is utilized for the DMA transfer. In order to synchronize the transfer with the DMA controller with the NOBRK condition the 'suspend to wait until...' modes must be used (for more.."
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hexmask.long.byte 0x10 20.--23. 1. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. One request line for receive data and the other for request line for transmit data. RXDMA_MAPx[3:0] defines the number.."
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hexmask.long.byte 0x10 16.--19. 1. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller. ne request line for receive data and the other for request line for transmit data. TXDMA_MAPx[3:0] defines the number of.."
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable. 1 =The physical DMA Request line for the receive path is enabled. The first DMA request pulse is generated after the first transfer from the referenced buffer (BUFIDx) is finished. The concerned buffer should be.." "0: No DMA request upon new receive data,1: The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable. 1 =The physical DMA Request line for the transmit path is enabled. The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. The concerned buffer should be.." "0: No DMA request upon new transmit data,1: The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only). 1 =NOBRKx ensures that ICOUNTx+1 data transfers are performed from the buffer referenced by BUFIDx without a data transfer from any other buffer. The sequencer remains at the DMA buffer until.." "0: The DMA transfers through the buffer referenced..,1: NOBRKx ensures that ICOUNTx+1 data transfers are.."
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hexmask.long.byte 0x10 8.--12. 1. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]. Every time COUNTx[4:0] hits zero it is reloaded with ICOUNTx[4:0]. The real number of transfer equals ICOUNTx[4:0] plus one. If ONESHOTx is set .."
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented. This bit represents the 8th bit of BUFID field such that any buffers between 127-255 can be configured as DMA capable buffers" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register. This bit is useful only when ICOUNTx in DMAxCOUNT register is programmed to be 0xFFFF. During all other values this bit remains to be '0'." "0,1"
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hexmask.long.byte 0x10 0.--5. 1. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set."
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repeat 4. (list 0x0 0x1 0x3 0x4)(list 0x0 0x4 0xC 0x10)
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group.long ($2+0xF8)++0x3
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line.long 0x0 "ICOUNT$1,MibSPI DMAxCOUNT"
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hexmask.long.word 0x0 16.--31. 1. "ICOUNT,Initial Number of DMA transfers. ICOUNTx is used to preset the transfer counter COUNTx. Every time COUNTx hits zero it is reloaded with ICOUNTx. The real number of transfer equals ICOUNTx plus one. If ONESHOTx is set ICOUNTx defines the number of.."
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hexmask.long.word 0x0 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set. Since the real COUNTx is always ICLOUNTx +1 the 17th bit of.."
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repeat.end
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rgroup.word 0x100++0x1
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line.word 0x0 "ICOUNT2,MibSPI DMAxCOUNT"
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hexmask.word 0x0 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field. It comprises the actual number of DMA transfers that remain until the DMA channel is disabled if ONESHOTx is set. Since the real COUNTx is always ICLOUNTx +1 the 17th bit of.."
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group.long 0x118++0x3
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line.long 0x0 "DMACNTLEN,DMA LARGE COUNT register"
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hexmask.long 0x0 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 0. "LARGE_COUNT,0: Writes to the DMAxCTRL register will modify the ICOUNT value. Reading ICOUNT and COUNT can be done from the DMAxCTRL register. The DMAxCOUNT register should not be used since any write to this register will be overwritten by a subsequent.." "0: Writes to the DMAxCTRL register will modify the..,1: Writes to the DMAxCTRL register will not modify.."
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group.long 0x120++0x3
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line.long 0x0 "PAR_ECC_CTRL,Parity/ECC Control Register"
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hexmask.long.byte 0x0 28.--31. 1. "NU4,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 24.--27. 1. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM. This signal can be used to generate interrupt if required. Write: 0101 -.."
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hexmask.long.byte 0x0 20.--23. 1. "NU3,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 16.--19. 1. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not. Write: 0101 - Disable correction of SBE detected by the SECDED block 1010 - Enable correction of SBE.."
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hexmask.long.byte 0x0 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 8. "PTESTEN,Parity/ECC memory Test Enable. This bit maps the parity/ecc bits corresponding to Multibuffer RAM locations into the peripheral RAM frame to make them accessible by the CPU. User and privilege mode (read): 0 = parity/ecc bits are not memory.." "0: disable memory mapping of Parity/ECC locations,1: enable memory mapping of Parity/ECC locations"
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hexmask.long.byte 0x0 4.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 0.--3. 1. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection. Write: 0101: Disables Parity/ECC Error Detection Logic(default) Others : Enables Parity/ECC Error Detection Logic. Read: Returns the current value of this field"
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rgroup.long 0x124++0xF
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line.long 0x0 "PAR_ECC_STAT,Parity/ECC Status Register"
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hexmask.long.tbyte 0x0 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 9. "SBE_FLG1,Single Bit Error in RXRAM. This flag indicates if a single bit ECC Error ocurred on reading RXRAM Read: 0 = No error occured. 1 = Single bit error is detected in RXRAM and the address is captured in SBERRADDR1 register. Write: 0 = No effect. 1 =.." "0: No effect,1: Clears the bit"
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bitfld.long 0x0 8. "SBE_FLG0,Single Bit Error in TXRAM. This flag indicates if a single bit ECC Error ocurred on reading TXRAM Read: 0 = No error occured. 1 = Single bit error is detected in TXRAM and the address is captured in SBERRADDR0 register. Write: 0 = No effect. 1 =.." "0: No effect,1: Clears the bit"
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hexmask.long.byte 0x0 2.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect."
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bitfld.long 0x0 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read: 0 = No error occured. 1 = Error detected and the address is captured in.." "0: No effect,1: Clears the bit"
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bitfld.long 0x0 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read: 0 = No error occured. 1 = Error detected and the address is captured in UERRADDR0 register." "0: No effect,1: Clears the bit"
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line.long 0x4 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
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hexmask.long.tbyte 0x4 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0x4 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM. The address captured is byte alligned when RAM.."
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line.long 0x8 "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
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hexmask.long.tbyte 0x8 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0x8 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM. The TXRAM can be read either by CPU or by the MibSPI Sequencer FSM logic for.."
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line.long 0xC "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
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hexmask.long.tbyte 0xC 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect."
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hexmask.long.word 0xC 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured. This address value will show only the offset address of the RAM location in the Multibuffer RAM address space. Refer to the device Spec for the actual absolute address.."
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group.long 0x134++0xF
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line.long 0x0 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins. It also controls whether loop-back should be digital or analog ones in this test mode. In addition it contains control bits to induce some of the.."
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hexmask.long.byte 0x0 25.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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bitfld.long 0x0 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode. Read 1 = A comparison between the internal CSNR field and the analog looped back value of SPISCS[7:0] pins failed. A stuck-at fault is detected.." "0: No effect,1: Clear this Flag bit"
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rbitfld.long 0x0 21.--23. "NU3,Reserved. Reads return '0' and writes have no effect." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode. 1 = The value of incoming data from the loopback Transmit pin is flipped. 0 = No affect on BIT ERROR." "0: No affect on BIT ERROR,1: The value of incoming data from the loopback.."
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bitfld.long 0x0 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode. 1 = Forces the incoming SPIENA pin (if functional) to remain '0' even after the transfer complete. This forcing will be retained until the Kernel reaches IDLE state. 0 = No.." "0: No affect on DESYNC Error,1: Forces the incoming SPIENA pin"
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bitfld.long 0x0 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode. 1 = Flips the Parity Polarity signal being used for transmit parity generation logic 0 = No affect on Parity Error" "0: No affect on Parity Error,1: Flips the Parity Polarity signal being used for.."
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bitfld.long 0x0 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode. 1 = Forces the incoming SPIENA pin (if functional) to remain '1' when transmission is initiated. The forcing will be retained until the Kernel reaches IDLE state. 0 = No.." "0: No affect on TIMEOUT Error,1: Forces the incoming SPIENA pin"
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bitfld.long 0x0 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode. 1 = When in Master mode forces the SPIENA pin(if functional) to '1' when the module starts Shifting the data. When in Slave mode forces the incoming SPISCS pin(if.." "0: No affect on Data Length Error,1: When in Master mode"
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hexmask.long.byte 0x0 12.--15. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.byte 0x0 8.--11. 1. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads. Write access only in Privileged mode. Write: 1010 = I/O DFT is enabled All other values = I/O DFT is disabled Read: 1010 = I/O DFT is enabled All other values = I/O DFT is.."
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rbitfld.long 0x0 6.--7. "NU1,Reserved. Reads return '0' and writes have no effect." "0,1,2,3"
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bitfld.long 0x0 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin. The value in this field is decoded to find out the ChipSelect pin on which to inject an error. During the analog loopback of IO Loopback Test mode if CTRL SCS PIN ERR bit is set to '1' then the chipselect.." "0: Select SPISCS[0] for injecting error 001,?,?,?,?,?,?,?"
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bitfld.long 0x0 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins. Individual pins of SPISCS[7:0] can be choosen using ERR SCS PIN. 1 = Enable the error inducing logic to the SPISCS pins. 0 = Disable the error inducing logic." "0: Disable the error inducing logic,1: Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x0 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital). User and Privileged mode reads. Write access only in Privileged mode. Write/Read : 1 = Analog loopback is enabled in module I/O DFT mode when IOLPBKTSTENA = 1010) 0 = Digital loopback is enabled in.." "0: Digital loopback is enabled in module I/O DFT..,1: Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x0 0. "RXPENA,Module Analog loopback through Receive Pin Enable. User and Privileged mode reads. Write only in privileged mode: Write/Read : 1 = Analog loopback through receive pin 0 = Analog loopback through transmit pin. This bit is valid only when LPBK TYPE.." "0: Analog loopback through transmit pin,1: Analog loopback through receive pin"
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line.long 0x4 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This is an extension of.."
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hexmask.long.byte 0x4 27.--31. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x4 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1. EPRESCALE_FMT1 can be modified in privilege mode only. EPRESCALE_FMT1 determines the bit transfer rate of Data Format 1 if the SPI/MibSPI is the network master. If the SPI / MibSPI is configured as.."
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hexmask.long.byte 0x4 11.--15. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x4 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only. EPRESCALE_FMT0 determines the bit transfer rate of Data Format 0 if the SPI is the network master. If the SPI / MibSPI is configured as slave this field DOES NOT NEED to be.."
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line.long 0x8 "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves. This register is an.."
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hexmask.long.byte 0x8 27.--31. 1. "NU4,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x8 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only. EPRESCALE_FMT3 determines the bit transfer rate of Data Format 3 if the SPI is the network master. If the SPI / MibSPI is configured as slave this field DOES NOT NEED to be.."
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hexmask.long.byte 0x8 11.--15. 1. "NU3,Reserved. Reads return '0' and writes have no effect."
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hexmask.long.word 0x8 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only. EPRESCALE_FMT2 determines the bit transfer rate of Data Format 2 if the SPI is the network master. If the SPI / MibSPI is configured as slave this field DOES NOT NEED to be.."
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line.long 0xC "ECCDIAG_CTRL,ECC Diagnostic Control register"
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hexmask.long 0xC 4.--31. 1. "NU,Reserved. Reads return '0' and writes have no effect."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits. 0101 : Diagnostic mode is enabled. Writes and reads from ECC bits allowed from the ECC address space. Refer to Section 9 for details on ECC/Parity address space. Others : Diagnostic mode is disabled. No.."
|
|
rgroup.long 0x144++0xB
|
|
line.long 0x0 "ECCDIAG_STAT,ECC Diagnostic Status register"
|
|
hexmask.long.word 0x0 18.--31. 1. "NU2,Reserved. Reads return '0' and writes have no effect."
|
|
newline
|
|
bitfld.long 0x0 17. "DEFLG1,Double bit error flag for RXRAM 1 - A double bit Error is detected for RXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A double bit Error is detected for RXRAM bank.."
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|
newline
|
|
bitfld.long 0x0 16. "DEFLG0,Double bit error flag for TXRAM 1 - A double bit Error is detected for TXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A double bit Error is detected for TXRAM bank.."
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "NU1,Reserved. Reads return '0' and writes have no effect."
|
|
newline
|
|
bitfld.long 0x0 1. "SEFLG1,Single bit error flag for RXRAM 1 - A Single bit Error is detected for RXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A Single bit Error is detected for RXRAM bank.."
|
|
newline
|
|
bitfld.long 0x0 0. "SEFLG0,Single bit error flag for TXRAM 1 - A Single bit Error is detected for TXRAM bank during diagnostic mode tests. 0 - No error. A write '1' to this bit will clear the bit." "0: No error,1: A Single bit Error is detected for TXRAM bank.."
|
|
line.long 0x4 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
|
|
hexmask.long.tbyte 0x4 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect."
|
|
newline
|
|
hexmask.long.word 0x4 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM. This error address is frozen from being updated until it is read by.."
|
|
line.long 0x8 "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
|
|
hexmask.long.tbyte 0x8 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect."
|
|
newline
|
|
hexmask.long.word 0x8 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM. The TXRAM can be read either by CPU or by the MibSPI Sequencer logic for.."
|
|
rgroup.long 0x1FC++0x3
|
|
line.long 0x0 "SPIREV,SPI / MibSPI Revision ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes. Reads 0x01" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "NU,Reserved.Reads return '0' and writes have no effect." "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL version number Read value will provide an approximate RTL revision number. The design release version can be obtained from the device specification"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision number Reads 0x8"
|
|
tree.end
|
|
tree "MSS_TOPRCM"
|
|
base ad:0x2140000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
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|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
repeat 3. (list 0x0 0x1 0x3)(list 0x0 0x4 0xC)
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "HW_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser. Reserved for HW RnD"
|
|
repeat.end
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PREVIOUS_NAME,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser. Reserved for HW RnD"
|
|
group.long 0x14++0x17
|
|
line.long 0x0 "HSI_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x0 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSI. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x4 "CSIRX_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x4 0.--11. 1. "clksrcsel,Select line for selecting source clock for CSI Rx Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x8 "MCUCLKOUT_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x8 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCU Clkout Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0xC "PMICCLKOUT_CLK_SRC_SEL,"
|
|
hexmask.long.word 0xC 0.--11. 1. "clksrcsel,Select line for selecting source clock for PMIC Clkout Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x10 "OBSCLKOUT_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for OBS Clkout Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x14 "TRCCLKOUT_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for TRC Clkout Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
group.long 0x44++0x13
|
|
line.long 0x0 "CSIRX_DIV_VAL,"
|
|
hexmask.long.word 0x0 0.--11. 1. "clkdiv,Divider value for CSI Rx selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x4 "MCUCLKOUT_DIV_VAL,"
|
|
hexmask.long.word 0x4 0.--11. 1. "clkdiv,Divider value for MCU Clkout selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x8 "PMICCLKOUT_DIV_VAL,"
|
|
hexmask.long.word 0x8 0.--11. 1. "clkdiv,Divider value for PMIC Clkout selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0xC "OBSCLKOUT_DIV_VAL,"
|
|
hexmask.long.word 0xC 0.--11. 1. "clkdiv,Divider value for OBS Clkout selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
line.long 0x10 "TRCCLKOUT_DIV_VAL,"
|
|
hexmask.long.word 0x10 0.--11. 1. "clkdiv,Divider value for TRC Clkout selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
|
|
group.long 0x84++0x17
|
|
line.long 0x0 "CSIRX_CLK_GATE,"
|
|
bitfld.long 0x0 0.--2. "gated,Clock gatring config for CSI Rx. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
|
|
line.long 0x4 "MCUCLKOUT_CLK_GATE,"
|
|
bitfld.long 0x4 0.--2. "gated,Clock gatring config for MCU Clkout. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
|
|
line.long 0x8 "PMICCLKOUT_CLK_GATE,"
|
|
bitfld.long 0x8 0.--2. "gated,Clock gatring config for PMIC Clkout Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
|
|
line.long 0xC "OBSCLKOUT_CLK_GATE,"
|
|
bitfld.long 0xC 0.--2. "gated,Clock gatring config for OBS Clkout Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
|
|
line.long 0x10 "TRCCLKOUT_CLK_GATE,"
|
|
bitfld.long 0x10 0.--2. "gated,Clock gatring config for TRC Clkout Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
|
|
line.long 0x14 "DSS_CLK_GATE,"
|
|
bitfld.long 0x14 0.--2. "gated,Clock gatring config for DSP Subsystem System Clock Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
|
|
rgroup.long 0xC0++0x17
|
|
line.long 0x0 "HSI_CLK_STATUS,"
|
|
hexmask.long.byte 0x0 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
|
|
line.long 0x4 "CSIRX_CLK_STATUS,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSI Clock"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "clkinuse,Status shows the source clock slected for HSI Clock"
|
|
line.long 0x8 "MCUCLKOUT_CLK_STATUS,"
|
|
hexmask.long.byte 0x8 8.--15. 1. "currdivider,Status shows the current divider value choosen for CSI Rx Clock"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "clkinuse,Status shows the source clock slected for CSI Rx Clock"
|
|
line.long 0xC "PMICCLKOUT_CLK_STATUS,"
|
|
hexmask.long.byte 0xC 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCU Clkout Clock"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "clkinuse,Status shows the source clock slected for MCU Clkout Clock"
|
|
line.long 0x10 "OBSCLKOUT_CLK_STATUS,"
|
|
hexmask.long.byte 0x10 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
|
|
line.long 0x14 "TRCCLKOUT_CLK_STATUS,"
|
|
hexmask.long.byte 0x14 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "WARM_RESET_CONFIG,"
|
|
bitfld.long 0x0 16.--18. "wdog_rst_en,Data should be loaded as multibit. Write 3'b000 to disable MSS Watchdog control on Warm reset Write 3'b111 enable MSS Watchdog to control Warm reset" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "sw_rst,Data should be loaded as multibit. Write 3'b000 to assert warm reset from SW Write 3'b111 to deassert warm reset from SW if this is the only source of warm reset" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "pad_bypass,Bypass the Warm reset from Pad Input Data should be loaded as multibit. Write 3'b000 : Reset is not asserted by SW (multibit 000) Write 3'b111 : Reset is asserted by SW (multibit 111)" "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x0 "SYS_RST_CAUSE,"
|
|
hexmask.long.byte 0x0 0.--4. 1. "cause,System Reset Cause register 5'b01001 - POR reset 5'b01010 - Warm reset due to MSS_WDT 5'b01100 - Warm reset due to TOP_RMC:WARM_RESET_CONFIG 5'b01000 - External Pad reset 5'b11000 - Warm reset due to HSM_WDT"
|
|
group.long 0x108++0x7
|
|
line.long 0x0 "SYS_RST_CAUSE_CLR,"
|
|
bitfld.long 0x0 0. "clear,Write pulse bit field: System Reset Cause register Clear" "0,1"
|
|
line.long 0x4 "DSS_RST_CTRL,"
|
|
bitfld.long 0x4 0.--2. "assert,Reset control for DSP Subsystem Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW (multibit 000) Write 3'b111 : Reset is asserted by SW (multibit 111)" "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
group.long 0x204++0x27
|
|
line.long 0x0 "RS232_BITINTERVAL,"
|
|
hexmask.long 0x0 0.--31. 1. "bitinterval,RS232 Bit Interval. 10 bit clock interval is selceted based on the value of RSS_CLK_SRC_SEL [9:0] used as RS232 Bit inteval when RSS_CLK_SRC_SEL = 0x0 [19:10] used as RS232 Bit inteval when RSS_CLK_SRC_SEL = 0x1 [29:20] used as RS232 Bit.."
|
|
line.long 0x4 "LVDS_PAD_CTRL0,"
|
|
hexmask.long 0x4 0.--31. 1. "ctrl,LVDS Pad Control 0 Register. Below is the mapping for each bit. Refer the LVDS IO Spec for more details Bit 0 : Power Down Control for LVDS CLK Lane Bit 1: LOPWRA Control for i LVDS CLK Lane Bit 2: LOPWRB Control for LVDS CLK Lane Bit 3 : LPSEL.."
|
|
line.long 0x8 "LVDS_PAD_CTRL1,"
|
|
hexmask.long 0x8 0.--31. 1. "ctlr,LVDS Pad Control 1 Register. Below is the mapping for each bit. Refer the LVDS IO Spec for more details Bit 0 : Power Down Control for LVDS DATA Lane 0 Bit 1: LOPWRA Control for i LVDS DATA Lane 0 Bit 2: LOPWRB Control for LVDS DATA Lane 0 Bit 3:.."
|
|
line.long 0xC "DFT_DMLED_EXEC,"
|
|
hexmask.long 0xC 0.--31. 1. "val,SW mapping for DMLED Execution Bit 0 : HSM CM4 Execution Bit 1 : HWA CM4 Execution Bit 2 : MSS CR5 Execution"
|
|
line.long 0x10 "DFT_DMLED_STATUS,"
|
|
hexmask.long 0x10 0.--31. 1. "val,SW mapping for DMLED Status Bit 0 : HSM CM4 Status Bit 1 : HWA CM4 Status Bit 2 : MSS CR5 Status"
|
|
line.long 0x14 "LIMP_MODE_EN,"
|
|
bitfld.long 0x14 8.--10. "force_rcclk_en,Force the RCCLK on when limp mode is detected 3'b000: The RCCLK will not be forced on when limp mode is detected (multibit 000) 3'b111 : The RCCLK will be forced on when limp mode is detected (multibit 111)" "0: The RCCLK will not be forced on when limp mode..,?,?,?,?,?,?,7: The RCCLK will be forced on when limp mode is.."
|
|
newline
|
|
bitfld.long 0x14 4.--6. "ccca_en,Enable MSS_CCCA Error to generate Limp mode 3'b000: MSS_CCCA Error will not generate Limp mode (multibit 000) 3'b111 : MSS_CCCA Error will generate Limp mode (multibit 111)" "0: MSS_CCCA Error will not generate Limp mode,?,?,?,?,?,?,7: MSS_CCCA Error will generate Limp mode"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "dcca_en,Enable MSS_DCCA Error to generate Limp mode 3'b000: MSS_DCCA Error will not generate Limp mode (multibit 000) 3'b111 : MSS_DCCA Error will generate Limp mode (multibit 111)" "0: MSS_DCCA Error will not generate Limp mode,?,?,?,?,?,?,7: MSS_DCCA Error will generate Limp mode"
|
|
line.long 0x18 "PMICCLKOUT_DCDC_CTRL,"
|
|
hexmask.long.byte 0x18 16.--23. 1. "max_freq_thr,PMIC Clockout DCDC Maximum Frequency Threshold"
|
|
newline
|
|
hexmask.long.byte 0x18 8.--15. 1. "min_freq_thr,PMIC Clockout DCDC Minimum Frequency Threshold"
|
|
newline
|
|
bitfld.long 0x18 4.--6. "reset_assert,Reset control for PMIC DCDC Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW (multibit 000) Write 3'b111 : Reset is asserted by SW (multibit 111)" "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
newline
|
|
bitfld.long 0x18 2. "freq_acc_mode,PMIC Clockout DCDC Freq Acc Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "dither_en,PMIC Clockout DCDC Clock Dither Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "dcdc_clk_en,PMIC Clockout DCDC Clock Enable" "0,1"
|
|
line.long 0x1C "PMICCLKOUT_DCDC_SLOPE,"
|
|
hexmask.long 0x1C 0.--26. 1. "slope_val,PMIC Clockout DCDC Slope Config Value"
|
|
line.long 0x20 "RCOSC32K_CTRL,"
|
|
bitfld.long 0x20 0.--2. "stoposc,Stop 32KHz RCOSC. Write 3'b111 to stop clock" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "ANA_HSI2DIGCLK_GATE,"
|
|
bitfld.long 0x24 0.--2. "gated,Clock gatring config for Analog HSI Clkout to Core GCms Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
|
|
group.long 0x400++0x23
|
|
line.long 0x0 "PLL_CORE_PWRCTRL,"
|
|
bitfld.long 0x0 5. "PONIN,ON/OFF control of the weak power switch digital. For functional mode it should be 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PGOODIN,ON/OFF control of the strong power switch digital. For functional mode it should be 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RET,Save/Restore control for Retention mode. For functional mode it should be 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins. For functional mode it should be 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "OFFMODE,Used to switch OFF the logic on VDDA. For functional mode it should be 0" "0,1"
|
|
line.long 0x4 "PLL_CORE_CLKCTRL,"
|
|
bitfld.long 0x4 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "ENSSC,Controls Clock Spreading. SSC is not supported. Should be set to 0x0 to disable clock spreading." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO 0x0 : synchronously disables CLKDCOLDO 0x1 : synchronously enables CLKDCOLDO" "0: synchronously disables CLKDCOLDO 0x1 :..,?"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--28. 1. "NWELLTRIM,Trim value for the PLL"
|
|
newline
|
|
bitfld.long 0x4 23. "IDLE,Sets PLL to Idle mode 0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go to Active and Locked 0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go to Idle Bypass low powe" "0: When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,?"
|
|
newline
|
|
bitfld.long 0x4 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module. In general this input is expected to be tied to static low. For the output clocks of the module that do not have an internal bypass mux viz. CLKDCOLDO and CLKOUTLDO a bypass mux could be.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "STBYRET,Standby retention control 0x0 : prepares ADPLLLJ for relock when out of retention by removing the gating on all internal clocks. 0x1 : prepares ADPLLLJ for retention by gating all the internal clocks." "0: prepares ADPLLLJ for relock when out of..,1: prepares ADPLLLJ for retention by gating all the.."
|
|
newline
|
|
bitfld.long 0x4 20. "CLKOUTEN,CLKOUT enable or disable 0x0 : synchronously disables CLKOUT 0x1 : synchronously enables CLKOUT" "0: synchronously disables CLKOUT 0x1 :..,?"
|
|
newline
|
|
rbitfld.long 0x4 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO" "0: synchronously disables CLKOUTLDO 0x1 :..,?"
|
|
newline
|
|
bitfld.long 0x4 18. "ULOWCLKEN,Select CLKOUT source in bypass 0x0: When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1) 0x1: When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW." "0: When ADPLLLJ in bypass mode,1: When ADPLLLJ in bypass mode"
|
|
newline
|
|
bitfld.long 0x4 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "M2PWDNZ,M2 divider power down mode 0x0: Asynchronous power down for M2 divider 0x1 : M2 divider is functional" "0: Asynchronous power down for M2 divider 0x1 : M2..,?"
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newline
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bitfld.long 0x4 14. "STOPMODE,When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode" "0: Limp mode 0x1 : Stopmode,?"
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newline
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bitfld.long 0x4 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector. 0x0: Reserved 0x2: HS2 : DCOCLK range is from 500 MHz to 1000 MHz 0x3: Reserved 0x4: HS1: DCOCLK range is from 1000 MHz to 2000 MHz 0x5: Reserved" "0: Reserved 0x2: HS2 : DCOCLK range is from 500 MHz..,?,?,?,?,?,?,?"
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newline
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bitfld.long 0x4 8. "RELAXED_LOCK,Decides when FREQLOCK asserted 0x0: FREQLOCK asserted when DC frequency error less than 1% 0x1: FREQLOCK asserted when DC frequency error less than 2%" "0: FREQLOCK asserted when DC frequency error less..,?"
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newline
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bitfld.long 0x4 1. "SSCTYPE,SSC Type" "0,1"
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newline
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bitfld.long 0x4 0. "TINTZ,PLL core soft reset" "0,1"
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line.long 0x8 "PLL_CORE_TENABLE,"
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bitfld.long 0x8 0. "TENABLE,M N. SD and SELFREQDCO latch (active rise edge)" "0,1"
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line.long 0xC "PLL_CORE_TENABLEDIV,"
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bitfld.long 0xC 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
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line.long 0x10 "PLL_CORE_M2NDIV,"
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hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
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line.long 0x14 "PLL_CORE_MN2DIV,"
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hexmask.long.byte 0x14 16.--19. 1. "N2,Bypass divider is REGN2+1"
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newline
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hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
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line.long 0x18 "PLL_CORE_FRACDIV,"
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hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP/ 250) where CLKINP is the input clock of the DPLL in MHz"
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newline
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hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider."
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line.long 0x1C "PLL_CORE_BWCTRL,"
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bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
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newline
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bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth 0x0 : decrease BW 0x1 : increase BW" "0: decrease BW 0x1 : increase BW,?"
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line.long 0x20 "PLL_CORE_FRACCTRL,"
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bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread 0x0 : enables both side frequency spread about the programmed frequency. 0x1 : enables low frequency spread only" "0: enables both side frequency spread about the..,1: enables low frequency spread only"
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newline
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bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency." "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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newline
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bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
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rgroup.long 0x424++0x3
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line.long 0x0 "PLL_CORE_STATUS,"
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bitfld.long 0x0 31. "PONOUT,Status of the weak power-switch 0x0 : indicates the/OFF status of the weak power-switch in digital to SOC. 0x1 : ndicates the ON status of the weak power-switch in digital to SOC." "0: indicates the/OFF status of the weak..,1: ndicates the ON status of the weak power-switch.."
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newline
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bitfld.long 0x0 30. "PGOODOUT,Status of the strong power-switch 0x0 : indicates the/OFF status of the strong power-switch in digital to SOC. 0x1 : ndicates the ON status of the strong power-switch in digital to SOC." "0: indicates the/OFF status of the strong..,1: ndicates the ON status of the strong.."
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newline
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bitfld.long 0x0 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT will be un-defined in this condition" "0,1"
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newline
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bitfld.long 0x0 28. "RECAL_BSTATUS3,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1"
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newline
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bitfld.long 0x0 27. "RECAL_OPPIN,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1"
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newline
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bitfld.long 0x0 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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newline
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bitfld.long 0x0 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
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newline
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bitfld.long 0x0 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
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newline
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bitfld.long 0x0 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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newline
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bitfld.long 0x0 7. "STBYRETACK,Standby and retention status 0x0: indicates to SOC that all internal clocks in ADPLLLJ are active and it is starting the relock process. 0x1: indicates to SOC that all internal clocks in ADPLLLJ are gated and it is ready for retention." "0: indicates to SOC that all internal clocks in..,1: indicates to SOC that all internal clocks in.."
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newline
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bitfld.long 0x0 6. "LOSSREF,Reference input loss" "0,1"
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newline
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bitfld.long 0x0 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN 0x0 = CLKOUT gating completed 0x1 = CLKOUT enabling completed" "0: CLKOUT gating completed 0x1 = CLKOUT enabling..,?"
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newline
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bitfld.long 0x0 4. "LOCK2,ADPLL internal loop lock status" "0,1"
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newline
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bitfld.long 0x0 3. "M2CHANGEACK,Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1 (depending on current value) once CLKOUT frequency change has completed." "0,1"
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newline
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bitfld.long 0x0 2. "SSCACK,Spread Spectrum status 0x0 : Spread-spectrum Clocking is disabled on output clocks 0x1 : Spread-spectrum Clocking is enabled on output clocks" "0: Spread-spectrum Clocking is disabled on output..,?"
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newline
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bitfld.long 0x0 1. "HIGHJITTER,1 indicates jitter. After PHASELOCK is asserted high the HIGHJITTER flag is asserted high if phase error between REFCLK and FBCLK greater than 24%." "0,1"
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newline
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bitfld.long 0x0 0. "BYPASS,Bypass status signal. 1 CLKOUT in bypass" "0,1"
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group.long 0x428++0x27
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line.long 0x0 "PLL_CORE_HSDIVIDER,"
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rbitfld.long 0x0 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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newline
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rbitfld.long 0x0 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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newline
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bitfld.long 0x0 2. "TENABLEDIV,Tenable Div" "0,1"
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newline
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bitfld.long 0x0 1. "LDOPWDN,LDO Power Down" "0,1"
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newline
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bitfld.long 0x0 0. "BYPASS,HSDIVIDER Bypass" "0,1"
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line.long 0x4 "PLL_CORE_HSDIVIDER_CLKOUT0,"
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bitfld.long 0x4 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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newline
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rbitfld.long 0x4 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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newline
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bitfld.long 0x4 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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newline
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rbitfld.long 0x4 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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newline
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hexmask.long.byte 0x4 0.--4. 1. "DIV,DPLL post-divider factor M4 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x8 "PLL_CORE_HSDIVIDER_CLKOUT1,"
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bitfld.long 0x8 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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newline
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rbitfld.long 0x8 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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newline
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bitfld.long 0x8 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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newline
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rbitfld.long 0x8 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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newline
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hexmask.long.byte 0x8 0.--4. 1. "DIV,DPLL post-divider factor M5 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0xC "PLL_CORE_HSDIVIDER_CLKOUT2,"
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bitfld.long 0xC 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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newline
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rbitfld.long 0xC 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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newline
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bitfld.long 0xC 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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newline
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rbitfld.long 0xC 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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newline
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hexmask.long.byte 0xC 0.--4. 1. "DIV,DPLL post-divider factor M6 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x10 "PLL_CORE_HSDIVIDER_CLKOUT3,"
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bitfld.long 0x10 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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newline
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rbitfld.long 0x10 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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newline
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bitfld.long 0x10 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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newline
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rbitfld.long 0x10 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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newline
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hexmask.long.byte 0x10 0.--4. 1. "DIV,DPLL post-divider factor M7 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x14 "MSS_CR5_CLK_SRC_SEL,"
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hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for MSS Coretex R5 and System bus Clock. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec.."
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line.long 0x18 "MSS_CR5_DIV_VAL,"
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hexmask.long.word 0x18 0.--11. 1. "clkdiv,Divider value for Cortex R5 selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
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line.long 0x1C "SYS_CLK_DIV_VAL,"
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hexmask.long.word 0x1C 0.--11. 1. "clkdiv,Divider value for System Clock selected clock. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
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line.long 0x20 "MSS_CR5_CLK_GATE,"
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bitfld.long 0x20 0.--2. "gated,Clock gatring config for MSS Coretex R5. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
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line.long 0x24 "SYS_CLK_GATE,"
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bitfld.long 0x24 0.--2. "gated,Clock gatring config for System Clock Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
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rgroup.long 0x450++0x7
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line.long 0x0 "SYS_CLK_STATUS,"
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hexmask.long.byte 0x0 8.--15. 1. "currdivider,Status shows the current divider value choosen for Sys Clock"
|
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line.long 0x4 "MSS_CR5_CLK_STATUS,"
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hexmask.long.byte 0x4 8.--15. 1. "currdivider,Status shows the current divider value choosen for CortexR5 Clock"
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|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
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group.long 0x458++0x33
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line.long 0x0 "PLL_CORE_RSTCTRL,"
|
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bitfld.long 0x0 0.--2. "assert,SW Reset override for the PLL Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
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line.long 0x4 "PLL_CORE_HSDIVIDER_RSTCTRL,"
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bitfld.long 0x4 0.--2. "assert,SW Reset override for the HSDIVIDER Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
|
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line.long 0x8 "RSS_CLK_SRC_SEL,"
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hexmask.long.word 0x8 0.--11. 1. "clksrcsel,Select line for selecting source clock for RSS Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source clock reference"
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line.long 0xC "PLLC_CLK2_SRC_SEL,"
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hexmask.long.word 0xC 0.--11. 1. "clksrcsel,Select line for selecting source clock for for PLLCORE_HSDIV_CLKOUT2_MUXED Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for.."
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line.long 0x10 "PLLD_CLK1_SRC_SEL,"
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hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for PLLDSP_HSDIV_CLKOUT1_MUXED Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for.."
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line.long 0x14 "PLLD_CLK2_SRC_SEL,"
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hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for PLLDSP_HSDIV_CLKOUT2_MUXED. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for.."
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line.long 0x18 "PLLP_CLK1_SRC_SEL,"
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hexmask.long.word 0x18 0.--11. 1. "clksrcsel,Select line for selecting source clock for PLLPER_HSDIV_CLKOUT1_MUXED Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. Refer to TPR12 clock spec for source.."
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line.long 0x1C "RSS_DIV_VAL,"
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hexmask.long.word 0x1C 0.--11. 1. "clkdiv,Divider value for RSS. Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register."
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line.long 0x20 "RSS_CLK_GATE,"
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bitfld.long 0x20 0.--2. "gated,Clock gatring config for RSS. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
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line.long 0x24 "PLLC_CLK2_GATE,"
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bitfld.long 0x24 0.--2. "gated,Clock gatring config for PLLCORE_HSDIV_CLKOUT2_MUXED. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
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line.long 0x28 "PLLD_CLK1_GATE,"
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|
bitfld.long 0x28 0.--2. "gated,Clock gatring config for PLLDSP_HSDIV_CLKOUT1_MUXED.. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
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line.long 0x2C "PLLD_CLK2_GATE,"
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bitfld.long 0x2C 0.--2. "gated,Clock gatring config for PLLDSP_HSDIV_CLKOUT2_MUXED. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
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line.long 0x30 "PLLP_CLK1_GATE,"
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|
bitfld.long 0x30 0.--2. "gated,Clock gatring config for PLLPER_HSDIV_CLKOUT1_MUXED. Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000) Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated"
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|
rgroup.long 0x48C++0x13
|
|
line.long 0x0 "RSS_CLK_STATUS,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RSS"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "clkinuse,Status shows the source clock slected for RSS"
|
|
line.long 0x4 "PLLC_CLK2_STATUS,"
|
|
hexmask.long.byte 0x4 0.--7. 1. "clkinuse,Status shows the source clock slected for GCM switch for PLLCORE_HSDIV_CLK2"
|
|
line.long 0x8 "PLLD_CLK1_STATUS,"
|
|
hexmask.long.byte 0x8 0.--7. 1. "clkinuse,Status shows the source clock slected for GCM switch for PLLDSP_HSDIV_CLK1"
|
|
line.long 0xC "PLLD_CLK2_STATUS,"
|
|
hexmask.long.byte 0xC 0.--7. 1. "clkinuse,Status shows the source clock slected for GCM switch for PLLDSP_HSDIV_CLK2"
|
|
line.long 0x10 "PLLP_CLK1_STATUS,"
|
|
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for GCM switch for PLLPER_HSDIV_CLK1"
|
|
group.long 0x4A0++0x2F
|
|
line.long 0x0 "PLL_1P2_HSDIVIDER,"
|
|
rbitfld.long 0x0 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TENABLEDIV,Tenable Div" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LDOPWDN,LDO Power Down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BYPASS,HSDIVIDER Bypass" "0,1"
|
|
line.long 0x4 "PLL_1P2_HSDIVIDER_CLKOUT0,"
|
|
bitfld.long 0x4 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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|
newline
|
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rbitfld.long 0x4 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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newline
|
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rbitfld.long 0x4 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 0.--4. 1. "DIV,DPLL post-divider factor M4 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
|
|
line.long 0x8 "PLL_1P2_HSDIVIDER_CLKOUT1,"
|
|
bitfld.long 0x8 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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|
newline
|
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rbitfld.long 0x8 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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|
newline
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rbitfld.long 0x8 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x8 0.--4. 1. "DIV,DPLL post-divider factor M5 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0xC "PLL_1P2_HSDIVIDER_CLKOUT2,"
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bitfld.long 0xC 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0xC 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0xC 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0xC 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0xC 0.--4. 1. "DIV,DPLL post-divider factor M6 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x10 "PLL_1P2_HSDIVIDER_CLKOUT3,"
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bitfld.long 0x10 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x10 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x10 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x10 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "DIV,DPLL post-divider factor M7 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x14 "PLL_1P2_HSDIVIDER_RSTCTRL,"
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bitfld.long 0x14 0.--2. "assert,SW Reset override for the HSDIVIDER Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
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line.long 0x18 "PLL_1P8_HSDIVIDER,"
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rbitfld.long 0x18 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x18 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x18 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x18 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x18 0. "BYPASS,HSDIVIDER Bypass" "0,1"
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line.long 0x1C "PLL_1P8_HSDIVIDER_CLKOUT0,"
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bitfld.long 0x1C 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x1C 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x1C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x1C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x1C 0.--4. 1. "DIV,DPLL post-divider factor M4 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x20 "PLL_1P8_HSDIVIDER_CLKOUT1,"
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bitfld.long 0x20 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x20 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x20 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x20 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x20 0.--4. 1. "DIV,DPLL post-divider factor M5 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x24 "PLL_1P8_HSDIVIDER_CLKOUT2,"
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bitfld.long 0x24 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0x24 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x24 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x24 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x24 0.--4. 1. "DIV,DPLL post-divider factor M6 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x28 "PLL_1P8_HSDIVIDER_CLKOUT3,"
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bitfld.long 0x28 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x28 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x28 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x28 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x28 0.--4. 1. "DIV,DPLL post-divider factor M7 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x2C "PLL_1P8_HSDIVIDER_RSTCTRL,"
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bitfld.long 0x2C 0.--2. "assert,SW Reset override for the HSDIVIDER Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
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group.long 0x800++0x23
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line.long 0x0 "PLL_DSP_PWRCTRL,"
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bitfld.long 0x0 5. "PONIN,ON/OFF control of the weak power switch digital. For functional mode it should be 1" "0,1"
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bitfld.long 0x0 4. "PGOODIN,ON/OFF control of the strong power switch digital. For functional mode it should be 1" "0,1"
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bitfld.long 0x0 3. "RET,Save/Restore control for Retention mode. For functional mode it should be 0" "0,1"
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bitfld.long 0x0 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
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bitfld.long 0x0 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins. For functional mode it should be 0" "0,1"
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bitfld.long 0x0 0. "OFFMODE,Used to switch OFF the logic on VDDA. For functional mode it should be 0" "0,1"
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line.long 0x4 "PLL_DSP_CLKCTRL,"
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bitfld.long 0x4 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK." "0,1"
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bitfld.long 0x4 30. "ENSSC,Controls Clock Spreading. SSC is not supported. Should be set to 0x0 to disable clock spreading." "0,1"
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bitfld.long 0x4 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO 0x0 : synchronously disables CLKDCOLDO 0x1 : synchronously enables CLKDCOLDO" "0: synchronously disables CLKDCOLDO 0x1 :..,?"
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hexmask.long.byte 0x4 24.--28. 1. "NWELLTRIM,Trim value for the PLL"
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bitfld.long 0x4 23. "IDLE,Sets PLL to Idle mode 0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go to Active and Locked 0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go to Idle Bypass low powe" "0: When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,?"
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bitfld.long 0x4 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module. In general this input is expected to be tied to static low. For the output clocks of the module that do not have an internal bypass mux viz. CLKDCOLDO and CLKOUTLDO a bypass mux could be.." "0,1"
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bitfld.long 0x4 21. "STBYRET,Standby retention control 0x0 : prepares ADPLLLJ for relock when out of retention by removing the gating on all internal clocks. 0x1 : prepares ADPLLLJ for retention by gating all the internal clocks." "0: prepares ADPLLLJ for relock when out of..,1: prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x4 20. "CLKOUTEN,CLKOUT enable or disable 0x0 : synchronously disables CLKOUT 0x1 : synchronously enables CLKOUT" "0: synchronously disables CLKOUT 0x1 :..,?"
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rbitfld.long 0x4 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO" "0: synchronously disables CLKOUTLDO 0x1 :..,?"
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bitfld.long 0x4 18. "ULOWCLKEN,Select CLKOUT source in bypass 0x0: When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1) 0x1: When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW." "0: When ADPLLLJ in bypass mode,1: When ADPLLLJ in bypass mode"
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bitfld.long 0x4 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p." "0,1"
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bitfld.long 0x4 16. "M2PWDNZ,M2 divider power down mode 0x0: Asynchronous power down for M2 divider 0x1 : M2 divider is functional" "0: Asynchronous power down for M2 divider 0x1 : M2..,?"
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bitfld.long 0x4 14. "STOPMODE,When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode" "0: Limp mode 0x1 : Stopmode,?"
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bitfld.long 0x4 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector. 0x0: Reserved 0x2: HS2 : DCOCLK range is from 500 MHz to 1000 MHz 0x3: Reserved 0x4: HS1: DCOCLK range is from 1000 MHz to 2000 MHz 0x5: Reserved" "0: Reserved 0x2: HS2 : DCOCLK range is from 500 MHz..,?,?,?,?,?,?,?"
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bitfld.long 0x4 8. "RELAXED_LOCK,Decides when FREQLOCK asserted 0x0: FREQLOCK asserted when DC frequency error less than 1% 0x1: FREQLOCK asserted when DC frequency error less than 2%" "0: FREQLOCK asserted when DC frequency error less..,?"
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bitfld.long 0x4 1. "SSCTYPE,SSC Type" "0,1"
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bitfld.long 0x4 0. "TINTZ,PLL core soft reset" "0,1"
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line.long 0x8 "PLL_DSP_TENABLE,"
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bitfld.long 0x8 0. "TENABLE,M N. SD and SELFREQDCO latch (active rise edge)" "0,1"
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line.long 0xC "PLL_DSP_TENABLEDIV,"
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bitfld.long 0xC 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
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line.long 0x10 "PLL_DSP_M2NDIV,"
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hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
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hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
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line.long 0x14 "PLL_DSP_MN2DIV,"
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hexmask.long.byte 0x14 16.--19. 1. "N2,Bypass divider is REGN2+1"
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newline
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hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
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line.long 0x18 "PLL_DSP_FRACDIV,"
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hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP/ 250) where CLKINP is the input clock of the DPLL in MHz"
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hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider."
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line.long 0x1C "PLL_DSP_BWCTRL,"
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bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
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newline
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bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth 0x0 : decrease BW 0x1 : increase BW" "0: decrease BW 0x1 : increase BW,?"
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line.long 0x20 "PLL_DSP_FRACCTRL,"
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bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread 0x0 : enables both side frequency spread about the programmed frequency. 0x1 : enables low frequency spread only" "0: enables both side frequency spread about the..,1: enables low frequency spread only"
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bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
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rgroup.long 0x824++0x3
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line.long 0x0 "PLL_DSP_STATUS,"
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bitfld.long 0x0 31. "PONOUT,Status of the weak power-switch 0x0 : indicates the/OFF status of the weak power-switch in digital to SOC. 0x1 : ndicates the ON status of the weak power-switch in digital to SOC." "0: indicates the/OFF status of the weak..,1: ndicates the ON status of the weak power-switch.."
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newline
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bitfld.long 0x0 30. "PGOODOUT,Status of the strong power-switch 0x0 : indicates the/OFF status of the strong power-switch in digital to SOC. 0x1 : ndicates the ON status of the strong power-switch in digital to SOC." "0: indicates the/OFF status of the strong..,1: ndicates the ON status of the strong.."
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newline
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bitfld.long 0x0 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT will be un-defined in this condition" "0,1"
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bitfld.long 0x0 28. "RECAL_BSTATUS3,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1"
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newline
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bitfld.long 0x0 27. "RECAL_OPPIN,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1"
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bitfld.long 0x0 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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newline
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bitfld.long 0x0 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x0 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
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bitfld.long 0x0 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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newline
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bitfld.long 0x0 7. "STBYRETACK,Standby and retention status 0x0: indicates to SOC that all internal clocks in ADPLLLJ are active and it is starting the relock process. 0x1: indicates to SOC that all internal clocks in ADPLLLJ are gated and it is ready for retention." "0: indicates to SOC that all internal clocks in..,1: indicates to SOC that all internal clocks in.."
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bitfld.long 0x0 6. "LOSSREF,Reference input loss" "0,1"
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bitfld.long 0x0 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN 0x0 = CLKOUT gating completed 0x1 = CLKOUT enabling completed" "0: CLKOUT gating completed 0x1 = CLKOUT enabling..,?"
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bitfld.long 0x0 4. "LOCK2,ADPLL internal loop lock status" "0,1"
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bitfld.long 0x0 3. "M2CHANGEACK,Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1 (depending on current value) once CLKOUT frequency change has completed." "0,1"
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bitfld.long 0x0 2. "SSCACK,Spread Spectrum status 0x0 : Spread-spectrum Clocking is disabled on output clocks 0x1 : Spread-spectrum Clocking is enabled on output clocks" "0: Spread-spectrum Clocking is disabled on output..,?"
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bitfld.long 0x0 1. "HIGHJITTER,1 indicates jitter. After PHASELOCK is asserted high the HIGHJITTER flag is asserted high if phase error between REFCLK and FBCLK greater than 24%." "0,1"
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newline
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bitfld.long 0x0 0. "BYPASS,Bypass status signal. 1 CLKOUT in bypass" "0,1"
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group.long 0x828++0x37
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line.long 0x0 "PLL_DSP_HSDIVIDER,"
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rbitfld.long 0x0 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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newline
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rbitfld.long 0x0 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x0 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x0 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x0 0. "BYPASS,HSDIVIDER Bypass" "0,1"
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line.long 0x4 "PLL_DSP_HSDIVIDER_CLKOUT0,"
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bitfld.long 0x4 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x4 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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newline
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bitfld.long 0x4 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x4 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x4 0.--4. 1. "DIV,DPLL post-divider factor M4 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x8 "PLL_DSP_HSDIVIDER_CLKOUT1,"
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bitfld.long 0x8 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x8 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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newline
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bitfld.long 0x8 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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newline
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rbitfld.long 0x8 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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newline
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hexmask.long.byte 0x8 0.--4. 1. "DIV,DPLL post-divider factor M5 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0xC "PLL_DSP_HSDIVIDER_CLKOUT2,"
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bitfld.long 0xC 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0xC 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0xC 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0xC 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0xC 0.--4. 1. "DIV,DPLL post-divider factor M6 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x10 "PLL_DSP_HSDIVIDER_CLKOUT3,"
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bitfld.long 0x10 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x10 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x10 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x10 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "DIV,DPLL post-divider factor M7 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x14 "PLL_PER_PWRCTRL,"
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bitfld.long 0x14 5. "PONIN,ON/OFF control of the weak power switch digital. For functional mode it should be 1" "0,1"
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bitfld.long 0x14 4. "PGOODIN,ON/OFF control of the strong power switch digital. For functional mode it should be 1" "0,1"
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bitfld.long 0x14 3. "RET,Save/Restore control for Retention mode. For functional mode it should be 0" "0,1"
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bitfld.long 0x14 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
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bitfld.long 0x14 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins. For functional mode it should be 0" "0,1"
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bitfld.long 0x14 0. "OFFMODE,Used to switch OFF the logic on VDDA. For functional mode it should be 0" "0,1"
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line.long 0x18 "PLL_PER_CLKCTRL,"
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bitfld.long 0x18 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK." "0,1"
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bitfld.long 0x18 30. "ENSSC,Controls Clock Spreading. SSC is not supported. Should be set to 0x0 to disable clock spreading." "0,1"
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bitfld.long 0x18 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO 0x0 : synchronously disables CLKDCOLDO 0x1 : synchronously enables CLKDCOLDO" "0: synchronously disables CLKDCOLDO 0x1 :..,?"
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hexmask.long.byte 0x18 24.--28. 1. "NWELLTRIM,Trim value for the PLL"
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bitfld.long 0x18 23. "IDLE,Sets PLL to Idle mode 0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go to Active and Locked 0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go to Idle Bypass low powe" "0: When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,?"
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bitfld.long 0x18 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module. In general this input is expected to be tied to static low. For the output clocks of the module that do not have an internal bypass mux viz. CLKDCOLDO and CLKOUTLDO a bypass mux could be.." "0,1"
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bitfld.long 0x18 21. "STBYRET,Standby retention control 0x0 : prepares ADPLLLJ for relock when out of retention by removing the gating on all internal clocks. 0x1 : prepares ADPLLLJ for retention by gating all the internal clocks." "0: prepares ADPLLLJ for relock when out of..,1: prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x18 20. "CLKOUTEN,CLKOUT enable or disable 0x0 : synchronously disables CLKOUT 0x1 : synchronously enables CLKOUT" "0: synchronously disables CLKOUT 0x1 :..,?"
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rbitfld.long 0x18 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO" "0: synchronously disables CLKOUTLDO 0x1 :..,?"
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bitfld.long 0x18 18. "ULOWCLKEN,Select CLKOUT source in bypass 0x0: When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1) 0x1: When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW." "0: When ADPLLLJ in bypass mode,1: When ADPLLLJ in bypass mode"
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bitfld.long 0x18 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p." "0,1"
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bitfld.long 0x18 16. "M2PWDNZ,M2 divider power down mode 0x0: Asynchronous power down for M2 divider 0x1 : M2 divider is functional" "0: Asynchronous power down for M2 divider 0x1 : M2..,?"
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bitfld.long 0x18 14. "STOPMODE,When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode" "0: Limp mode 0x1 : Stopmode,?"
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bitfld.long 0x18 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector. 0x0: Reserved 0x2: HS2 : DCOCLK range is from 500 MHz to 1000 MHz 0x3: Reserved 0x4: HS1: DCOCLK range is from 1000 MHz to 2000 MHz 0x5: Reserved" "0: Reserved 0x2: HS2 : DCOCLK range is from 500 MHz..,?,?,?,?,?,?,?"
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bitfld.long 0x18 8. "RELAXED_LOCK,Decides when FREQLOCK asserted 0x0: FREQLOCK asserted when DC frequency error less than 1% 0x1: FREQLOCK asserted when DC frequency error less than 2%" "0: FREQLOCK asserted when DC frequency error less..,?"
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bitfld.long 0x18 1. "SSCTYPE,SSC Type" "0,1"
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bitfld.long 0x18 0. "TINTZ,PLL core soft reset" "0,1"
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line.long 0x1C "PLL_PER_TENABLE,"
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bitfld.long 0x1C 0. "TENABLE,M N. SD and SELFREQDCO latch (active rise edge)" "0,1"
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line.long 0x20 "PLL_PER_TENABLEDIV,"
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bitfld.long 0x20 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
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line.long 0x24 "PLL_PER_M2NDIV,"
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hexmask.long.byte 0x24 16.--22. 1. "M2,Post-divider is REGM2"
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hexmask.long.byte 0x24 0.--7. 1. "N,Pre-divider is REGN+1"
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line.long 0x28 "PLL_PER_MN2DIV,"
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hexmask.long.byte 0x28 16.--19. 1. "N2,Bypass divider is REGN2+1"
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hexmask.long.word 0x28 0.--11. 1. "M,Feedback Multiplier is REGM"
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line.long 0x2C "PLL_PER_FRACDIV,"
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hexmask.long.byte 0x2C 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP/ 250) where CLKINP is the input clock of the DPLL in MHz"
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hexmask.long.tbyte 0x2C 0.--17. 1. "FRACTIONALM,Fractional part of the M divider."
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line.long 0x30 "PLL_PER_BWCTRL,"
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bitfld.long 0x30 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
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bitfld.long 0x30 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth 0x0 : decrease BW 0x1 : increase BW" "0: decrease BW 0x1 : increase BW,?"
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line.long 0x34 "PLL_PER_FRACCTRL,"
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bitfld.long 0x34 31. "DOWNSPREAD,Controls frequency spread 0x0 : enables both side frequency spread about the programmed frequency. 0x1 : enables low frequency spread only" "0: enables both side frequency spread about the..,1: enables low frequency spread only"
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bitfld.long 0x34 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x34 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x34 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x34 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
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rgroup.long 0x860++0x3
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line.long 0x0 "PLL_PER_STATUS,"
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bitfld.long 0x0 31. "PONOUT,Status of the weak power-switch 0x0 : indicates the/OFF status of the weak power-switch in digital to SOC. 0x1 : ndicates the ON status of the weak power-switch in digital to SOC." "0: indicates the/OFF status of the weak..,1: ndicates the ON status of the weak power-switch.."
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bitfld.long 0x0 30. "PGOODOUT,Status of the strong power-switch 0x0 : indicates the/OFF status of the strong power-switch in digital to SOC. 0x1 : ndicates the ON status of the strong power-switch in digital to SOC." "0: indicates the/OFF status of the strong..,1: ndicates the ON status of the strong.."
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bitfld.long 0x0 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT will be un-defined in this condition" "0,1"
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bitfld.long 0x0 28. "RECAL_BSTATUS3,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1"
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bitfld.long 0x0 27. "RECAL_OPPIN,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1"
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bitfld.long 0x0 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x0 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x0 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
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bitfld.long 0x0 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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bitfld.long 0x0 7. "STBYRETACK,Standby and retention status 0x0: indicates to SOC that all internal clocks in ADPLLLJ are active and it is starting the relock process. 0x1: indicates to SOC that all internal clocks in ADPLLLJ are gated and it is ready for retention." "0: indicates to SOC that all internal clocks in..,1: indicates to SOC that all internal clocks in.."
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bitfld.long 0x0 6. "LOSSREF,Reference input loss" "0,1"
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bitfld.long 0x0 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN 0x0 = CLKOUT gating completed 0x1 = CLKOUT enabling completed" "0: CLKOUT gating completed 0x1 = CLKOUT enabling..,?"
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bitfld.long 0x0 4. "LOCK2,ADPLL internal loop lock status" "0,1"
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bitfld.long 0x0 3. "M2CHANGEACK,Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1 (depending on current value) once CLKOUT frequency change has completed." "0,1"
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bitfld.long 0x0 2. "SSCACK,Spread Spectrum status 0x0 : Spread-spectrum Clocking is disabled on output clocks 0x1 : Spread-spectrum Clocking is enabled on output clocks" "0: Spread-spectrum Clocking is disabled on output..,?"
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bitfld.long 0x0 1. "HIGHJITTER,1 indicates jitter. After PHASELOCK is asserted high the HIGHJITTER flag is asserted high if phase error between REFCLK and FBCLK greater than 24%." "0,1"
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bitfld.long 0x0 0. "BYPASS,Bypass status signal. 1 CLKOUT in bypass" "0,1"
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group.long 0x864++0x23
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line.long 0x0 "PLL_PER_HSDIVIDER,"
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rbitfld.long 0x0 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x0 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x0 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x0 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x0 0. "BYPASS,HSDIVIDER Bypass" "0,1"
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line.long 0x4 "PLL_PER_HSDIVIDER_CLKOUT0,"
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bitfld.long 0x4 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x4 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x4 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x4 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x4 0.--4. 1. "DIV,DPLL post-divider factor M4 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x8 "PLL_PER_HSDIVIDER_CLKOUT1,"
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bitfld.long 0x8 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x8 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x8 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x8 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x8 0.--4. 1. "DIV,DPLL post-divider factor M5 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0xC "PLL_PER_HSDIVIDER_CLKOUT2,"
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bitfld.long 0xC 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0xC 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0xC 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0xC 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0xC 0.--4. 1. "DIV,DPLL post-divider factor M6 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x10 "PLL_PER_HSDIVIDER_CLKOUT3,"
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bitfld.long 0x10 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x10 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x10 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x10 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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hexmask.long.byte 0x10 0.--4. 1. "DIV,DPLL post-divider factor M7 for internal clock generation. Divide values from 1 to 31. 0h (R/W) = Reserved"
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line.long 0x14 "PLL_DSP_RSTCTRL,"
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bitfld.long 0x14 0.--2. "assert,SW Reset override for the PLL Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
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line.long 0x18 "PLL_DSP_HSDIVIDER_RSTCTRL,"
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bitfld.long 0x18 0.--2. "assert,SW Reset override for the HSDIVIDER Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
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line.long 0x1C "PLL_PER_RSTCTRL,"
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bitfld.long 0x1C 0.--2. "assert,SW Reset override for the PLL Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
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line.long 0x20 "PLL_PER_HSDIVIDER_RSTCTRL,"
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bitfld.long 0x20 0.--2. "assert,SW Reset override for the HSDIVIDER Write 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted"
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group.long 0xC00++0x13
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line.long 0x0 "ANA_REG_CLK_CTRL_REG1_XO_SLICER,"
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hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset"
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bitfld.long 0x0 14. "SLICER_APLL_BYPASS_DRV,Slicer APLL Bypass Drive This bit controls the drive strength of the APLL Bypass Slicer 0 = Low-power drive 1 = High-power drive 0x0 = Functional Reset" "0: Low-power drive,1: High-power drive 0x0 = Functional Reset"
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bitfld.long 0x0 13. "SLICER_APLL_BYPASS,Slicer APLL Bypass This bit enables a high-speed slicer connected to CLKM which can be used to drive a high-speed clock directly as the SYNTH reference clock. 0 = Normal operation (bypass slicer disabled) 1 = APLL Bypass Slicer Enabled.." "0: Normal operation,1: APLL Bypass Slicer Enabled 0x0 = Functional Reset"
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bitfld.long 0x0 12. "XTAL_DETECT_XO_SLICER,XTAL Detect Enable This bit connects a pullup and sense circuitry to CLKM to detect the presence or absence of a crystal. This operation will conflict with oscillator functionality so this bit must be asserted only when the.." "0: Functional Reset,1: XTAL sense function enabled"
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bitfld.long 0x0 11. "SLICER_DCCPL_XO_SLICER,Slicer DC-Coupled Mode 0 = Normal operation (AC-couple CLKP to internal slicer) 1 = DC-couple CLKP to internal slicer to CLKP 0x0 = Functional Reset" "0: Normal operation,1: DC-couple CLKP to internal slicer to CLKP 0x0 =.."
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bitfld.long 0x0 10. "SLICER_HIPWR_XO_SLICER,Slicer High-power Mode This bit bypasses the input clock slicer current-starving/filtering circuitry to increase gain and reduce device phase-noise at the expense of power and reduced supply noise rejection. This permits the use.." "0: Normal operation,1: High-power/high-speed test mode 0x0 = Functional.."
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bitfld.long 0x0 9. "FASTCHARGEZ_BIAS_XO_SLICER,Bias Fast-charge Enable (Active Low) This bit bypasses the RC filtering on the XOSC/SLICER Bias to permit more rapid power-up. 0 = Bias fast-charge 1 = Normal operation (filtering present) 0x1 = Functional Reset" "0: Bias fast-charge,1: Functional Reset"
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hexmask.long.byte 0x0 4.--8. 1. "XOSC_DRIVE_XO_SLICER,Crystal Oscillator Output Drive Binary-weighted oscillator drive control 0x0 = Functional Reset"
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hexmask.long.byte 0x0 0.--3. 1. "RTRIM_BIAS_XO_SLICER,Crystal Oscillator and Slicer Bias RTrim Binary-weighted bias control 0x0 = Functional Reset"
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line.long 0x4 "ANA_REG_CLK_CTRL_REG1_CLKTOP,"
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hexmask.long 0x4 3.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset"
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bitfld.long 0x4 2. "ENABLE_XOSC,Enable Crystal Oscillator 0 = Disabled 1 = Enabled 0x1 = Functional Reset" "0: Disabled,1: Enabled 0x1 = Functional Reset"
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bitfld.long 0x4 1. "ENABLE_SLICER_CLKP,Enable CLKP Input Slicer 0 = Disabled 1 = Enabled 0x1 = Functional Reset" "0: Disabled,1: Enabled 0x1 = Functional Reset"
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bitfld.long 0x4 0. "ENABLE_BIAS_XO_SLICER,Enable Bias for Crystal Oscillator and Slicer 0 = Disabled 1 = Enabled 0x1 = Functional Reset" "0: Disabled,1: Enabled 0x1 = Functional Reset"
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line.long 0x8 "ANA_REG_CLK_CTRL_REG2_CLKTOP,"
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hexmask.long 0x8 0.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset"
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line.long 0xC "ANA_REG_CLK_CTRL_REG1_LDO_CLKTOP,"
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hexmask.long.tbyte 0xC 10.--31. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset"
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bitfld.long 0xC 9. "CLK_BIST_DISABLE_LDO,DC BIST Disable for LDO 0 = Normal operation of DC BIST 1 = DC BIST Disabled 0x0 = Functional Reset" "0: Normal operation of DC BIST,1: DC BIST Disabled 0x0 = Functional Reset"
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hexmask.long.byte 0xC 1.--8. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset"
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bitfld.long 0xC 0. "EN_SLICER_LDO,SLICER LDO ENABLE 0 = Slicer LDO Disabled 1 = Slicer LDO Enabled 0x1 = Functional Reset" "0: Slicer LDO Disabled,1: Slicer LDO Enabled 0x1 = Functional Reset"
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line.long 0x10 "ANA_REG_CLK_CTRL_REG2_LDO_CLKTOP,"
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hexmask.long.byte 0x10 24.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset"
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hexmask.long.byte 0x10 20.--23. 1. "BISTMUX_CTRL,SLICER LDO BIST MUX CONTROL (ONE HOT) Analog MUX enables to BIST output port 0000 = HI-Z Output 0001 = VBG_0P9*10/9 =1.0 V 0010 = VDD18*0.5 = 0.9V 0100 = VLDO Output * 0.6 1000 = Floating WARNING: Enabling more than one bit may damage the.."
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hexmask.long.byte 0x10 16.--19. 1. "TESTMUX_CTRL,SLICER LDO TEST MUX CONTROL (ONE HOT) Analog MUX enables to test output port 0000 = HI-Z Output 0001 = 0.6 * VLDO_OUT 0010 = VDD18*0.5 = 0.9V 0100 = VSSA 1000 = LDO Test Current (12.5uA) WARNING: Enabling more than one bit may damage the.."
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bitfld.long 0x10 13.--15. "TLOAD_CTRL,SLICER LDO TLOAD CONTROL Need inverter on bit13 updated description needed 0x0 = Functional Reset" "0: Functional Reset,?,?,?,?,?,?,?"
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bitfld.long 0x10 12. "ENABLE_PMOS_PULLDOWN,SLICER LDO PMOS PULL DOWN ENABLE 0 = Slicer LDO PMOS Pull Down disabled 1 = Slicer LDO.." "0: Slicer LDO PMOS Pull Down disabled,1: Slicer LDO PMOS Pull Down enabled 0x0 =.."
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bitfld.long 0x10 11. "SCPRT_IBIAS_CTRL,SLICER LDO SHORT CKT PROTECTION IBIAS CONTROL 0 = Nominal short circuit bias with nominal short.." "0: Functional Reset,?"
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bitfld.long 0x10 8.--10. "LDO_BW_CTRL,SLICER LDO BANDWIDTH CONTROL Need inverters on bits 8 and 10 need updated description 0x7 = Functional Reset" "?,?,?,?,?,?,?,7: Functional Reset"
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bitfld.long 0x10 7. "EN_BYPASS,SLICER LDO BYPASS ENABLE 0 = Slicer LDO in normal mode 1 = Slicer LDO Bypassed with external.." "0: Slicer LDO in normal mode,1: Slicer LDO Bypassed with external voltage 0x0 =.."
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bitfld.long 0x10 6. "EN_SHRT_CKT,SLICER LDO SHORT CKT PROTECTION ENABLE 0 = Slicer LDO Short Ckt Protection Disabled 1 = Slicer.." "0: Slicer LDO Short Ckt Protection Disabled,1: Slicer LDO Short Ckt Protection Enabled 0x0=.."
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bitfld.long 0x10 5. "EN_TEST_MODE,SLICER LDO TEST MODE ENABLE 0 = Slicer LDO TEST MODE Disabled 1 = Slicer LDO TEST MODE Enabled.." "0: Slicer LDO TEST MODE Disabled,1: Slicer LDO TEST MODE Enabled 0x0 = Functional.."
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bitfld.long 0x10 4. "ENZ_LOW_BW_CAP,SLICER LDO LOW BW MODE DISABLE 1 = Slicer LDO Low BW mode Enabled 0 = Slicer LDO Low BW mode Disabled.." "0: Slicer LDO Low BW mode Disabled Description IS..,1: Slicer LDO Low BW mode Enabled"
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hexmask.long.byte 0x10 0.--3. 1. "LDO_VOUT_CTRL,SLICER LDO VOUT TRIM NEEDS updated description Need inverters on 0 1 2 0x0 = Functional Reset"
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rgroup.long 0xC18++0x3
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line.long 0x0 "ANA_REG_CLK_STATUS_REG,"
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hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect."
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bitfld.long 0x0 8. "CLK_TEST_PATH_LDO_SC_OUT,CLK TEST PATH LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 7. "SYNC_20G_LDO_SC_OUT,SYNC 20G LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 6. "CLKTOP_IOBUF_ROUTE_LDO_SC_OUT,CLKTOP IOBUF ROUTE LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 5. "SYNTH_DIV_LDO_SC_OUT,SYNTH DIV LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 4. "SYNTH_VCO_LDO_SC_OUT,SYNTH VCO LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 3. "SDM_LDO_SC_OUT,SDM LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 2. "CLKTOP_IOBUF_APLL_LDO_SC_OUT,CLKTOP IOBUF APLL LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 1. "APLL_VCO_LDO_SC_OUT,APLL VCO LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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bitfld.long 0x0 0. "SLICER_LDO_SC_OUT,SLICER LDO SHORT CIRCUIT INDICATOR 0 = Normal operation 1 = LDO Output Short Circuit Detected" "0: Normal operation,1: LDO Output Short Circuit Detected"
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group.long 0xC1C++0x1B
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line.long 0x0 "ANA_REG_REFSYS_CTRL_REG_LOWV,"
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bitfld.long 0x0 31. "RESERVED0,Reserved 0x0 = Functional Reset" "0: Functional Reset,?"
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hexmask.long.byte 0x0 27.--30. 1. "FTRIM_3_0,Filter TRIM Control 0x0 = Functional Reset"
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bitfld.long 0x0 26. "DO_NOT_USE3,Do not use this bit --> mapped to REFSYS_CTRL_REG<26> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x0 25. "DO_NOT_USE2,Do not use this bit --> mapped to REFSYS_CTRL_REG<25> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x0 24. "REFSYS_BYPASS_EN,<5> REFSYS By-Pass Enable 0x0 = Functional Reset" "0,1"
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bitfld.long 0x0 23. "DO_NOT_USE1,Do not use this bit --> mapped to REFSYS_CTRL_REG<23> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x0 22. "DO_NOT_USE0,Do not use this bit --> mapped to REFSYS_CTRL_REG<22> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x0 21. "CLKTOP_IBIAS_EN,<2> CLK TOP IBIAS EN 0x1 = Functional Reset" "0,1"
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bitfld.long 0x0 20. "V2I_STARTUP,<1> V2I Startup 0x0 = Functional Reset" "?,1: V2I Startup 0x0 = Functional Reset"
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bitfld.long 0x0 19. "BGAP_ISW,<0> BGAP ISW STARTUP 0x0 = Functional Reset" "0: BGAP ISW STARTUP 0x0 = Functional Reset,?"
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hexmask.long.byte 0x0 14.--18. 1. "IREF_TRIM_4_0,Default Resistor Trim for NOM LOT 0x02 = Functional Reset"
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hexmask.long.byte 0x0 9.--13. 1. "MAG_TRIM_4_0,Default Magnitude Trim for NOM LOT 0x00 = Functional Reset"
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hexmask.long.byte 0x0 4.--8. 1. "SLOPE_TRIM_4_0,Default Slope Trim for NOM LOT 0x0D = Functional Reset"
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bitfld.long 0x0 3. "REFSYS_PRE_CHARGE,REFSYS Pre Charge Control 0 = Disable Pre Charge Block 1 = Enable Pre Charge Block 0x0 = Functional Reset" "0: Disable Pre Charge Block,1: Enable Pre Charge Block 0x0 = Functional Reset"
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bitfld.long 0x0 2. "REFSYS_CAP_SW_CTRLZ,REFSYS Cap Switch Control 0 = Switch External Cap to reference output 1 = Disconnect External Cap to Reference output 0x0 = Functional Reset" "0: Switch External Cap to reference output,1: Disconnect External Cap to Reference output 0x0.."
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bitfld.long 0x0 1. "REFSYS_V2I_EN_CTRL,REFSYS Enable Control 0 = Disable V2I REFSYS 1 = Enable V2I REFSYS 0x1 = Functional Reset" "0: Disable V2I REFSYS,1: Enable V2I REFSYS 0x1 = Functional Reset"
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bitfld.long 0x0 0. "REFSYS_BGAP_EN_CTRL,REFSYS Enable Control 0 = Disable REFSYS 1 = Enable REFSYS 0x1 = Functional Reset" "0: Disable REFSYS,1: Enable REFSYS 0x1 = Functional Reset"
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line.long 0x4 "ANA_REG_REFSYS_TMUX_CTRL_LOWV,"
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bitfld.long 0x4 31. "REFSYS_CTRL_8,REFSYS Test Mux Enable. Other bits in Bus are One-hot. This control enabled in sync with other one hot control bits in Reg 0 = TMUX Disabled 1 = TMUX Enabled 0x0 = Functional Reset" "0: TMUX Disabled,1: TMUX Enabled 0x0 = Functional Reset"
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hexmask.long.word 0x4 16.--30. 1. "RESERVED3,Reserved Reads return 0x0 and writes have no effect. 0x0000 = Functional Reset"
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bitfld.long 0x4 15. "LO_IBIASP_20u,<15> LO IBG BIASP 20uA (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 14. "TX_IBIASP_20u,<14> TX IBG BIASP 20uA (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 13. "BYPASS_MIRR_VPBIAS,VPBIAS Control for IREF Gen Test Mode V2I By-Pass Feature 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 12. "I2V_SENSE,Sense Voltage from the BIST I2V conversion of 20u and 12u bias current paths Sense voltage of 1V for BIST select<6> Sense voltage of 0.6V for BIST select<7> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 11. "RESERVED2,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 10. "IREFP_10UA,<10> IREFP 10uA (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 9. "IDIODEP_100U,<9> Idiode BIASP 100uA (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 8. "RESERVED1,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 7. "IBIASP_TS_6U,<7> IBG BIASP TS 6uA (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 6. "IBIASP_20U,<6> CLK IBG BIASP 20uA (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 5. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 4. "VBE_WEAK,<4> - VBE Weak (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 3. "RX_IBIASP_20u,<3> RX IBG BIASP 20uA (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 2. "VBG_1P22V,<2> - VBG 1.22V (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 1. "VREF_0P9V,<1> - VREF 0P9V (Cap Node) (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x4 0. "VREF_0P45V,<0> - VREF 0P45 (TMUX One-Hot) 0x0 = Functional Reset" "0: Functional Reset,?"
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line.long 0x8 "ANA_REG_REFSYS_SPARE_REG_LOWV,"
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bitfld.long 0x8 31. "RESERVED6,Reserved Used for ANALOGTEST TMUX ESD CTRL in Pad-Frame in TPR (formerly RX_REFSYS_TMUX_SPARE_CTRL_LOWV<31> in AWR/IWR devices but RX does not exist in TPR) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 28.--30. "RESERVED5,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset" "0: Functional Reset,?,?,?,?,?,?,?"
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bitfld.long 0x8 26.--27. "VDDA_OSC_IR_DROP_COMP_SEL,VDDA_OSC UV VMON Reference Selection 0x0 = 0.56V 0x1 = 0.54V 0x2 = 0.52V 0x3 = 0.5V 0x0 = Functional Reset" "0: Functional Reset,?,?,?"
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bitfld.long 0x8 24.--25. "VDDS_3P3V_IR_DROP_COMP_SEL,VIOIN VMON UV Reference Selection 0x0 = 0.56V 0x1 = 0.54V 0x2 = 0.52V 0x3 = 0.5V 0x0 = Functional Reset" "0: Functional Reset,?,?,?"
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bitfld.long 0x8 22.--23. "VDD_IR_DROP_COMP_SEL,VDD 1.2V VMON UV Reference Selection and VDD 1.2V VMON OV Self-test Reference Selection If MSS_REFSYS_SPARE_REG<8> = 0x0 reference selection is dependent on MSS_REFSYS_SPARE_REG<7:6> programming (normal VDD 1.2V VMON UV operation).." "0: Functional Reset,?,?,?"
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bitfld.long 0x8 21. "VDD_OV_RSET_MASK,If asserted VDD_OV will not trigger the automatic reset of the device through WU Seq hardware control. However OV flag will still propagate to the digital where the CPU will need to take action. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 20. "VDD_UV_RSET_MASK,If asserted VDD_UV will not trigger the automatic reset of the device through WU Seq hardware control. However UV flag will still propagate to the digital where the CPU will need to take action. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 19. "VDDA_OSC_UV_RSET_MASK,If asserted VDDA_OSC_UV will not trigger the automatic reset of the device through WU Seq hardware control. However UV flag will still propagate to the digital where the CPU will need to take action. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 18. "VIOIN_UV_RSET_MASK,If asserted VIOIN_UV will not trigger the automatic reset of the device through WU Seq hardware control. However UV flag will still propagate to the digital where the CPU will need to take action. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 16.--17. "VDD_OV_SR_SEL,Final level of VDD 1.2V VMON OV Reference Selection See definition in MSS_REFSYS_SPARE_REG<15:14> for normal operation (MSS_REFSYS_SPARE_REG<9> = 0x0) See definition in MSS_REFSYS_SPARE_REG<23:22> for self-test operation.." "0: Functional Reset,?,?,?"
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bitfld.long 0x8 14.--15. "VDD_OV_IR_DROP_COMP_SEL,VDD 1.2V VMON OV Reference Selection and VDD 1.2V VMON UV Self-test Reference Selection If MSS_REFSYS_SPARE_REG<9> = 0x0 reference selection is dependent on MSS_REFSYS_SPARE_REG<17:16> programming (normal VDD 1.2V VMON OV.." "0: Functional Reset,?,?,?"
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bitfld.long 0x8 13. "RESERVED3,Reserved Reserved in case VIOIN OV VMON and self test is ever implemented 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 12. "VDDS_3P3V_UV_SELF_TEST_SEL,Enable VIOIN Strict UV VMON Self Test If Self-test mode is enabled VIOIN UV VMON reference is programmed as follows for MSS_REFSYS_SPARE_REG<25:24>: 0x0 = 0.66V 0x1 = 0.64V 0x2 = 0.62V 0x3 = 0.6V 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 11. "RESERVED2,Reserved Reserved in case VDDA_OSC OV VMON and self test is ever implemented 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 10. "VDDA_OSC_UV_SELF_TEST_SEL,Enable VDDA_OSC Strict UV VMON Self Test If Self-test mode is enabled VDDA_OSC UV VMON reference is programmed as follows for MSS_REFSYS_SPARE_REG<27:26>: 0x0 = 0.66V 0x1 = 0.64V 0x2 = 0.62V 0x3 = 0.6V 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x8 9. "VDD_OV_SELF_TEST_SEL,Enable 1.2V VDD Strict OV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON OV reference is programmed based on MSS_REFSYS_SPARE_REG<23:22> and MSS_REFSYS_SPARE_REG<17:16> as follows: If MSS_REFSYS_SPARE_REG<17:16> = 0x0 .." "0: Functional Reset,?"
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bitfld.long 0x8 8. "VDD_UV_SELF_TEST_SEL,Enable 1.2V VDD Strict UV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON UV reference is programmed based on MSS_REFSYS_SPARE_REG<15:14> and MSS_REFSYS_SPARE_REG<7:6> as follows: If MSS_REFSYS_SPARE_REG<7:6> = 0x0 .." "0: Functional Reset,?"
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bitfld.long 0x8 6.--7. "VDD_SR_SEL,Final level of VDD 1.2V VMON UV Reference Selection See definition in MSS_REFSYS_SPARE_REG<23:22> for normal operation (MSS_REFSYS_SPARE_REG<8> = 0x0) See definition in MSS_REFSYS_SPARE_REG<15:14> for self-test operation.." "0: Functional Reset,?,?,?"
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hexmask.long.byte 0x8 1.--5. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect but these bits are tied to efuse overrides. 0x0 = Functional Reset"
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bitfld.long 0x8 0. "RESERVED0,Reserved In TPR this bit is mapped to efuse and is used to control POR_DIG_SEQ_ECO_DIS. Writes have no effect. 0: Enable Slicer delay ECO 1: Disable Slicer delay ECO 0x0 = Functional Reset" "0: Enable Slicer delay ECO,1: Disable Slicer delay ECO 0x0 = Functional Reset"
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line.long 0xC "ANA_REG_WU_CTRL_REG_LOWV,"
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bitfld.long 0xC 31. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0xC 29.--30. "WU_SPARE_IN_2,WU Spare Control 0x3 = Functional Reset" "?,?,?,3: Functional Reset"
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bitfld.long 0xC 28. "WU_VDD_OV_VMON_EN,WU VDD OV VMON Enable Control 0 = VDD OV Detect Disabled 1 = VDD OV Detect Enabled 0x0 = Functional Reset" "0: VDD OV Detect Disabled,1: VDD OV Detect Enabled 0x0 = Functional Reset"
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bitfld.long 0xC 27. "WU_VDD_UV_VMON_EN,WU VDD UV VMON Enable Control 0 = VDD UV Detect Disabled 1 = VDD UV Detect Enabled 0x0 = Functional Reset" "0: VDD UV Detect Disabled,1: VDD UV Detect Enabled 0x0 = Functional Reset"
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bitfld.long 0xC 26. "WU_VDDA_OSC_UV_VMON_EN,WU VDDA OSC UV VMON Enable Control 0 = VDDA OSC UV Detect Disabled 1 = VDDA OSC UV Detect Enabled 0x0 = Functional Reset" "0: VDDA OSC UV Detect Disabled,1: VDDA OSC UV Detect Enabled 0x0 = Functional Reset"
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bitfld.long 0xC 25. "WU_VDDS_3P3V_UV_VMON_EN,WU VDDS 3.3V UV VMON Enable Control 0 = VDDS 3.3V UV Detect Disabled 1 = VDDS 3.3V UV Detect Enabled 0x0 = Functional Reset" "0: Functional Reset,1: VDDS 3"
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bitfld.long 0xC 23.--24. "WU_SPARE_IN,WU Spare Control Change for 1642 ES2P0 Change Name : Newly added OR gates to provide options to bypass crude VDD DET (also refer to <11>) Bit <0> of this field when HIGH over rides the crude VDD_DET this control is using firmware Bit<0> of.." "0: Functional Reset,1: is '0',?,?"
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bitfld.long 0xC 22. "WU_SUPP_DET_CTRL,WU VMON Detect Status Override Disable in Functional Test SOP 0 = VMON Det Status Override Disabled 1 = VMON Det Status Override Enabled 0x1 = Functional Reset" "0: VMON Det Status Override Disabled,1: VMON Det Status Override Enabled 0x1 =.."
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bitfld.long 0xC 21. "WU_VRAM_VMON_EN,WU VRAM VMON Enable Control 0 = SRAM UV Detect Disabled 1 = SRAM UV Detect Enabled 0x1 = Functional Reset" "0: SRAM UV Detect Disabled,1: SRAM UV Detect Enabled 0x1 = Functional Reset"
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bitfld.long 0xC 20. "WU_SUPP_VMON_EN,WU VMON Enable Control 0 = VMON Control Disabled 1 = VMON Control Enabled 0x1 = Functional Reset" "0: VMON Control Disabled,1: VMON Control Enabled 0x1 = Functional Reset"
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bitfld.long 0xC 19. "WU_XTAL_DLY_CTRL,Introduce additional delay for XTAL settling 0 = Default delay as per WU-SEQ 1 = Introduce additional delay as per WU-SEQ 0x0 = Functional Reset" "0: Default delay as per WU-SEQ,1: Introduce additional delay as per WU-SEQ 0x0 =.."
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bitfld.long 0xC 18. "WU_OV_DET_CTRL,WU Over Voltage Detect Control Changed for 1243 ES3P0 (Metal only change from 1642 ES2P0) Change Name : FW control of VDD OV DET EN 1 = OV Detect is disabled 0 = OV Detect is Enabled 0x1 = Functional Reset" "0: OV Detect is Enabled 0x1 = Functional Reset,1: OV Detect is disabled"
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bitfld.long 0xC 17. "WU_UV_DET_CTRL,WU Under Voltage Detect Control 0 = UV Detect is disabled 1 = UV Detect is Enabled 0x1 = Functional Reset" "0: UV Detect is disabled,1: UV Detect is Enabled 0x1 = Functional Reset"
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bitfld.long 0xC 16. "XTAL_EN_OVERRIDE,XTAL EN Override (WU-SEQ) Control 0 = XTAL Enable is driven by WU-SEQ detection 1 = Override XTAL Enable if disabled by default 0x0 = Functional Reset" "0: XTAL Enable is driven by WU-SEQ detection,1: Override XTAL Enable if disabled by default 0x0.."
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bitfld.long 0xC 15. "WU_CPU_CLK_CTRL,WU CLK Control 0 = CLK Monitor Function in Dig Sequencer is disabled 1 = REF CLK Monitor Function is Enabled 0x1 = Functional Reset" "0: CLK Monitor Function in Dig Sequencer is disabled,1: REF CLK Monitor Function is Enabled 0x1 =.."
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hexmask.long.byte 0xC 11.--14. 1. "INT_CLK_FREQ_SEL_3_0,WU Internal Clock (RCOSC) Frequency Select Bit<3> is used as override for VMON on.."
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bitfld.long 0xC 10. "ECO_SLICER_CLK_DLY_DIS,Disable slicer clock delay ECO (mapped to eFuse) 0x0 = Functional Reset" "0: Functional Reset,?"
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hexmask.long.byte 0xC 3.--9. 1. "INT_CLK_TRIM_6_0,WU lnternal Clock (RCOSC) Trim 0x4B = Functional Reset (If not trimmed)"
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bitfld.long 0xC 2. "INT_CLK_SW_SEL,WU Internal Clock (RCOSC) SW_SEL 0 = TBD 1 = TBD 0x1 = Functional Reset" "0: TBD,1: TBD 0x1 = Functional Reset"
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bitfld.long 0xC 1. "INT_CLK_STOP,WU Internal Clock (RCOSC) STOP 0 = Internal CLK can be enabled 1 = Internal CLK is OFF 0x0 =.." "0: Internal CLK can be enabled,1: Internal CLK is OFF 0x0 = Functional Reset"
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bitfld.long 0xC 0. "INT_CLK_EN,WU Internal Clock (RCOSC) ENABLE 0 = Internal CLK Disabled 1 = Internal CLK Enabled 0x1 =.." "0: Internal CLK Disabled,1: Internal CLK Enabled 0x1 = Functional Reset"
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line.long 0x10 "ANA_REG_WU_TMUX_CTRL_LOWV,"
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bitfld.long 0x10 31. "WU_TMUX_EN,WU TMUX Enable 0 = TMUX Disabled 1 = TMUX Enabled 0x0 = Functional Reset" "0: TMUX Disabled,1: TMUX Enabled 0x0 = Functional Reset"
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hexmask.long.byte 0x10 25.--30. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect. 0x00 = Functional Reset"
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bitfld.long 0x10 24. "SCALED_VDDS33,Test Mux Control. One Hot Control Scaling Factor: 0.289 * VDDS33 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 23. "SCALED_VDDA_LVDS_1P8V,Test Mux Control. One Hot Control Change in TPR VDDS_3P3V IO DET reference (3.3V mode) Scaling Factor: 0.4 * VDDA_LVDS_1P8V 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 22. "SCALED_VDDA_LVDS_1P8V_1P2,Test Mux Control. One Hot Control Change in TPR VDDS_3P3V IO DET reference (1.8V mode) Scaling Factor: 0.67 * VDDA_LVDS_1P8V 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 21. "VFB_0P85V,Scaled VDD 1.2V used as reference for VDDA_OSC crude supply detect 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 20. "VDDSINT18,VIOIN scaled supply for VIOIN Detect Scaling Factor: VIOIN*(52/90) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 19. "SCALED_VDDA_OSC_DIV22_39,Scaled VDDA_OSC supply for crude supply detect Scaling Factor: VDDA_OSC*(22/39) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 18. "VT_DIG_SIG_OV,Test Mux Control. One Hot Control VT Detect Signal Level on VDD12 Crude OV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 17. "VT_DIG_SIG_UV,Test Mux Control. One Hot Control VT Detect Signal Level on VDD12 Crude UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 16. "VT_ANA_SIG,Test Mux Control. One Hot Control VT Detect Signal Level on VDDA_LVDS_1P8V 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 15. "VDDA10RF2_UV_VREF,Test Mux Control. One Hot Control Vref for VDDA10RF2_UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 14. "VDDA10RF1_UV_VREF,Test Mux Control. One Hot Control Vref for VDDA10RF1_UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 13. "VDDA18VCO_UV_VREF,Test Mux Control. One Hot Control Vref for VDDA18VCO_UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 12. "VDD_UV_VREF,Test Mux Control. One Hot Control Vref for VDD_UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 11. "VDD_OV_VREF,Test Mux Control. One Hot Control Vref for VDD_OV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 10. "VDDA18BB_UV_VREF,Test Mux Control. One Hot Control Vref for VDDA18BB_UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 9. "VIOIN33_UV_VREF,Test Mux Control. One Hot Control Vref for VIOIN33_UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 8. "VDDA_OSC_UV_VREF,Test Mux Control. One Hot Control Vref for VDDA_OSC_UV VMON 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 7. "VREF_0P9V,Test Mux Control. One Hot Control VREF_0P9V 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 6. "SCALED_VDDA10RF2,Test Mux Control. One Hot Control Scaling Factor: VDDA10RF2/2 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 5. "SCALED_VDDA10RF1,Test Mux Control. One Hot Control Scaling Factor: VDDA10RF1/2 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 4. "SCALED_VDDA18VCO,Test Mux Control. One Hot Control Scaling Factor: VDDA18VCO/3 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 3. "VFB_0P6V,Test Mux Control. One Hot Control Scaling Factor: 0.5 * VDD 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 2. "SCALED_VDDA18BB,Test Mux Control. One Hot Control Scaling Factor: VDDA18BB/3 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 1. "SCALED_VIO3318,Test Mux Control. One Hot Control Scaling Factor: VIOIN/5.5 (3.3V mode) VIOIN/3 (1.8V mode) 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x10 0. "SCALED_VDDA_OSC_DIV3,Test Mux Control. One Hot Control Scaling Factor: VDDA_OSC/3 0x0 = Functional Reset" "0: Functional Reset,?"
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line.long 0x14 "ANA_REG_TW_CTRL_REG_LOWV,"
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hexmask.long.tbyte 0x14 15.--31. 1. "Reserved0,Reserved 0x00000 = Functional Reset"
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bitfld.long 0x14 14. "ANA_TMUX_BUF_EN,MSS TW ANA TMUX Buffer Enabled 0 = ANA TMUX Buffer Disabled 1 = ANA TMUX Buffer Enabled 0x0 = Functional Reset" "0: ANA TMUX Buffer Disabled,1: ANA TMUX Buffer Enabled 0x0 = Functional Reset"
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bitfld.long 0x14 13. "ANA_TMUX_BUF_BYPASS,MSS TW ANA TMUX Buffer Bypass 0 = ANA TMUX Buffer By-pass Disabled 1 = ANA TMUX Buffer By-pass Enabled 0x0 = Functional Reset" "0: ANA TMUX Buffer By-pass Disabled,1: ANA TMUX Buffer By-pass Enabled 0x0 = Functional.."
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bitfld.long 0x14 12. "VIN_EXT_CTRL,MSS TW VIN Control from External Source 0 = External VIN Control Disabled 1 = External VIN Control Enabled 0x0 = Functional Reset" "0: External VIN Control Disabled,1: External VIN Control Enabled 0x0 = Functional.."
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bitfld.long 0x14 11. "VREF_EXT_CTRL,MSS TW VREF Control from External SOurce 0 = External VREF Control Disabled 1 = External VREF Control Enabled 0x0 = Functional Reset" "0: External VREF Control Disabled,1: External VREF Control Enabled 0x0 = Functional.."
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bitfld.long 0x14 10. "IFORCE_EXT_CTRL,MSS TW Iforce Control from External Source 0 = IFORCE Control Disabled 1 = IFORCE Control Enabled 0x0 = Functional Reset" "0: IFORCE Control Disabled,1: IFORCE Control Enabled 0x0 = Functional Reset"
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bitfld.long 0x14 9. "TS_SE_INP_BUF_EN,MSS TW ADC TS SE Inp Buffer Enable 0 = Input Buffer disabled 1 = Input Buffer Enabled 0x0 = Functional Reset" "0: Input Buffer disabled,1: Input Buffer Enabled 0x0 = Functional Reset"
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bitfld.long 0x14 8. "TS_DIFF_INP_BUF_EN,MSS TW ADC TS DIFF Inp Buffer Enable 0 = Input Buffer disabled 1 = Input Buffer Enabled 0x1 = Functional Reset" "0: Input Buffer disabled,1: Input Buffer Enabled 0x1 = Functional Reset"
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bitfld.long 0x14 5.--7. "ADC_REF_SEL_2_0,MSS TW ADC Reference Select 0b001 = Reference from Top Refsys 0b010 = Reference from RX Refsys 0b100 = Reference from External Test Pin (CZ/ Trim) 0x001 = Functional Reset" "?,1: Functional Reset,?,?,?,?,?,?"
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bitfld.long 0x14 4. "ADC_REF_BUF_EN,MSS TW ADC Reference Buffer Enable 0 = Input Buffer disabled 1 = Input Buffer Enabled (Default) 0x1 = Functional Reset" "0: Input Buffer disabled,1: Functional Reset"
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bitfld.long 0x14 3. "ADC_INP_BUF_EN,MSS TW ADC Input Buffer Enable 0 = Input Buffer disabled 1 = Input Buffer Enabled (Default) 0x1 = Functional Reset" "0: Input Buffer disabled,1: Functional Reset"
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bitfld.long 0x14 2. "ADC_RESET,MSS TW ADC Reset (Active High) 0 = ADC Out of Reset 1 = ADC In Reset 0x1 = Functional Reset" "0: ADC Out of Reset,1: ADC In Reset 0x1 = Functional Reset"
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bitfld.long 0x14 1. "RESERVED ,RESERVED the bit to analog is directly driven MSS_GPADC" "0,1"
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bitfld.long 0x14 0. "ADC_EN,TW MSS ADC Control 0 = ADC Disable 1 = ADC Enable 0x0 = Functional Reset" "0: ADC Disable,1: ADC Enable 0x0 = Functional Reset"
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line.long 0x18 "ANA_REG_TW_ANA_TMUX_CTRL_LOWV,"
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bitfld.long 0x18 31. "DO_NOT_USE21,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<31> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 30. "DO_NOT_USE20,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<30> 0x0 = Functional Reset" "0: Functional Reset,?"
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hexmask.long.byte 0x18 23.--29. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect. 0x00 = Functional Reset"
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bitfld.long 0x18 22. "DO_NOT_USE19,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<22> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 21. "ADC_REF_BUF_OUT,MSS ADC reference buffer out to Test Pin 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 20. "ADC_BUF_OUT_1P8V,Buffered output of MSS ADC inputs to GPADC 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 19. "BIST_MUX_OUT_1P8V,MSS BIST Mux output pre ADC input Buffer 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 18. "DO_NOT_USE18,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<18> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 17. "DO_NOT_USE17,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<17> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 16. "DO_NOT_USE16,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<16> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 15. "DO_NOT_USE15,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<15> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 14. "DO_NOT_USE14,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<14> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 13. "DO_NOT_USE13,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<13> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 12. "DO_NOT_USE12,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<12> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 11. "DO_NOT_USE11,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<11> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 10. "DO_NOT_USE10,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<10> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 9. "DO_NOT_USE9,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<9> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 8. "DO_NOT_USE8,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<8> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 7. "DO_NOT_USE7,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<7> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 6. "DO_NOT_USE6,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<6> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 5. "DO_NOT_USE5,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<5> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 4. "DO_NOT_USE4,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<4> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 3. "DO_NOT_USE3,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<3> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 2. "DO_NOT_USE2,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<2> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 1. "DO_NOT_USE1,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<1> 0x0 = Functional Reset" "0: Functional Reset,?"
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bitfld.long 0x18 0. "DO_NOT_USE0,Do not use this bit --> mapped to TW_ANA_TMUX_CTRL<0> 0x0 = Functional Reset" "0: Functional Reset,?"
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rgroup.long 0xC3C++0xB
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line.long 0x0 "ANA_REG_WU_MODE_REG_LOWV,"
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hexmask.long 0x0 7.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect. 0x0000000 = Functional Reset"
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hexmask.long.byte 0x0 2.--6. 1. "SOP_MODE_LAT_4_0,SOP Mode Latched Output"
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bitfld.long 0x0 1. "TEST_MODE_DET_SYNC,Latched Output of Test Mode Detect SOP" "0,1"
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bitfld.long 0x0 0. "FUNC_TEST_DET_SYNC,Latched Output of Functional Test Mode SOP" "0,1"
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line.long 0x4 "ANA_REG_WU_STATUS_REG_LOWV,"
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hexmask.long.word 0x4 19.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect."
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bitfld.long 0x4 18. "VDDS_3P3V_UVDET_LAT,Latched Value of 3.3V IO UV Detect 0 = UV Detect Not Triggered 1 = UV Detect has Triggered" "0: UV Detect Not Triggered,1: UV Detect has Triggered"
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bitfld.long 0x4 17. "VDDA_OSC_UVDET_LAT,Latched value of UV detect for 1.8V CLK 0 = UV Detect Not Triggered 1 = UV Detect has Triggered" "0: UV Detect Not Triggered,1: UV Detect has Triggered"
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bitfld.long 0x4 16. "APLLVCO18_UVDET_LAT,Latched Value of UV Detect for 1.8V VCO 0 = UV Detect Not Triggered 1 = UV Detect has Triggered" "0: UV Detect Not Triggered,1: UV Detect has Triggered"
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bitfld.long 0x4 15. "HVMODE,HVMODE Status from VMON 1 = 3.3V VIO 0 = 1.8V VIO" "0,1"
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bitfld.long 0x4 14. "LIMP_MODE_STATUS,Ref CLK status at Wake-up 0 = REF CLK is present 1 = REF CLK is absent and CPU CLK Switched to RCOSC" "0: REF CLK is present,1: REF CLK is absent and CPU CLK Switched to RCOSC"
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bitfld.long 0x4 13. "XTAL_DET_STATUS,XTAL Detect status at Wake-up 0 = XTAL absent 1 = XTAL Present" "0: XTAL absent,1: XTAL Present"
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bitfld.long 0x4 12. "RCOSC_CLK_STATUS,RCOSC status at Wake-up 0 = RCOSC CLK absent 1 = RCOSC CLK Present" "0: RCOSC CLK absent,1: RCOSC CLK Present"
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bitfld.long 0x4 11. "REF_CLK_STATUS,Ref CLK status at Wake-up 0 = REF CLK absent 1 = REF CLK Present" "0: REF CLK absent,1: REF CLK Present"
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bitfld.long 0x4 10. "SUPP_OK_VDDD18,Can be made spare (TiedLO internally)" "0,1"
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bitfld.long 0x4 9. "SUPP_OK_SRAM12,Can be made spare (TiedLO internally)" "0,1"
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bitfld.long 0x4 8. "VDDA10RF2_UVDET_LAT,Latched Value of UV Detect for 1V RF2 0 = UV Detect Not Triggered 1 = UV Detect has Triggered" "0: UV Detect Not Triggered,1: UV Detect has Triggered"
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bitfld.long 0x4 7. "VDDA10RF1_UVDET_LAT,Latched Value of UV Detect for 1V RF1 0 = UV Detect Not Triggered 1 = UV Detect has Triggered" "0: UV Detect Not Triggered,1: UV Detect has Triggered"
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bitfld.long 0x4 6. "SUPP_OK_RF10,Can be made spare (TiedLO internally)" "0,1"
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bitfld.long 0x4 5. "SUPP_OK_IO33,Supp Detect output of IO 3.3V 0 = Supply Not detected 1 = Supply Detected" "0: Supply Not detected,1: Supply Detected"
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bitfld.long 0x4 4. "SUPP_OK_IO18,Supp Detect output of IO 1.8V 0 = Supply Not detected 1 = Supply Detected" "0: Supply Not detected,1: Supply Detected"
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bitfld.long 0x4 3. "SUPP_OK_CLK18,Supp Detect output of CLK 1.8V 0 = Supply Not detected 1 = Supply Detected" "0: Supply Not detected,1: Supply Detected"
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bitfld.long 0x4 2. "VDDA18BB_UV_DET_LAT,Latched Value of UV Detect for 1.8V Baseband 0 = UV Detect Not Triggered 1 = UV Detect has Triggered" "0: UV Detect Not Triggered,1: UV Detect has Triggered"
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bitfld.long 0x4 1. "CORE_UVDET_LAT,Latched Value of UV Detect 0 = UV Detect Not Triggered 1 = UV Detect has Triggered" "0: UV Detect Not Triggered,1: UV Detect has Triggered"
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bitfld.long 0x4 0. "CORE_OVDET_LAT,Latched Value of OV Detect 0 = OV Detect Not Triggered 1 = OV Detect has Triggered" "0: OV Detect Not Triggered,1: OV Detect has Triggered"
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line.long 0x8 "ANA_REG_WU_SPARE_OUT_LOWV,"
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hexmask.long.tbyte 0x8 8.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect."
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bitfld.long 0x8 7. "CORE_UVDET_LOWV,UV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x8 6. "CORE_OVDET_LOWV,OV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x8 5. "INT_OSC_CTRL,Internal Oscillator Control" "0,1"
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bitfld.long 0x8 4. "SUPPDET_OV_CTRL,Supply Detect Override Bit" "0,1"
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bitfld.long 0x8 3. "HVMODE,Status of VIO supply. 3.3V or 1.8V" "0,1"
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bitfld.long 0x8 2. "VDDS18DET,Status of 1.8V IO Bias Supply" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VDDARF_DET,Status of 1.3V RF Supply" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "VDDCLK18DET,Status of 1.8V CLK Supply" "0,1"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_wph,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "MSS_TPCC_A"
|
|
base ad:0x3100000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "CCCFG,CC Configuration Register"
|
|
hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD"
|
|
bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included"
|
|
newline
|
|
bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included"
|
|
bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
|
|
bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD"
|
|
hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N."
|
|
newline
|
|
bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."
|
|
rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."
|
|
rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "QUETCMAP,Queue to TC Mapping"
|
|
hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD"
|
|
bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QUEPRI,Queue Priority"
|
|
hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD"
|
|
bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit.."
|
|
bitfld.long 0x0 31. "E31,Event Missed #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
line.long 0x4 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated.."
|
|
bitfld.long 0x4 31. "E63,Event Missed #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed #32" "0,1"
|
|
wgroup.long 0x308++0x7
|
|
line.long 0x0 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
line.long 0x4 "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x0 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR).."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x0 "CCERR,CC Error Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: QTHRXCD0 = 0 : Watermark/threshold has not been..,1: Watermark/threshold has been exceeded"
|
|
group.long 0x31C++0x7
|
|
line.long 0x0 "CCERRCLR,CC Error Clear Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "?,1: Write of '1' clears the values of QSTAT1"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0: Write of '1' clears the values of QSTAT0,?"
|
|
line.long 0x4 "EEVAL,Error Eval Register"
|
|
hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD"
|
|
bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1"
|
|
group.long 0x340++0x7
|
|
line.long 0x0 "DRAEM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
|
|
line.long 0x4 "DRAEHM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "QRAEN,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD"
|
|
bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.."
|
|
repeat.end
|
|
rgroup.long 0x600++0x3
|
|
line.long 0x0 "QSTATN,QSTATn Register Set"
|
|
hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD"
|
|
bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR,1: Threshold specified by QWMTHR"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10.."
|
|
newline
|
|
bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"
|
|
group.long 0x620++0x3
|
|
line.long 0x0 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0.."
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value"
|
|
newline
|
|
rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value"
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x0 "CCSTAT,CC Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD"
|
|
bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7"
|
|
newline
|
|
bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6"
|
|
bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5"
|
|
newline
|
|
bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4"
|
|
bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3"
|
|
newline
|
|
bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2"
|
|
bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1"
|
|
newline
|
|
bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0"
|
|
bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.."
|
|
bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.."
|
|
bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
newline
|
|
bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "AETCTL,Advanced Event Trigger Control"
|
|
bitfld.long 0x0 31. "EN,AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled"
|
|
hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"
|
|
rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA Events,1: Event specified by STARTEVT applies to QDMA.."
|
|
hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"
|
|
rgroup.long 0x704++0x3
|
|
line.long 0x0 "AETSTAT,Advanced Event Trigger Stat"
|
|
hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "STAT,AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "AETCMD,AET Command"
|
|
hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1000++0x7
|
|
line.long 0x0 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low).."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1008++0xF
|
|
line.long 0x0 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1018++0xF
|
|
line.long 0x0 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1028++0xF
|
|
line.long 0x0 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1038++0x7
|
|
line.long 0x0 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1040++0x7
|
|
line.long 0x0 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1050++0x7
|
|
line.long 0x0 "IER,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1058++0xF
|
|
line.long 0x0 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x1068++0x7
|
|
line.long 0x0 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1070++0x7
|
|
line.long 0x0 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x1078++0x3
|
|
line.long 0x0 "IEVAL,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1080++0x7
|
|
line.long 0x0 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x1088++0x7
|
|
line.long 0x0 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x1094++0x3
|
|
line.long 0x0 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2000++0x7
|
|
line.long 0x0 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2008++0xF
|
|
line.long 0x0 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2018++0xF
|
|
line.long 0x0 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2028++0xF
|
|
line.long 0x0 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2038++0x7
|
|
line.long 0x0 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2040++0x7
|
|
line.long 0x0 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2050++0x7
|
|
line.long 0x0 "IER_RN,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2058++0xF
|
|
line.long 0x0 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x2068++0x7
|
|
line.long 0x0 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2070++0x7
|
|
line.long 0x0 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x2078++0x3
|
|
line.long 0x0 "IEVAL_RN,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x2080++0x7
|
|
line.long 0x0 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x2088++0x7
|
|
line.long 0x0 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2090++0x3
|
|
line.long 0x0 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x2094++0x3
|
|
line.long 0x0 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
tree.end
|
|
tree "MSS_TPCC_B"
|
|
base ad:0x3120000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "CCCFG,CC Configuration Register"
|
|
hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD"
|
|
bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included"
|
|
newline
|
|
bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included"
|
|
bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
|
|
bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD"
|
|
hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N."
|
|
newline
|
|
bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."
|
|
rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."
|
|
rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "QUETCMAP,Queue to TC Mapping"
|
|
hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD"
|
|
bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QUEPRI,Queue Priority"
|
|
hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD"
|
|
bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit.."
|
|
bitfld.long 0x0 31. "E31,Event Missed #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
line.long 0x4 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated.."
|
|
bitfld.long 0x4 31. "E63,Event Missed #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed #32" "0,1"
|
|
wgroup.long 0x308++0x7
|
|
line.long 0x0 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
line.long 0x4 "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x0 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR).."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x0 "CCERR,CC Error Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: QTHRXCD0 = 0 : Watermark/threshold has not been..,1: Watermark/threshold has been exceeded"
|
|
group.long 0x31C++0x7
|
|
line.long 0x0 "CCERRCLR,CC Error Clear Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "?,1: Write of '1' clears the values of QSTAT1"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0: Write of '1' clears the values of QSTAT0,?"
|
|
line.long 0x4 "EEVAL,Error Eval Register"
|
|
hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD"
|
|
bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1"
|
|
group.long 0x340++0x7
|
|
line.long 0x0 "DRAEM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
|
|
line.long 0x4 "DRAEHM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "QRAEN,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD"
|
|
bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.."
|
|
repeat.end
|
|
rgroup.long 0x600++0x3
|
|
line.long 0x0 "QSTATN,QSTATn Register Set"
|
|
hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD"
|
|
bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR,1: Threshold specified by QWMTHR"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10.."
|
|
newline
|
|
bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"
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|
group.long 0x620++0x3
|
|
line.long 0x0 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0.."
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value"
|
|
newline
|
|
rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value"
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x0 "CCSTAT,CC Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD"
|
|
bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7"
|
|
newline
|
|
bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6"
|
|
bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5"
|
|
newline
|
|
bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4"
|
|
bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3"
|
|
newline
|
|
bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2"
|
|
bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1"
|
|
newline
|
|
bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0"
|
|
bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.."
|
|
bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.."
|
|
bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
newline
|
|
bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "AETCTL,Advanced Event Trigger Control"
|
|
bitfld.long 0x0 31. "EN,AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled"
|
|
hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"
|
|
rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA Events,1: Event specified by STARTEVT applies to QDMA.."
|
|
hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"
|
|
rgroup.long 0x704++0x3
|
|
line.long 0x0 "AETSTAT,Advanced Event Trigger Stat"
|
|
hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "STAT,AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "AETCMD,AET Command"
|
|
hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1000++0x7
|
|
line.long 0x0 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low).."
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|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1008++0xF
|
|
line.long 0x0 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1018++0xF
|
|
line.long 0x0 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1028++0xF
|
|
line.long 0x0 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1038++0x7
|
|
line.long 0x0 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1040++0x7
|
|
line.long 0x0 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1050++0x7
|
|
line.long 0x0 "IER,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1058++0xF
|
|
line.long 0x0 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x1068++0x7
|
|
line.long 0x0 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1070++0x7
|
|
line.long 0x0 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x1078++0x3
|
|
line.long 0x0 "IEVAL,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1080++0x7
|
|
line.long 0x0 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x1088++0x7
|
|
line.long 0x0 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x1094++0x3
|
|
line.long 0x0 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2000++0x7
|
|
line.long 0x0 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2008++0xF
|
|
line.long 0x0 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2018++0xF
|
|
line.long 0x0 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2028++0xF
|
|
line.long 0x0 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2038++0x7
|
|
line.long 0x0 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2040++0x7
|
|
line.long 0x0 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2050++0x7
|
|
line.long 0x0 "IER_RN,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2058++0xF
|
|
line.long 0x0 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x2068++0x7
|
|
line.long 0x0 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2070++0x7
|
|
line.long 0x0 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x2078++0x3
|
|
line.long 0x0 "IEVAL_RN,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x2080++0x7
|
|
line.long 0x0 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x2088++0x7
|
|
line.long 0x0 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2090++0x3
|
|
line.long 0x0 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x2094++0x3
|
|
line.long 0x0 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
tree.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0x3140000 ad:0x3160000)
|
|
tree "MSS_TPTC_A$1"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x100)++0x7
|
|
line.long 0x0 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3"
|
|
bitfld.long 0x0 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "WSACTV,Write Status Active WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands. WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write.." "0: Write status is not pending,1: Write Status is pending"
|
|
newline
|
|
bitfld.long 0x0 1. "SRCACTV,Source Active State SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1]. SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.."
|
|
bitfld.long 0x0 0. "PROGBUSY,Program Register Set Busy PROGBUSY = 0 : Prog set idle and is available for programming. PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy"
|
|
line.long 0x4 "INTSTAT,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "TRDONE,TR Done Event Status: TRDONE = 0 : Condition not detected. TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to.." "0: Condition not detected,1: Set when TC has completed a Transfer Request"
|
|
bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY = 0 : Condition not detected. PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.."
|
|
group.long ($2+0x108)++0x3
|
|
line.long 0x0 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE = 0 : TRDONE Event is disabled. INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.."
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled. INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.."
|
|
wgroup.long ($2+0x10C)++0x7
|
|
line.long 0x0 "INTCLR,Interrupt Clear Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE = 0 : Writes of '0' have no effect. INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect. INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
|
|
line.long 0x4 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x4 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
|
|
rgroup.long ($2+0x120)++0x3
|
|
line.long 0x0 "ERRSTAT,Error Status Register"
|
|
bitfld.long 0x0 3. "MMRAERR,MMR Address Error: MMRAERR = 0 : Condition not detected. MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.."
|
|
bitfld.long 0x0 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Bus Error Event: BUSERR = 0: Condition not detected. BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.."
|
|
group.long ($2+0x124)++0x3
|
|
line.long 0x0 "ERREN,Error Enable Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR = 0 : BUSERR is disabled. ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.."
|
|
bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR = 0 : BUSERR is disabled. ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.."
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR = 0 : BUSERR is disabled. ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.."
|
|
wgroup.long ($2+0x128)++0x3
|
|
line.long 0x0 "ERRCLR,Error Clear Register"
|
|
bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR = 0 : Writes of '0' have no effect. ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
|
|
bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR = 0 : Writes of '0' have no effect. ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
|
|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR = 0 : Writes of '0' have no effect. ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
|
|
rgroup.long ($2+0x12C)++0x3
|
|
line.long 0x0 "ERRDET,Error Details Register"
|
|
bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
|
|
bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "15-14,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."
|
|
hexmask.long.byte 0x0 0.--3. 1. "13-8,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle.."
|
|
wgroup.long ($2+0x130)++0x3
|
|
line.long 0x0 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x0 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0x200)++0x13
|
|
line.long 0x0 "POPT,Prog Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
|
|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
|
|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
line.long 0x4 "PSRC,Prog Set Src Address"
|
|
hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set"
|
|
line.long 0x8 "PCNT,Prog Set Count"
|
|
hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."
|
|
hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
|
|
line.long 0xC "PDST,Prog Set Dst Address"
|
|
hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set"
|
|
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
|
|
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
|
|
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.."
|
|
rgroup.long ($2+0x214)++0x3
|
|
line.long 0x0 "PMPPRXY,Prog Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "SAOPT,Src Actv Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
|
|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
|
|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
rgroup.long ($2+0x244)++0x23
|
|
line.long 0x0 "SASRC,Src Actv Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set"
|
|
line.long 0x4 "SACNT,Src Actv Set A-Count"
|
|
hexmask.long.tbyte 0x4 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
|
|
line.long 0x8 "SADST,Src Actv Set Dst Address"
|
|
hexmask.long 0x8 0.--31. 1. "DADDR,Destination address for Source Active Register Set"
|
|
line.long 0xC "SABIDX,Src Actv Set B-Dim Idx"
|
|
hexmask.long.word 0xC 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
|
|
hexmask.long.word 0xC 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used.."
|
|
line.long 0x10 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
|
|
bitfld.long 0x10 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x10 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
line.long 0x14 "SACNTRLD,Src Actv Set Cnt Reload"
|
|
hexmask.long.word 0x14 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.."
|
|
line.long 0x18 "SASRCBREF,Src Actv Set Src Addr B-Reference"
|
|
hexmask.long 0x18 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
|
|
line.long 0x1C "SADSTBREF,Src Actv Set Dst Addr B-Reference"
|
|
hexmask.long 0x1C 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."
|
|
line.long 0x20 "SABCNT,Src Actv Set B-Count"
|
|
hexmask.long.word 0x20 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT.."
|
|
rgroup.long ($2+0x280)++0x7
|
|
line.long 0x0 "DFCNTRLD,Dst FIFO Set Cnt Reload"
|
|
hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by.."
|
|
line.long 0x4 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
|
|
hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "DFOPT$1,Dst FIFO Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
|
|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
|
|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x304)++0x3
|
|
line.long 0x0 "DFSRC$1,Dst FIFO Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x308)++0x3
|
|
line.long 0x0 "DFACNT$1,Dst FIFO Set A-Count"
|
|
hexmask.long.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x30C)++0x3
|
|
line.long 0x0 "DFDST$1,Dst FIFO Set Dst Address"
|
|
hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set: Initial value is copied from PDST.DADDR. TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued. When a TR.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x310)++0x3
|
|
line.long 0x0 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
|
|
hexmask.long.word 0x0 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x314)++0x3
|
|
line.long 0x0 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x318)++0x3
|
|
line.long 0x0 "DFBCNT$1,Dst FIFO Set B-Count"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x3140000
|
|
tree "MSS_TPTC_B0"
|
|
base ad:0x3180000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x0 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3"
|
|
bitfld.long 0x0 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "WSACTV,Write Status Active WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands. WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write.." "0: Write status is not pending,1: Write Status is pending"
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|
newline
|
|
bitfld.long 0x0 1. "SRCACTV,Source Active State SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1]. SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.."
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|
bitfld.long 0x0 0. "PROGBUSY,Program Register Set Busy PROGBUSY = 0 : Prog set idle and is available for programming. PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy"
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|
line.long 0x4 "INTSTAT,Interrupt Status Register"
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|
bitfld.long 0x4 1. "TRDONE,TR Done Event Status: TRDONE = 0 : Condition not detected. TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to.." "0: Condition not detected,1: Set when TC has completed a Transfer Request"
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|
bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY = 0 : Condition not detected. PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.."
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|
group.long 0x108++0x3
|
|
line.long 0x0 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE = 0 : TRDONE Event is disabled. INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.."
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|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled. INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.."
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|
wgroup.long 0x10C++0x7
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|
line.long 0x0 "INTCLR,Interrupt Clear Register"
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|
bitfld.long 0x0 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE = 0 : Writes of '0' have no effect. INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
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|
bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect. INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
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|
line.long 0x4 "INTCMD,Interrupt Command Register"
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|
bitfld.long 0x4 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
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|
bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
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|
rgroup.long 0x120++0x3
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|
line.long 0x0 "ERRSTAT,Error Status Register"
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|
bitfld.long 0x0 3. "MMRAERR,MMR Address Error: MMRAERR = 0 : Condition not detected. MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.."
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|
bitfld.long 0x0 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1"
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|
newline
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|
bitfld.long 0x0 0. "BUSERR,Bus Error Event: BUSERR = 0: Condition not detected. BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.."
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|
group.long 0x124++0x3
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|
line.long 0x0 "ERREN,Error Enable Register"
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|
bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR = 0 : BUSERR is disabled. ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.."
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|
bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR = 0 : BUSERR is disabled. ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.."
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|
newline
|
|
bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR = 0 : BUSERR is disabled. ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.."
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|
wgroup.long 0x128++0x3
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|
line.long 0x0 "ERRCLR,Error Clear Register"
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|
bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR = 0 : Writes of '0' have no effect. ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR = 0 : Writes of '0' have no effect. ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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|
newline
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bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR = 0 : Writes of '0' have no effect. ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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|
rgroup.long 0x12C++0x3
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|
line.long 0x0 "ERRDET,Error Details Register"
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|
bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
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|
bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
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|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "15-14,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."
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|
hexmask.long.byte 0x0 0.--3. 1. "13-8,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle.."
|
|
wgroup.long 0x130++0x3
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|
line.long 0x0 "ERRCMD,Error Command Register"
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|
bitfld.long 0x0 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
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|
bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
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|
group.long 0x140++0x3
|
|
line.long 0x0 "RDRATE,Read Rate Register"
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|
bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7"
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|
group.long 0x200++0x13
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|
line.long 0x0 "POPT,Prog Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
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|
newline
|
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bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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|
newline
|
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bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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|
line.long 0x4 "PSRC,Prog Set Src Address"
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|
hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set"
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|
line.long 0x8 "PCNT,Prog Set Count"
|
|
hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."
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|
hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
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|
line.long 0xC "PDST,Prog Set Dst Address"
|
|
hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set"
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|
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
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hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
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hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.."
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|
rgroup.long 0x214++0x3
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|
line.long 0x0 "PMPPRXY,Prog Set Mem Protect Proxy"
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|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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|
hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
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|
group.long 0x240++0x3
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|
line.long 0x0 "SAOPT,Src Actv Set Options"
|
|
bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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|
newline
|
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
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|
newline
|
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bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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newline
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bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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rgroup.long 0x244++0x23
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line.long 0x0 "SASRC,Src Actv Set Src Address"
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hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set"
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line.long 0x4 "SACNT,Src Actv Set A-Count"
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hexmask.long.tbyte 0x4 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
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line.long 0x8 "SADST,Src Actv Set Dst Address"
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hexmask.long 0x8 0.--31. 1. "DADDR,Destination address for Source Active Register Set"
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line.long 0xC "SABIDX,Src Actv Set B-Dim Idx"
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hexmask.long.word 0xC 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
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hexmask.long.word 0xC 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used.."
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line.long 0x10 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
|
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bitfld.long 0x10 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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bitfld.long 0x10 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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hexmask.long.byte 0x10 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
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line.long 0x14 "SACNTRLD,Src Actv Set Cnt Reload"
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hexmask.long.word 0x14 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.."
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line.long 0x18 "SASRCBREF,Src Actv Set Src Addr B-Reference"
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hexmask.long 0x18 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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line.long 0x1C "SADSTBREF,Src Actv Set Dst Addr B-Reference"
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hexmask.long 0x1C 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."
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line.long 0x20 "SABCNT,Src Actv Set B-Count"
|
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hexmask.long.word 0x20 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT.."
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|
rgroup.long 0x280++0x7
|
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line.long 0x0 "DFCNTRLD,Dst FIFO Set Cnt Reload"
|
|
hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by.."
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line.long 0x4 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
|
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hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
group.long ($2+0x300)++0x3
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|
line.long 0x0 "DFOPT$1,Dst FIFO Set Options"
|
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bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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|
bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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newline
|
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
|
|
hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
|
|
newline
|
|
bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
|
|
bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x304)++0x3
|
|
line.long 0x0 "DFSRC$1,Dst FIFO Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x308)++0x3
|
|
line.long 0x0 "DFACNT$1,Dst FIFO Set A-Count"
|
|
hexmask.long.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x30C)++0x3
|
|
line.long 0x0 "DFDST$1,Dst FIFO Set Dst Address"
|
|
hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set: Initial value is copied from PDST.DADDR. TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued. When a TR.."
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|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x310)++0x3
|
|
line.long 0x0 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
|
|
hexmask.long.word 0x0 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x314)++0x3
|
|
line.long 0x0 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
|
|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
|
|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x318)++0x3
|
|
line.long 0x0 "DFBCNT$1,Dst FIFO Set B-Count"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
|
|
repeat.end
|
|
tree.end
|
|
tree "MSS_VIM_R5A"
|
|
base ad:0x2080000
|
|
rgroup.long 0x0++0x17
|
|
line.long 0x0 "PID,The Revision Register contains the major and minor revisions for the module."
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
|
|
line.long 0x4 "INFO,The Info Register gives the configuration Inforrmation of this VIM."
|
|
hexmask.long.tbyte 0x4 11.--31. 1. "RES1,RESERVE FIELD"
|
|
hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
|
|
line.long 0x8 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ."
|
|
bitfld.long 0x8 31. "VALID,Indicates that the num field is valid." "0,1"
|
|
hexmask.long.word 0x8 20.--30. 1. "RES2,RESERVE FIELD"
|
|
hexmask.long.byte 0x8 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0x8 10.--15. 1. "RES3,RESERVE FIELD"
|
|
hexmask.long.word 0x8 0.--9. 1. "NUM,Number of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
line.long 0xC "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ."
|
|
bitfld.long 0xC 31. "VALID,Indicates that the num field is valid." "0,1"
|
|
hexmask.long.word 0xC 20.--30. 1. "RES4,RESERVE FIELD"
|
|
hexmask.long.byte 0xC 16.--19. 1. "PRI,Priority of the highest priority pending FIQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0xC 10.--15. 1. "RES5,RESERVE FIELD"
|
|
hexmask.long.word 0xC 0.--9. 1. "NUM,Number of the highest priority pending FIQ. valid only if the valid flag is set."
|
|
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts."
|
|
hexmask.long 0x10 0.--31. 1. "STS,Indicates that the num field is valid."
|
|
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts."
|
|
hexmask.long 0x14 0.--31. 1. "STS,Indicates that the num field is valid."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ."
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true."
|
|
rbitfld.long 0x0 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
|
|
line.long 0x4 "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ."
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true."
|
|
rbitfld.long 0x4 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ."
|
|
bitfld.long 0x0 31. "VALID,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written." "0,1"
|
|
hexmask.long.word 0x0 20.--30. 1. "RES6,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0x0 10.--15. 1. "RES7,RESERVE FIELD"
|
|
hexmask.long.word 0x0 0.--9. 1. "NUM,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set."
|
|
line.long 0x4 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ."
|
|
bitfld.long 0x4 31. "VALID,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written." "0,1"
|
|
hexmask.long.word 0x4 20.--30. 1. "RES8,RESERVE FIELD"
|
|
hexmask.long.byte 0x4 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0x4 10.--15. 1. "RES9,RESERVE FIELD"
|
|
hexmask.long.word 0x4 0.--9. 1. "NUM,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ."
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address."
|
|
rbitfld.long 0x0 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
|
|
hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Read 1 Active/Pending Write 0 No effect Write 1 Set to Interrupt Raw Status"
|
|
line.long 0x4 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
|
|
hexmask.long 0x4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or Disabled Read 1 Active/Pending and Enabled Write 0 No effect Write 1 Clear Interrupt Raw Status"
|
|
line.long 0x8 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
|
|
hexmask.long 0x8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Set Enable"
|
|
line.long 0xC "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
|
|
hexmask.long 0xC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Clear Enable"
|
|
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
|
|
hexmask.long 0x10 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an IRQ Read 1 Active/Pending Enabled and IRQ Write 0 No effect Write 1 Clear.."
|
|
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
|
|
hexmask.long 0x14 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an FIQ Read 1 Active/Pending Enabled and FIQ Write 0 No effect Write 1 Clear.."
|
|
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
|
|
hexmask.long 0x18 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default) 1 FIQ Interrupt"
|
|
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
|
|
hexmask.long 0x1C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.."
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x420)++0x3
|
|
line.long 0x0 "RAW_$1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
|
|
hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Read 1 Active/Pending Write 0 No effect Write 1 Set to Interrupt Raw Status"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x424)++0x3
|
|
line.long 0x0 "STS_$1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or Disabled Read 1 Active/Pending and Enabled Write 0 No effect Write 1 Clear Interrupt Raw Status"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x428)++0x3
|
|
line.long 0x0 "INTR_EN_SET_$1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Set Enable"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x42C)++0x3
|
|
line.long 0x0 "INTER_EN_CLR_$1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Clear Enable"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "IRQSTS_$1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an IRQ Read 1 Active/Pending Enabled and IRQ Write 0 No effect Write 1 Clear.."
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x434)++0x3
|
|
line.long 0x0 "FIQSTS_$1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an FIQ Read 1 Active/Pending Enabled and FIQ Write 0 No effect Write 1 Clear.."
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x438)++0x3
|
|
line.long 0x0 "INTMAP_$1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default) 1 FIQ Interrupt"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x43C)++0x3
|
|
line.long 0x0 "INTTYPE_$1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
|
|
hexmask.long 0x0 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.."
|
|
repeat.end
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat 16. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30)(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40)(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50)(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60)(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70)(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80)(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90)(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0)(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0)(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0)(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0)(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0)(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0)(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 15. (list 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat 16. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30)(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40)(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50)(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60)(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70)(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80)(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90)(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0)(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0)(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0)(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0)(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0)(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0)(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 15. (list 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
tree.end
|
|
tree "MSS_VIM_R5B"
|
|
base ad:0x20A0000
|
|
rgroup.long 0x0++0x17
|
|
line.long 0x0 "PID,The Revision Register contains the major and minor revisions for the module."
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3"
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID"
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release."
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision"
|
|
line.long 0x4 "INFO,The Info Register gives the configuration Inforrmation of this VIM."
|
|
hexmask.long.tbyte 0x4 11.--31. 1. "RES1,RESERVE FIELD"
|
|
hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
|
|
line.long 0x8 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ."
|
|
bitfld.long 0x8 31. "VALID,Indicates that the num field is valid." "0,1"
|
|
hexmask.long.word 0x8 20.--30. 1. "RES2,RESERVE FIELD"
|
|
hexmask.long.byte 0x8 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0x8 10.--15. 1. "RES3,RESERVE FIELD"
|
|
hexmask.long.word 0x8 0.--9. 1. "NUM,Number of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
line.long 0xC "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ."
|
|
bitfld.long 0xC 31. "VALID,Indicates that the num field is valid." "0,1"
|
|
hexmask.long.word 0xC 20.--30. 1. "RES4,RESERVE FIELD"
|
|
hexmask.long.byte 0xC 16.--19. 1. "PRI,Priority of the highest priority pending FIQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0xC 10.--15. 1. "RES5,RESERVE FIELD"
|
|
hexmask.long.word 0xC 0.--9. 1. "NUM,Number of the highest priority pending FIQ. valid only if the valid flag is set."
|
|
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts."
|
|
hexmask.long 0x10 0.--31. 1. "STS,Indicates that the num field is valid."
|
|
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts."
|
|
hexmask.long 0x14 0.--31. 1. "STS,Indicates that the num field is valid."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ."
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true."
|
|
rbitfld.long 0x0 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
|
|
line.long 0x4 "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ."
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true."
|
|
rbitfld.long 0x4 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ."
|
|
bitfld.long 0x0 31. "VALID,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written." "0,1"
|
|
hexmask.long.word 0x0 20.--30. 1. "RES6,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0x0 10.--15. 1. "RES7,RESERVE FIELD"
|
|
hexmask.long.word 0x0 0.--9. 1. "NUM,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set."
|
|
line.long 0x4 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ."
|
|
bitfld.long 0x4 31. "VALID,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written." "0,1"
|
|
hexmask.long.word 0x4 20.--30. 1. "RES8,RESERVE FIELD"
|
|
hexmask.long.byte 0x4 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set."
|
|
hexmask.long.byte 0x4 10.--15. 1. "RES9,RESERVE FIELD"
|
|
hexmask.long.word 0x4 0.--9. 1. "NUM,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ."
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address."
|
|
rbitfld.long 0x0 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
|
|
hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Read 1 Active/Pending Write 0 No effect Write 1 Set to Interrupt Raw Status"
|
|
line.long 0x4 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
|
|
hexmask.long 0x4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or Disabled Read 1 Active/Pending and Enabled Write 0 No effect Write 1 Clear Interrupt Raw Status"
|
|
line.long 0x8 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
|
|
hexmask.long 0x8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Set Enable"
|
|
line.long 0xC "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
|
|
hexmask.long 0xC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Clear Enable"
|
|
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
|
|
hexmask.long 0x10 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an IRQ Read 1 Active/Pending Enabled and IRQ Write 0 No effect Write 1 Clear.."
|
|
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
|
|
hexmask.long 0x14 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an FIQ Read 1 Active/Pending Enabled and FIQ Write 0 No effect Write 1 Clear.."
|
|
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
|
|
hexmask.long 0x18 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default) 1 FIQ Interrupt"
|
|
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
|
|
hexmask.long 0x1C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.."
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x420)++0x3
|
|
line.long 0x0 "RAW_$1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
|
|
hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Read 1 Active/Pending Write 0 No effect Write 1 Set to Interrupt Raw Status"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x424)++0x3
|
|
line.long 0x0 "STS_$1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or Disabled Read 1 Active/Pending and Enabled Write 0 No effect Write 1 Clear Interrupt Raw Status"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x428)++0x3
|
|
line.long 0x0 "INTR_EN_SET_$1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Set Enable"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x42C)++0x3
|
|
line.long 0x0 "INTER_EN_CLR_$1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Disabled Read 1 Enabled Write 0 No effect Write 1 Clear Enable"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "IRQSTS_$1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an IRQ Read 1 Active/Pending Enabled and IRQ Write 0 No effect Write 1 Clear.."
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x434)++0x3
|
|
line.long 0x0 "FIQSTS_$1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive Disabled or not an FIQ Read 1 Active/Pending Enabled and FIQ Write 0 No effect Write 1 Clear.."
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x438)++0x3
|
|
line.long 0x0 "INTMAP_$1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default) 1 FIQ Interrupt"
|
|
repeat.end
|
|
repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x0 0x20 0x40 0x60 0x80 0xA0 0xC0)
|
|
group.long ($2+0x43C)++0x3
|
|
line.long 0x0 "INTTYPE_$1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
|
|
hexmask.long 0x0 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.."
|
|
repeat.end
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat 16. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30)(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40)(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50)(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60)(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70)(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80)(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90)(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0)(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0)(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0)(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0)(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0)(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 16. (list 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0)(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
repeat 15. (list 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8)
|
|
group.long ($2+0x1004)++0x3
|
|
line.long 0x0 "INTPRIORITY_$1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
|
|
hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)"
|
|
repeat.end
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat 16. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30)(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40)(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50)(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60)(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70)(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80)(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90)(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0)(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0)(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0)(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0)(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0)(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 16. (list 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0)(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
repeat 15. (list 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8)
|
|
group.long ($2+0x2004)++0x3
|
|
line.long 0x0 "INTVECTOR_$1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.."
|
|
rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3"
|
|
repeat.end
|
|
tree.end
|
|
tree "MSS_WDT"
|
|
base ad:0x2F7A300
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "RTIGCTRL,Global Control Register starts / stops the counters"
|
|
hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved. Reads return 0 and writes have no effect"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.."
|
|
newline
|
|
bitfld.long 0x0 15. "COS,COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while.." "0: stop counters in debug mode,1: continue counting in debug mode"
|
|
hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved. Reads return 0 and writes have no effect"
|
|
newline
|
|
bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bit.."
|
|
bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start.." "0: stop counters,1: start counters Gives the absolute 32 bits source.."
|
|
line.long 0x4 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
|
|
hexmask.long 0x4 2.--31. 1. "RESERVED3,Reserved"
|
|
bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0.." "0: Do not increment FRC0 on failing external clock,1: Increment FRC0 on failing external clock"
|
|
newline
|
|
bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme,1: MUX is switched to external NTUx clocking scheme"
|
|
line.long 0x8 "RTICAPCTRL,Capture Control controls the capture source for the counters"
|
|
hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1. This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
|
|
newline
|
|
bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0. This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.."
|
|
line.long 0xC "RTICOMPCTRL,Compare Control controls the source for the compare registers"
|
|
hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved. Reads return 0 and writes have no effect"
|
|
bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 9.--11. "RESERVED7,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 5.--7. "RESERVED6,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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bitfld.long 0xC 1.--3. "RESERVED5,Reserved. Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1.." "0: enable compare with FRC 0,1: enable compare with FRC 1"
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line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
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hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
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hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
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hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.."
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group.long 0x20++0x7
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line.long 0x0 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0.."
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line.long 0x4 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0."
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group.long 0x30++0xB
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line.long 0x0 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
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hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by.."
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line.long 0x4 "RTIUC1,Up Counter 1 current value of prescale counter 1"
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hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.."
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line.long 0x8 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
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hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.."
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group.long 0x40++0x7
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line.long 0x0 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
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hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1.."
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line.long 0x4 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
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hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1."
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group.long 0x50++0x27
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line.long 0x0 "RTICOMP0,Compare 0 compare value to be compared with the counters"
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hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x4 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
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hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register. This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x8 "RTICOMP1,Compare 1 compare value to be compared with the counters"
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hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0xC "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
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hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register. This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
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hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
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hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register. This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
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hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.."
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line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
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hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register. This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and.."
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line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
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hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when.."
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line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
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hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.."
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group.long 0x80++0xB
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line.long 0x0 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request" "0: leaves the corresponding bit unchanged,1: enable DMA request"
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hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,1: interrupt is enabled Privilege mode"
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bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt" "0: leaves the corresponding bit unchanged,1: enable interrupt"
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line.long 0x4 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
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hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request" "0: leaves the corresponding bit unchanged,1: disable DMA request"
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hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt" "0: leaves the corresponding bit unchanged,1: disable interrupt"
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line.long 0x8 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
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hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 =.." "0: leaves the bit unchanged,1: set the bit to 0"
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hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0" "0: leaves the bit unchanged,1: set the bit to 0"
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group.long 0x90++0x2F
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line.long 0x0 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
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hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled).."
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line.long 0x4 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
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hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts.."
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line.long 0x8 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
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hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved. Reads return 0 and writes have no effect"
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bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read):.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written.." "0: leaves the current value unchanged,1: clears the bit to 0"
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bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired.." "0: leaves the current value unchanged,1: clears the bit to 0"
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newline
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bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 -> 1 threshold not exceeded 1 = AWD pin 0 -> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0" "0: leaves the current value unchanged,1: clears the bit to 0"
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line.long 0xC "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
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hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.."
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line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
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hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved. Reads return 0 and writes have no effect"
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hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.."
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line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
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hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read) privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.."
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line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
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hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read) privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital.."
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line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
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hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled."
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hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled."
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hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled."
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hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved. Reads return 0 and writes have no effect"
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hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled."
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line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
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hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.."
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line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
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hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.."
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line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
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hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.."
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line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
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hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear. This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.."
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tree.end
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tree "RSS_CSI2A"
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base ad:0x5080000
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rgroup.long 0x0++0x3
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line.long 0x0 "CSI2_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital. For example we have: 0x01 = revision 0.1 and 0x21 = revision 2.1"
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hexmask.long.tbyte 0x0 8.--31. 1. "RES1,RESERVE FIELD"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision"
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|
group.long 0x10++0x3
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line.long 0x0 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register."
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hexmask.long.tbyte 0x0 14.--31. 1. "RES2,RESERVE FIELD"
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newline
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bitfld.long 0x0 12.--13. "MSTANDBY_MODE,RESERVE FIELD" "0,1,2,3"
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newline
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hexmask.long.word 0x0 2.--11. 1. "RES3,RESERVE FIELD"
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newline
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bitfld.long 0x0 1. "SOFT_RESET,Software reset. Set the bit to 1 to trigger a module reset. The bit is automatically reset by the hw. During reads return 0. 0: Normal mode. 1: The module is reset" "0: Normal mode,1: The module is reset"
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newline
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bitfld.long 0x0 0. "AUTO_IDLE,Internal OCP gating strategy 0: OCP clock is free-running. 1: Automatic OCP clock gating strategy is applied based on the OCP interface activity." "0: OCP clock is free-running,1: Automatic OCP clock gating strategy is applied.."
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rgroup.long 0x14++0x3
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line.long 0x0 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register."
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hexmask.long 0x0 1.--31. 1. "RES4,RESERVE FIELD"
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newline
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bitfld.long 0x0 0. "RESET_DONE,Internal reset monitoring Read 0x1: Reset completed. Read 0x0: Internal module reset is on going." "0: Internal module reset is on going,1: Reset completed"
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group.long 0x18++0x7
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line.long 0x0 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt. The context shall be enabled for events to be generated on that context."
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hexmask.long.tbyte 0x0 15.--31. 1. "RES5,RESERVE FIELD"
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newline
|
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bitfld.long 0x0 14. "OCP_ERR_IRQ,OCP Error Interrupt 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x0 13. "SHORT_PACKET_IRQ,Short packet reception status (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event.." "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x0 12. "ECC_CORRECTION_IRQ,ECC has been used to do the correction of the only 1-bit error status (short packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x0 11. "ECC_NO_CORRECTION_IRQ,ECC error status (short and long packets). No correction of the header because of more than 1-bit error. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. -.." "0: READS: Event is false,1: READS: Event is true"
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newline
|
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rbitfld.long 0x0 10. "COMPLEXIO2_ERR_IRQ,RESERVE FIELD" "0,1"
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newline
|
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rbitfld.long 0x0 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: status of the PHY errors received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO). Read 0: READS: Event is false. Read 1: READS: Event is true.." "0: READS: Event is false,1: READS: Event is true"
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newline
|
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bitfld.long 0x0 8. "FIFO_OVF_IRQ,FIFO overflow error status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
|
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rbitfld.long 0x0 7. "CONTEXT7,Context 7 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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newline
|
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rbitfld.long 0x0 6. "CONTEXT6,Context 6 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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newline
|
|
rbitfld.long 0x0 5. "CONTEXT5,Context 5 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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newline
|
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rbitfld.long 0x0 4. "CONTEXT4,Context 4 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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newline
|
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rbitfld.long 0x0 3. "CONTEXT3,Context 3 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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newline
|
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rbitfld.long 0x0 2. "CONTEXT2,Context 2 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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newline
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rbitfld.long 0x0 1. "CONTEXT1,Context 1 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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newline
|
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rbitfld.long 0x0 0. "CONTEXT0,Context 0 Read 0: READS: Event is false. Read 1: READS: Event is true (pending)." "0: READS: Event is false,1: READS: Event is true"
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line.long 0x4 "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually."
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|
hexmask.long.tbyte 0x4 15.--31. 1. "RES6,RESERVE FIELD"
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|
newline
|
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bitfld.long 0x4 14. "OCP_ERR_IRQ,OCP Error Interrupt 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
|
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newline
|
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bitfld.long 0x4 13. "SHORT_PACKET_IRQ,Short packet reception (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x4 12. "ECC_CORRECTION_IRQ,ECC has been used to correct the only 1-bit error (short packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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newline
|
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bitfld.long 0x4 11. "ECC_NO_CORRECTION_IRQ,ECC error (short and long packets). No correction of the header because of more than 1-bit error. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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newline
|
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bitfld.long 0x4 10. "COMPLEXIO2_ERR_IRQ,RESERVED" "0,1"
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|
newline
|
|
bitfld.long 0x4 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: the interrupt is triggered when any error is received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO). 0: Event is masked 1: Event generates an.." "0: Event is masked 1: Event generates an interrupt..,1: the interrupt is triggered when any error is.."
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newline
|
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bitfld.long 0x4 8. "FIFO_OVF_IRQ,FIFO overflow enable 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
|
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bitfld.long 0x4 7. "CONTEXT7,Context 7 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
|
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bitfld.long 0x4 6. "CONTEXT6,Context 6 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
|
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bitfld.long 0x4 5. "CONTEXT5,Context 5 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
|
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bitfld.long 0x4 4. "CONTEXT4,Context 4 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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|
newline
|
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bitfld.long 0x4 3. "CONTEXT3,Context 3 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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|
newline
|
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bitfld.long 0x4 2. "CONTEXT2,Context 2 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
|
|
newline
|
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bitfld.long 0x4 1. "CONTEXT1,Context 1 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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|
newline
|
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bitfld.long 0x4 0. "CONTEXT0,Context 0 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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group.long 0x40++0x3
|
|
line.long 0x0 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified dynamically (except IF_EN bit field)."
|
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hexmask.long.word 0x0 23.--31. 1. "RES7,RESERVE FIELD"
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newline
|
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bitfld.long 0x0 20.--22. "MFLAG_LEVH,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 17.--19. "MFLAG_LEVL,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 16. "BURST_SIZE_EXPAND,Sets the DMA burst size on the L3 interconnect. 0: Use the burst size defined in the BURST_SIZE register 1: Allow generation of 16x64-bit bursts" "0: Use the burst size defined in the BURST_SIZE..,?"
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newline
|
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bitfld.long 0x0 15. "VP_CLK_EN,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "STREAMING,Streaming mode 0: Disable 1: Enable" "0: Disable 1: Enable,?"
|
|
newline
|
|
bitfld.long 0x0 13. "NON_POSTED_WRITE,Not Posted Writes 0: Disable 1: Enable" "0: Disable 1: Enable,?"
|
|
newline
|
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rbitfld.long 0x0 12. "RES8,RESERVE FIELD" "0,1"
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|
newline
|
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bitfld.long 0x0 11. "VP_ONLY_EN,RESERVE FIELD" "0,1"
|
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newline
|
|
bitfld.long 0x0 10. "STREAMING_32_BIT,Indicates if 64-bit or 32-bit streaming burst is used. Valid only if CSI2_CTRL.STREAMING=1 0: 64-bit streaming burst is used; byte enable pattern is 0xFF 1: 32-bit streaming burst is used; byte enable pattern is 0x0F" "0,1"
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newline
|
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bitfld.long 0x0 8.--9. "VP_OUT_CTRL,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 7. "DBG_EN,Enables the debug mode. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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|
newline
|
|
bitfld.long 0x0 5.--6. "BURST_SIZE,Sets the DMA burst size on the L3 interconnect. 0x0: 1x64 OCP writes 0x1: 2x64 OCP writes 0x2: 4x64 OCP writes 0x3: 8x64 OCP writes" "0,1,2,3"
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newline
|
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bitfld.long 0x0 4. "ENDIANNESS,Select endianness for YUV422 8 bit and YUV420 legacy formats. 0: Use native MIPI CSI2 endianness: Little endian for all formats except for YUV422 8b and YUV420 Legacy which a big endian. 1: Store all pixel formats little endian." "0: Use native MIPI CSI2 endianness: Little endian..,1: Store all pixel formats little endian"
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newline
|
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bitfld.long 0x0 3. "FRAME,Set the modality in which IF_EN works. 0: If IF_EN = 0 the interface is disabled immediately. 1: If IF_EN = 1 the interface is disabled after all FEC sync code have been received for the active contexts." "0: If IF_EN = 0 the interface is disabled immediately,1: If IF_EN = 1 the interface is disabled after all.."
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newline
|
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bitfld.long 0x0 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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newline
|
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bitfld.long 0x0 1. "SECURE,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "IF_EN,Enables the physical interface to the module. 0: The interface is disabled. If FRAME = 0 it is disabled immediately. If FRAME = 1 it is disabled when each context has received the FEC sync code. 1: The interface is enabled immediately the.." "0: The interface is disabled,1: The interface is enabled immediately"
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wgroup.long 0x44++0x3
|
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line.long 0x0 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The register is"
|
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hexmask.long 0x0 0.--31. 1. "DBG,32-bit input value."
|
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rgroup.long 0x48++0x3
|
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line.long 0x0 "CSI2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design."
|
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hexmask.long 0x0 6.--31. 1. "RES9,RESERVE FIELD"
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newline
|
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hexmask.long.byte 0x0 2.--5. 1. "FIFODEPTH,Output FIFO size in multiple of 68 bits. Read 0x2: 8x 68 bits Read 0x3: 16x 68 bits Read 0x4: 32x 68 bits Read 0x5: 64x 68 bits Read 0x6: 128 x 68 bits Read 0x7: 256 x 68 bits"
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newline
|
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bitfld.long 0x0 0.--1. "NBCONTEXTS,Number of contexts supported by the module. Read 0x0: 1 Context Read 0x1: 2 Contexts Read 0x2: 4 Contexts Read 0x3: 8 Contexts" "0,1,2,3"
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group.long 0x4C++0xF
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line.long 0x0 "CSI2_COMPLEXIO_CFG2,COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential.."
|
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rbitfld.long 0x0 31. "RES10,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x0 30. "RESET_CTRL,RESERVE FIELD" "0,1"
|
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newline
|
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rbitfld.long 0x0 29. "RESET_DONE,RESERVE FIELD" "0,1"
|
|
newline
|
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bitfld.long 0x0 27.--28. "PWR_CMD,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
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rbitfld.long 0x0 25.--26. "PWR_STATUS,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 24. "PWR_AUTO,RESERVE FIELD" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 20.--23. 1. "RES11,RESERVE FIELD"
|
|
newline
|
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bitfld.long 0x0 19. "DATA4_POL,RESERVE FIELD" "0,1"
|
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newline
|
|
bitfld.long 0x0 16.--18. "DATA4_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x0 15. "DATA3_POL,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x0 12.--14. "DATA3_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x0 11. "DATA2_POL,RESERVE FIELD" "0,1"
|
|
newline
|
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bitfld.long 0x0 8.--10. "DATA2_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x0 7. "DATA1_POL,RESERVE FIELD" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--6. "DATA1_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x0 3. "CLOCK_POL,RESERVE FIELD" "0,1"
|
|
newline
|
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bitfld.long 0x0 0.--2. "CLOCK_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CSI2_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals.."
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|
rbitfld.long 0x4 31. "RES12,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 30. "RESET_CTRL,Controls the reset of the complex IO 0: Complex IO reset active. 1: Complex IO reset de-asserted." "0: Complex IO reset active,1: Complex IO reset de-asserted"
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newline
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rbitfld.long 0x4 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io Read 0: Internal module reset is on going. Read 1: Reset completed." "0: Internal module reset is on going,1: Reset completed"
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newline
|
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bitfld.long 0x4 27.--28. "PWR_CMD,Command for power control of the complex io 0x0: Command to change to OFF state 0x1: Command to change to ON state 0x2: Command to change to Ultra Low Power state" "0: Command to change to OFF state 0x1: Command to..,?,?,?"
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newline
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rbitfld.long 0x4 25.--26. "PWR_STATUS,Status of the power control of the complex io Read 0x0: Complex IO in OFF state Read 0x1: Complex IO in ON state Read 0x2: Complex IO in Ultra Low Power state" "0: Complex IO in OFF state Read 0x1: Complex IO in..,?,?,?"
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newline
|
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bitfld.long 0x4 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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newline
|
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hexmask.long.byte 0x4 20.--23. 1. "RES13,RESERVE FIELD"
|
|
newline
|
|
bitfld.long 0x4 19. "DATA4_POL,+/- differential pin order of DATA lane 4. 0: +/- pin order 1: -/+ pin order" "0,1"
|
|
newline
|
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bitfld.long 0x4 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4. The values 6 and 7 are reserved. 0x0: Not used/connected 0x1: Data lane 4 is at the position 1. 0x2: Data lane 4 is at the position 2. 0x3: Data lane 4 is at the position 3. 0x4: Data lane 4.." "0: Not used/connected 0x1: Data lane 4 is at the..,?,2: Data lane 4 is at the position 2,3: Data lane 4 is at the position 3,4: Data lane 4 is at the position 4,5: Data lane 4 is at the position 5,?,?"
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newline
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bitfld.long 0x4 15. "DATA3_POL,+/- differential pin order of DATA lane 3. 0: +/- pin order 1: -/+ pin order" "0,1"
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|
newline
|
|
bitfld.long 0x4 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3. The values 6 and 7 are reserved. 0x0: Not used/connected 0x1: Data lane 3 is at the position 1. 0x2: Data lane 3 is at the position 2. 0x3: Data lane 3 is at the position 3. 0x4: Data lane 3.." "0: Not used/connected 0x1: Data lane 3 is at the..,?,2: Data lane 3 is at the position 2,3: Data lane 3 is at the position 3,4: Data lane 3 is at the position 4,5: Data lane 3 is at the position 5,?,?"
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newline
|
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bitfld.long 0x4 11. "DATA2_POL,+/- differential pin order of DATA lane 2. 0: +/- pin order 1: -/+ pin order" "0,1"
|
|
newline
|
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bitfld.long 0x4 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2. The values 6 and 7 are reserved. 0x0: Not used/connected 0x1: Data lane 2 is at the position 1. 0x2: Data lane 2 is at the position 2. 0x3: Data lane 2 is at the position 3. 0x4: Data lane 2.." "0: Not used/connected 0x1: Data lane 2 is at the..,?,2: Data lane 2 is at the position 2,3: Data lane 2 is at the position 3,4: Data lane 2 is at the position 4,5: Data lane 2 is at the position 5,?,?"
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newline
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bitfld.long 0x4 7. "DATA1_POL,+/- differential pin order of DATA lane 1. 0: +/- pin order 1: -/+ pin order" "0,1"
|
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newline
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bitfld.long 0x4 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1. 0 6 and 7 are reserved. The data lane 1 is always present. 0x1: Data lane 1 is at the position 1. 0x2: Data lane 1 is at the position 2. 0x3: Data lane 1 is at the position 3. 0x4: Data lane.." "?,1: Data lane 1 is at the position 1,2: Data lane 1 is at the position 2,3: Data lane 1 is at the position 3,4: Data lane 1 is at the position 4,5: Data lane 1 is at the position 5,?,?"
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newline
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bitfld.long 0x4 3. "CLOCK_POL,+/- differential pin order of CLOCK lane. 0: +/- pin order 1: -/+ pin order" "0,1"
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newline
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bitfld.long 0x4 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane. 0 6 and 7 are reserved. The clock lane is always present. 0x1: Clock lane is at the position 1. 0x2: Clock lane is at the position 2. 0x3: Clock lane is at the position 3. 0x4: Clock lane is at.." "?,1: Clock lane is at the position 1,2: Clock lane is at the position 2,3: Clock lane is at the position 3,4: Clock lane is at the position 4,5: Clock lane is at the position 5,?,?"
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line.long 0x8 "CSI2_COMPLEXIO1_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #1"
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hexmask.long.byte 0x8 27.--31. 1. "RES14,RESERVE FIELD"
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newline
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bitfld.long 0x8 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 25. "STATEALLULPMENTER,All active lanes are entering in ULPM. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 19. "ERRCONTROL5,Control error for lane #5 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 18. "ERRCONTROL4,Control error for lane #4 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 17. "ERRCONTROL3,Control error for lane #3 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 16. "ERRCONTROL2,Control error for lane #2 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 15. "ERRCONTROL1,Control error for lane #1 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 14. "ERRESC5,Escape entry error for lane #5 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 13. "ERRESC4,Escape entry error for lane #4 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 12. "ERRESC3,Escape entry error for lane #3 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 11. "ERRESC2,Escape entry error for lane #2 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 10. "ERRESC1,Escape entry error for lane #1 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 4. "ERRSOTHS5,Start of transmission error for lane #5 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 3. "ERRSOTHS4,Start of transmission error for lane #4 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 2. "ERRSOTHS3,Start of transmission error for lane #3 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 1. "ERRSOTHS2,Start of transmission error for lane #2 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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newline
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bitfld.long 0x8 0. "ERRSOTHS1,Start of transmission error for lane #1 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0xC "CSI2_COMPLEXIO2_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #2"
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hexmask.long.byte 0xC 27.--31. 1. "RES15,RESERVE FIELD"
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newline
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bitfld.long 0xC 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 24. "STATEULPM5,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 23. "STATEULPM4,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 22. "STATEULPM3,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 21. "STATEULPM2,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 20. "STATEULPM1,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 14. "ERRESC5,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 13. "ERRESC4,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 12. "ERRESC3,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 11. "ERRESC2,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 10. "ERRESC1,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0xC 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
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rgroup.long 0x5C++0x3
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line.long 0x0 "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F"
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hexmask.long.byte 0x0 24.--31. 1. "RES16,RESERVE FIELD"
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newline
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hexmask.long.tbyte 0x0 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD"
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group.long 0x60++0x7
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line.long 0x0 "CSI2_COMPLEXIO1_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #1"
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hexmask.long.byte 0x0 27.--31. 1. "RES17,RESERVE FIELD"
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newline
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bitfld.long 0x0 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 25. "STATEALLULPMENTER,All active lanes are entering in ULPM. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 19. "ERRCONTROL5,Control error for lane #5 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 18. "ERRCONTROL4,Control error for lane #4 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 17. "ERRCONTROL3,Control error for lane #3 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 16. "ERRCONTROL2,Control error for lane #2 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 15. "ERRCONTROL1,Control error for lane #1 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 14. "ERRESC5,Escape entry error for lane #5 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 13. "ERRESC4,Escape entry error for lane #4 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 12. "ERRESC3,Escape entry error for lane #3 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 11. "ERRESC2,Escape entry error for lane #2 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 10. "ERRESC1,Escape entry error for lane #1 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 4. "ERRSOTHS5,Start of transmission error for lane #5 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 3. "ERRSOTHS4,Start of transmission error for lane #4 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 2. "ERRSOTHS3,Start of transmission error for lane #3 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 1. "ERRSOTHS2,Start of transmission error for lane #2 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x0 0. "ERRSOTHS1,Start of transmission error for lane #1 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0x4 "CSI2_COMPLEXIO2_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #2"
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hexmask.long.byte 0x4 27.--31. 1. "RES18,RESERVE FIELD"
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newline
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bitfld.long 0x4 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 24. "STATEULPM5,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 23. "STATEULPM4,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 22. "STATEULPM3,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 21. "STATEULPM2,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 20. "STATEULPM1,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 14. "ERRESC5,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 13. "ERRESC4,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 12. "ERRESC3,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 11. "ERRESC2,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "ERRESC1,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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newline
|
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bitfld.long 0x4 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x4 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
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wgroup.long 0x68++0x3
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line.long 0x0 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The register.."
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hexmask.long 0x0 0.--31. 1. "DBG,32-bit input value."
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group.long 0x6C++0x11F
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line.long 0x0 "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified while CSI2_CTRL.IF_EN is set to '1'. It is used to indicate the number of L3 cycles for the Stop State monitoring."
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bitfld.long 0x0 31. "FORCE_RX_MODE_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x0 30. "STOP_STATE_X16_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x0 29. "STOP_STATE_X4_IO2,RESERVE FIELD" "0,1"
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hexmask.long.word 0x0 16.--28. 1. "STOP_STATE_COUNTER_IO2,RESERVE FIELD"
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bitfld.long 0x0 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal 0: De-assertion of ForceRxMode. The HW reset the bit at the end of the Force RX Mode assertion. The SW can reset the bit in order to stop the assertion of the ForceRXMode signal prior to the completion of.." "0: De-assertion of ForceRxMode,1: Assertion of ForceRxMode"
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bitfld.long 0x0 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field 0: The number of L3 cycles defined in STOP_STATE _COUNTER is multiplied by 1x 1: The number of L3 cycles defined in STOP_STATE _COUNTER is.." "0: The number of L3 cycles defined in STOP_STATE..,?"
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bitfld.long 0x0 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field 0: The number of L3 cycles defined in STOP_STATE _COUNTER is multiplied by 1x 1: The number of L3 cycles defined in STOP_STATE _COUNTER is.." "0: The number of L3 cycles defined in STOP_STATE..,?"
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hexmask.long.word 0x0 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring. It indicates the number of L3 to monitor for Stop State before de-asserting ForceRxMode (Complex IO #1). The value is from 0 to 8191."
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line.long 0x4 "CSI2_CTX0_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0x4 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x4 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0x4 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x4 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0x4 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0x4 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0x4 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0x4 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0x4 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0x4 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x4 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0x4 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0x4 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x4 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0x4 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0x8 "CSI2_CTX0_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0x8 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0x8 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x8 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0x8 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0x8 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0x8 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0xC "CSI2_CTX0_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0xC 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xC 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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hexmask.long.byte 0xC 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x10 "CSI2_CTX0_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0x10 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x10 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x14 "CSI2_CTX0_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0x14 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x14 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x18 "CSI2_CTX0_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x18 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x18 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0x18 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x18 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x18 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0x18 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x18 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x18 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x18 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x18 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0x1C "CSI2_CTX0_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x1C 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x1C 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x1C 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x1C 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x1C 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0x1C 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x1C 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x1C 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x1C 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x1C 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0x20 "CSI2_CTX0_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0x20 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x20 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0x20 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0x24 "CSI2_CTX1_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0x24 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x24 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0x24 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x24 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0x24 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0x24 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0x24 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0x24 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0x24 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0x24 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x24 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0x24 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0x24 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x24 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0x24 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0x28 "CSI2_CTX1_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0x28 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0x28 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x28 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0x28 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0x28 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0x28 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0x2C "CSI2_CTX1_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0x2C 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x2C 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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line.long 0x30 "CSI2_CTX1_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0x30 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x30 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x34 "CSI2_CTX1_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0x34 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x34 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x38 "CSI2_CTX1_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x38 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x38 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0x38 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x38 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x38 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0x38 4. "RES23,RESERVE FIELD" "0,1"
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newline
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bitfld.long 0x38 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x38 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x38 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x38 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0x3C "CSI2_CTX1_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x3C 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x3C 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x3C 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x3C 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x3C 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0x3C 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x3C 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x3C 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x3C 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x3C 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0x40 "CSI2_CTX1_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0x40 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x40 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0x40 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0x44 "CSI2_CTX2_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0x44 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x44 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0x44 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x44 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0x44 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0x44 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0x44 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0x44 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0x44 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0x44 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x44 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0x44 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0x44 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x44 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0x44 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0x48 "CSI2_CTX2_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0x48 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0x48 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x48 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0x48 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0x48 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0x48 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0x4C "CSI2_CTX2_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0x4C 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x4C 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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line.long 0x50 "CSI2_CTX2_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0x50 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x50 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x54 "CSI2_CTX2_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0x54 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x54 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x58 "CSI2_CTX2_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x58 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x58 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0x58 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x58 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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newline
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bitfld.long 0x58 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0x58 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x58 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x58 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x58 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x58 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0x5C "CSI2_CTX2_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x5C 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x5C 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x5C 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x5C 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x5C 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0x5C 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x5C 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x5C 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x5C 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x5C 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0x60 "CSI2_CTX2_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0x60 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x60 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0x60 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0x64 "CSI2_CTX3_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0x64 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x64 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0x64 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x64 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0x64 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0x64 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0x64 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0x64 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0x64 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0x64 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x64 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0x64 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0x64 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x64 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0x64 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0x68 "CSI2_CTX3_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0x68 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0x68 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x68 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0x68 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0x68 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0x68 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0x6C "CSI2_CTX3_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0x6C 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x6C 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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line.long 0x70 "CSI2_CTX3_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0x70 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x70 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x74 "CSI2_CTX3_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0x74 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x74 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x78 "CSI2_CTX3_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x78 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x78 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0x78 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x78 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x78 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0x78 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x78 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x78 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x78 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x78 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0x7C "CSI2_CTX3_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x7C 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x7C 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x7C 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x7C 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x7C 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0x7C 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x7C 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x7C 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x7C 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x7C 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0x80 "CSI2_CTX3_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0x80 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x80 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0x80 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0x84 "CSI2_CTX4_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0x84 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x84 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0x84 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x84 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0x84 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0x84 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0x84 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0x84 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0x84 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0x84 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0x84 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0x84 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0x84 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x84 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0x84 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0x88 "CSI2_CTX4_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0x88 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0x88 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x88 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0x88 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0x88 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0x88 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0x8C "CSI2_CTX4_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0x8C 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x8C 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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line.long 0x90 "CSI2_CTX4_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0x90 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x90 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x94 "CSI2_CTX4_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0x94 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0x94 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0x98 "CSI2_CTX4_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x98 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x98 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0x98 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x98 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x98 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0x98 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x98 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x98 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x98 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0x98 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0x9C "CSI2_CTX4_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0x9C 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x9C 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x9C 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x9C 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x9C 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0x9C 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x9C 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x9C 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x9C 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0x9C 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0xA0 "CSI2_CTX4_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0xA0 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xA0 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0xA0 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0xA4 "CSI2_CTX5_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0xA4 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0xA4 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0xA4 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xA4 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0xA4 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0xA4 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0xA4 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0xA4 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0xA4 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0xA4 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0xA4 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0xA4 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0xA4 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xA4 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0xA4 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0xA8 "CSI2_CTX5_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0xA8 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0xA8 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xA8 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0xA8 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0xA8 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0xA8 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0xAC "CSI2_CTX5_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0xAC 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xAC 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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line.long 0xB0 "CSI2_CTX5_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0xB0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0xB0 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0xB4 "CSI2_CTX5_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0xB4 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0xB4 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0xB8 "CSI2_CTX5_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0xB8 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xB8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0xB8 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xB8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xB8 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0xB8 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xB8 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xB8 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xB8 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xB8 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0xBC "CSI2_CTX5_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0xBC 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xBC 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xBC 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xBC 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xBC 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0xBC 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xBC 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xBC 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xBC 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xBC 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0xC0 "CSI2_CTX5_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0xC0 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xC0 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0xC0 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0xC4 "CSI2_CTX6_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0xC4 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0xC4 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0xC4 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0xC4 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0xC4 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0xC4 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0xC4 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0xC4 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0xC4 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0xC4 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0xC4 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0xC4 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0xC4 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0xC8 "CSI2_CTX6_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0xC8 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0xC8 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xC8 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0xC8 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0xC8 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0xC8 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0xCC "CSI2_CTX6_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0xCC 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xCC 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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line.long 0xD0 "CSI2_CTX6_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0xD0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0xD0 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0xD4 "CSI2_CTX6_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0xD4 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0xD4 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0xD8 "CSI2_CTX6_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0xD8 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xD8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0xD8 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xD8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xD8 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0xD8 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xD8 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xD8 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xD8 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xD8 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0xDC "CSI2_CTX6_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0xDC 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xDC 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xDC 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xDC 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xDC 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0xDC 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xDC 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xDC 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xDC 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xDC 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0xE0 "CSI2_CTX6_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0xE0 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xE0 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0xE0 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0xE4 "CSI2_CTX7_CTRL1,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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bitfld.long 0xE4 31. "BYTESWAP,Allows swapping bytes two by two in the payload data. It doesn't affect - short packets - long packet header or footers - CRC calculation The purpose is to by swap data send to the OCP port and/or video port 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0xE4 30. "GENERIC,Enables the generic mode. 0: Disabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet code transmitted in the MIPI stream is used. 1: Enabled. Data is received according to CSI2_CTX_CTRL1.FORMAT and the long packet.." "0: Disabled,1: Enabled"
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rbitfld.long 0xE4 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 28. "HSCALE,Enable horizontal downscaling by a factor of two. Applies to RAW data when transcoding is enabled. Must be disabled when transcoding is disabled. 0: Disable 1: Enable" "0: Disable 1: Enable,?"
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hexmask.long.byte 0xE4 24.--27. 1. "TRANSCODE,Enables image transcoding. When this features is enabled: - the data format from the camera is defined by the FORMAT register - the format after transcode is defined by the TRANSCODE register. The memory storage / video port formats is defined.."
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hexmask.long.byte 0xE4 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory. (shall be used only in interlace mode otherwise set to '1')"
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hexmask.long.byte 0xE4 8.--15. 1. "COUNT,Sets the number of frame to acquire. Once the frame acquisition starts the COUNT value is decremented after every frame. When COUNT reaches 0 the FRAME_NUMBER_IRQ interrupt is triggered and CTX_EN is set to '0'. Writes to this bit field are.."
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bitfld.long 0xE4 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame Read 0: The end of frame signal is not asserted at the end of each frame. Read 1: The end of frame signal is asserted at the end of each frame." "0: The end of frame signal is not asserted at the..,1: The end of frame signal is asserted at the end.."
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bitfld.long 0xE4 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line. Read 0: The end of line signal is not asserted at the end of each frame. Read 1: The end of line signal is asserted at the end of each frame." "0: The end of line signal is not asserted at the..,1: The end of line signal is asserted at the end of.."
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bitfld.long 0xE4 5. "CS_EN,Enables the checksum check for the received payload (long packet only). 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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bitfld.long 0xE4 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field. Write 0: COUNT bit field is locked. Writes have no effect Write 1: COUNT bit field is unlocked. Writes are possible." "0: COUNT bit field is locked,1: COUNT bit field is unlocked"
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rbitfld.long 0xE4 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame. This bit field toggles after every FEC_NUMBER FEC sync code received for the current context. Read 0:.." "0: PING buffer Read 1: PONG buffer,?"
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bitfld.long 0xE4 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 1. "LINE_MODULO,Line modulo configuration 0: CSI2_CTX_CTRL3.LINE_NUMBER is used once per frame for the generation of the LINE_NUMBER_IRQ. 1: CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo number for the generation of the LINE_NUMBER_IRQ (multiple times.." "0: CSI2_CTX_CTRL3,1: CSI2_CTX_CTRL3"
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bitfld.long 0xE4 0. "CTX_EN,Enables the Context 0: Disabled 1: Enabled" "0: Disabled 1: Enabled,?"
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line.long 0xE8 "CSI2_CTX7_CTRL2,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and.."
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hexmask.long.word 0xE8 16.--31. 1. "FRAME,Frame number. The CSI-2 protocol engine extracts the frame number from the SOF short packet sent by the camera."
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rbitfld.long 0xE8 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xE8 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT 0x0: RAW6 0x1: RAW7 0x2: RAW8 (not valid if FORMAT is USER_DEFINED_8_BIT_DATA_TYPE_x_EXP8 with x from 1 to 8)" "0: RAW6 0x1: RAW7 0x2: RAW8,?,?,?"
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bitfld.long 0xE8 11.--12. "VIRTUAL_ID,Virtual channel ID 0x0: Virtual Channel ID 0 0x1: Virtual Channel ID 1 0x2: Virtual Channel ID 2 0x3: Virtual Channel ID 3" "0: Virtual Channel ID 0 0x1: Virtual Channel ID 1..,?,?,?"
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bitfld.long 0xE8 10. "DPCM_PRED,Selects the DPCM predictor. 0: The advanced predictor is used. Not supported for 10 - 8 - 10 algorithm. Performance limited to 1 pixel/cycle. 1: The simple predictor is used." "0: The advanced predictor is used,1: The simple predictor is used"
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hexmask.long.word 0xE8 0.--9. 1. "FORMAT,Data format selection. 0x000: OTHERS (except NULL and BLANKING packets) 0x012: Embedded 8-bit non-image data (e.g. JPEG) 0x018: YUV420 8bit 0x019: YUV420 10bit 0x01A: YUV420 8bit legacy 0x01C: YUV420 8bit + CSPS 0x01D: YUV420 10bit +.."
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line.long 0xEC "CSI2_CTX7_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and.."
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hexmask.long.word 0xEC 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xEC 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement). If OFST = 0 the data is written contiguously in memory. Otherwise OFST sets the destination offset between the first pixel of the previous line and the first pixel of the current line."
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line.long 0xF0 "CSI2_CTX7_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled.."
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hexmask.long 0xF0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0xF0 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0xF4 "CSI2_CTX7_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled.."
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hexmask.long 0xF4 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address."
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hexmask.long.byte 0xF4 0.--4. 1. "RES,RESERVE FIELD"
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line.long 0xF8 "CSI2_CTX7_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0xF8 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xF8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only). 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,1: bit error"
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bitfld.long 0xF8 7. "LINE_NUMBER_IRQ,Context - Line number is reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xF8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xF8 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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rbitfld.long 0xF8 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xF8 3. "LE_IRQ,Context - Line end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xF8 2. "LS_IRQ,Context - Line start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xF8 1. "FE_IRQ,Context - Frame end sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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bitfld.long 0xF8 0. "FS_IRQ,Context - Frame start sync code detection. 0: Event is masked 1: Event generates an interrupt when it occurs" "0: Event is masked 1: Event generates an interrupt..,?"
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line.long 0xFC "CSI2_CTX7_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context."
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hexmask.long.tbyte 0xFC 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xFC 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only). 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW.." "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xFC 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xFC 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xFC 5. "CS_IRQ,Context - Check-Sum mismatch status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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rbitfld.long 0xFC 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xFC 3. "LE_IRQ,Context - Line end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. . - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xFC 2. "LS_IRQ,Context - Line start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xFC 1. "FE_IRQ,Context - Frame end sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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bitfld.long 0xFC 0. "FS_IRQ,Context - Frame start sync code detection status. 0: READS: Event is false. WRITES: Status bit unchanged. 1: READS: Event is true (pending). WRITES: Status bit is reset. - (RW W1toClr)" "0: READS: Event is false,1: READS: Event is true"
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line.long 0x100 "CSI2_CTX7_CTRL3,CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code."
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rbitfld.long 0x100 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x100 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444. When TRANSCODE=1 and BYS=1 Image width in pixels acquired from the BYS port."
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hexmask.long.word 0x100 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
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line.long 0x104 "CSI2_PHY_CFG_REG0,"
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hexmask.long.byte 0x104 24.--31. 1. "HS_CLK_CONFIG,Disable clock missing detector"
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hexmask.long.byte 0x104 16.--23. 1. "RESERVED,RESERVED"
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hexmask.long.byte 0x104 8.--15. 1. "THS_TERM,Ths-term timing parameter in multiples of DDR clock. Effective time for enabling of termination= synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* DDRCLK + THS-TERM + ~ (1-15) ns Programmed value = ceil(12.5 /.."
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hexmask.long.byte 0x104 0.--7. 1. "THS_SETTLE,THS-SETTLE timing parameter in multiples on DDR clock frequency. Effective Ths-settle seen on line (starting to look for sync pattern) = synchronizer delay + timer delay + LPRX delay + combinational routing delay - pipeline delay in HS data.."
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line.long 0x108 "CSI2_PHY_CFG_REG1,"
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bitfld.long 0x108 30.--31. "RSVD2,Reserved" "0,1,2,3"
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rbitfld.long 0x108 29. "RESETDONECTRLCLK,RESETDONECTRLCLK" "0,1"
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rbitfld.long 0x108 28. "RESETDONERXBYTECLK,RESETDONERXBYTECLK" "0,1"
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bitfld.long 0x108 26.--27. "RSVD1,Reserved" "0,1,2,3"
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rbitfld.long 0x108 25. "CLK_MISS_DET,1: Error in clock missing detector 0: Clock missing detector successful." "0: Clock missing detector successful,1: Error in clock missing detector"
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hexmask.long.byte 0x108 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value =.."
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hexmask.long.byte 0x108 10.--17. 1. "D_PHY_HS_SYNC_PAT,DPHY mode HS sync pattern in byte order (reverse of RW 0xB8 received order) D-PHY mode sync pattern. Default : '10111000'"
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bitfld.long 0x108 8.--9. "CTRLCLK_DIV_FACT,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3"
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hexmask.long.byte 0x108 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~(1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.."
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line.long 0x10C "CSI2_PHY_CFG_REG2,"
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bitfld.long 0x10C 30.--31. "RXTRIGGERESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3"
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bitfld.long 0x10C 28.--29. "RXTRIGGERESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3"
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bitfld.long 0x10C 26.--27. "RXTRIGGERESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2." "0,1,2,3"
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bitfld.long 0x10C 24.--25. "RXTRIGGERESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3"
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hexmask.long.tbyte 0x10C 0.--23. 1. "CCP2_SYNC_PAT,CCP2 mode sync pattern in byte order (reverse of received order)"
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line.long 0x110 "CSI2_PHY_CFG_REG3,"
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bitfld.long 0x110 31. "OVR_ENHSRX,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x110 26.--30. 1. "ENHSRX,RESERVE FIELD"
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bitfld.long 0x110 25. "OVR_ENRXTERM,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x110 20.--24. 1. "ENRXTERM,RESERVE FIELD"
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bitfld.long 0x110 19. "OVR_ENLPRX,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x110 14.--18. 1. "ENLPRX,RESERVE FIELD"
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hexmask.long.byte 0x110 9.--13. 1. "ENULPRX,RESERVE FIELD"
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bitfld.long 0x110 8. "OVR_ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x110 7. "ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x110 6. "OVR_ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x110 5. "ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x110 4. "OVR_ENCCP_TO_ANAT,RESERVE FIELD" "0,1"
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bitfld.long 0x110 3. "OVR_ENCCP_TO_HSRX,RESERVE FIELD" "0,1"
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bitfld.long 0x110 2. "RSVD1,RESERVE FIELD" "0,1"
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bitfld.long 0x110 1. "RECAL_HS_RX,RESERVE FIELD" "0,1"
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bitfld.long 0x110 0. "RECAL_BIAS,RESERVE FIELD" "0,1"
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line.long 0x114 "CSI2_PHY_CFG_REG4,"
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hexmask.long.byte 0x114 27.--31. 1. "TRIM_BIAS_GEN,RESERVE FIELD"
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hexmask.long.byte 0x114 22.--26. 1. "TRIM_TERM_LANE4,RESERVE FIELD"
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hexmask.long.byte 0x114 17.--21. 1. "TRIM_TERM_LANE3,RESERVE FIELD"
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hexmask.long.byte 0x114 12.--16. 1. "TRIM_TERM_LANE2,RESERVE FIELD"
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hexmask.long.byte 0x114 7.--11. 1. "TRIM_TERM_LANE1,RESERVE FIELD"
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hexmask.long.byte 0x114 2.--6. 1. "TRIM_TERM_LANE0,RESERVE FIELD"
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bitfld.long 0x114 1. "BYPASS_EFUSE,RESERVE FIELD" "0,1"
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bitfld.long 0x114 0. "RSVD1,RESERVE FIELD" "0,1"
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line.long 0x118 "CSI2_PHY_CFG_REG5,"
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hexmask.long.byte 0x118 26.--31. 1. "TRIM_OFFSET_LANE4_HS_RX,RESERVE FIELD"
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hexmask.long.byte 0x118 20.--25. 1. "TRIM_OFFSET_LANE3_HS_RX,RESERVE FIELD"
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hexmask.long.byte 0x118 14.--19. 1. "TRIM_OFFSET_LANE2_HS_RX,RESERVE FIELD"
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hexmask.long.byte 0x118 8.--13. 1. "TRIM_OFFSET_LANE1_HS_RX,RESERVE FIELD"
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hexmask.long.byte 0x118 2.--7. 1. "TRIM_OFFSET_LANE0_HS_RX,RESERVE FIELD"
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bitfld.long 0x118 1. "BYPASS_CALIB_OFFSET,RESERVE FIELD" "0,1"
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bitfld.long 0x118 0. "RSVD1,RESERVE FIELD" "0,1"
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line.long 0x11C "CSI2_PHY_CFG_REG6,"
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hexmask.long.word 0x11C 21.--31. 1. "RSVD2,RESERVE FIELD"
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bitfld.long 0x11C 20. "OVR_AFE_LANE_ADR_POL,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x11C 12.--19. 1. "AFE_LANE_SEL,RESERVE FIELD"
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bitfld.long 0x11C 11. "AFE_LANE_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x11C 10. "HSCOMOOUT,RESERVE FIELD" "0,1"
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bitfld.long 0x11C 9. "BYPASS_LDO_REG,RESERVE FIELD" "0,1"
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bitfld.long 0x11C 8. "OBSV_LDO_VOLT_DYA,RESERVE FIELD" "0,1"
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bitfld.long 0x11C 7. "OBSV_BIAS_CURR_DXA,RESERVE FIELD" "0,1"
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bitfld.long 0x11C 6. "RSVD1,RESERVE FIELD" "0,1"
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bitfld.long 0x11C 5. "BIASGEN_CAL_OVR,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x11C 0.--4. 1. "BIASGEN_CAL_OVR_VAL,RESERVE FIELD"
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group.long 0x1C0++0x3F
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line.long 0x0 "CSI2_CTX0_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
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rbitfld.long 0x0 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
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rbitfld.long 0x0 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
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line.long 0x4 "CSI2_CTX0_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
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rbitfld.long 0x4 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x4 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
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rbitfld.long 0x4 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x4 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
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line.long 0x8 "CSI2_CTX1_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
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rbitfld.long 0x8 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x8 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
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rbitfld.long 0x8 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x8 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
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line.long 0xC "CSI2_CTX1_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
|
|
rbitfld.long 0xC 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0xC 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
|
|
newline
|
|
rbitfld.long 0xC 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0xC 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
|
|
line.long 0x10 "CSI2_CTX2_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
|
|
rbitfld.long 0x10 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x10 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x10 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x10 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
|
|
line.long 0x14 "CSI2_CTX2_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
|
|
rbitfld.long 0x14 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x14 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x14 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x14 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
|
|
line.long 0x18 "CSI2_CTX3_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
|
|
rbitfld.long 0x18 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x18 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x18 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x18 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
|
|
line.long 0x1C "CSI2_CTX3_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
|
|
rbitfld.long 0x1C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x1C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x1C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
|
|
line.long 0x20 "CSI2_CTX4_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
|
|
rbitfld.long 0x20 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x20 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x20 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x20 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
|
|
line.long 0x24 "CSI2_CTX4_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
|
|
rbitfld.long 0x24 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x24 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x24 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x24 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
|
|
line.long 0x28 "CSI2_CTX5_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
|
|
rbitfld.long 0x28 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x28 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x28 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x28 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
|
|
line.long 0x2C "CSI2_CTX5_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
|
|
rbitfld.long 0x2C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x2C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x2C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
|
|
line.long 0x30 "CSI2_CTX6_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
|
|
rbitfld.long 0x30 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x30 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x30 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x30 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
|
|
line.long 0x34 "CSI2_CTX6_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
|
|
rbitfld.long 0x34 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x34 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x34 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x34 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
|
|
line.long 0x38 "CSI2_CTX7_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
|
|
rbitfld.long 0x38 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x38 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191. Pixels HSKIP-WIDTH pixels are output when HCOUNT=0. WIDTH corresponds to the image width provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x38 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x38 0.--12. 1. "HSKIP,Pixel to skip horizontally. Valid values: 0-8191"
|
|
line.long 0x3C "CSI2_CTX7_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
|
|
rbitfld.long 0x3C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x3C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191. Pixels VSKIP-HEIGHT pixels are output when VCOUNT=0. HEIGHT corresponds to the image height provided by the sensor."
|
|
newline
|
|
rbitfld.long 0x3C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x3C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
|
|
tree.end
|
|
tree "RSS_CTRL"
|
|
base ad:0x5020000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
group.long 0x8++0x1F
|
|
line.long 0x0 "RSS_TPCC_A_ERRAGG_MASK,"
|
|
bitfld.long 0x0 25. "tptc_a0_read_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "tpcc_a_read_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "tptc_a0_write_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "tpcc_a_write_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "tpcc_a_parity_err," "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "tptc_a0_err," "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "tpcc_a_mpint," "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "tpcc_a_errint," "0,1"
|
|
line.long 0x4 "RSS_TPCC_A_ERRAGG_STATUS,"
|
|
bitfld.long 0x4 25. "tptc_a0_read_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "tpcc_a_read_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "tptc_a0_write_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "tpcc_a_write_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "tpcc_a_parity_err," "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "tptc_a0_err," "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "tpcc_a_mpint," "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "tpcc_a_errint," "0,1"
|
|
line.long 0x8 "RSS_TPCC_A_ERRAGG_STATUS_RAW,"
|
|
bitfld.long 0x8 25. "tptc_a0_read_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "tpcc_a_read_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "tptc_a0_write_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "tpcc_a_write_access_error," "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "tpcc_a_parity_err," "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "tptc_a0_err," "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "tpcc_a_mpint," "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "tpcc_a_errint," "0,1"
|
|
line.long 0xC "RSS_TPCC_A_INTAGG_MASK,"
|
|
bitfld.long 0xC 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt RCSS_TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
|
|
newline
|
|
bitfld.long 0xC 8. "tpcc_a_int7," "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "tpcc_a_int6," "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "tpcc_a_int5," "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "tpcc_a_int4," "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "tpcc_a_int3," "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "tpcc_a_int2," "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "tpcc_a_int1," "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "tpcc_a_int0," "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "tpcc_a_intg," "0,1"
|
|
line.long 0x10 "RSS_TPCC_A_INTAGG_STATUS,"
|
|
bitfld.long 0x10 16. "tptc_a0,Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in RCSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "tpcc_a_int7," "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "tpcc_a_int6," "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "tpcc_a_int5," "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "tpcc_a_int4," "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "tpcc_a_int3," "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "tpcc_a_int2," "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "tpcc_a_int1," "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "tpcc_a_int0," "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "tpcc_a_intg," "0,1"
|
|
line.long 0x14 "RSS_TPCC_A_INTAGG_STATUS_RAW,"
|
|
bitfld.long 0x14 16. "tptc_a0,Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in RCSS_TPCC_A_INTAGG_MASK" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "tpcc_a_int7," "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "tpcc_a_int6," "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "tpcc_a_int5," "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "tpcc_a_int4," "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "tpcc_a_int3," "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "tpcc_a_int2," "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "tpcc_a_int1," "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "tpcc_a_int0," "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "tpcc_a_intg," "0,1"
|
|
line.long 0x18 "RSS_TPCC_MEMINIT_START,"
|
|
bitfld.long 0x18 0. "tpcc_a_meminit_start,Start Memory intialization of memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed." "0,1"
|
|
line.long 0x1C "RSS_TPCC_MEMINIT_DONE,"
|
|
bitfld.long 0x1C 0. "tpcc_a_meminit_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "RSS_TPCC_MEMINIT_STATUS,"
|
|
bitfld.long 0x0 0. "tpcc_a_meminit_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
|
|
group.long 0x2C++0x7
|
|
line.long 0x0 "TPTC_DBS_CFG,"
|
|
bitfld.long 0x0 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
|
|
line.long 0x4 "RSS_TPCC_A_PARITY_CTRL,"
|
|
bitfld.long 0x4 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "parity_testen,Enable Parity Test for TPCC. Write 0x1 : Parity Test is enabled on PARAM memory" "?,1: Parity Test is enabled on PARAM memory"
|
|
newline
|
|
bitfld.long 0x4 0. "parity_en,Enable Parity for TPCC. Write 0x1 : Parity is enabled on PARAM memory" "?,1: Parity is enabled on PARAM memory"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "RSS_TPCC_A_PARITY_STATUS,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
|
|
group.long 0x38++0x27
|
|
line.long 0x0 "RSS_CSI2A_CFG,"
|
|
bitfld.long 0x0 28.--30. "sof_intr1_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT1 Write 0 : Start of Frame for Context 0 will be propagated on this interrupt line Write 7 : Start of Frame for Context 7 will be propagated on this interrupt line" "0: Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "sof_intr0_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT0 Write 0 : Start of Frame for Context 0 will be propagated on this interrupt line Write 7 : Start of Frame for Context 7 will be propagated on this interrupt line" "0: Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "eof_intr1_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT1 Write 0 : Start of Frame for Context 0 will be propagated on this interrupt line Write 7 : Start of Frame for Context 7 will be propagated on this interrupt line" "0: Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "eof_intr0_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT0 Write 0 : Start of Frame for Context 0 will be propagated on this interrupt line Write 7 : Start of Frame for Context 7 will be propagated on this interrupt line" "0: Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 16. "sign_ext_en,Sign Extention Enable for CSI2 A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "mwait,Power Idle Protocol related Mwait Port" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "lane_enable,Lane enable for CSI2 A"
|
|
line.long 0x4 "RSS_CSI2A_CTX0_LINE_PING_PONG,"
|
|
bitfld.long 0x4 16. "enable,Enable line based ping pong toggle for Context 0 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 0"
|
|
line.long 0x8 "RSS_CSI2A_CTX1_LINE_PING_PONG,"
|
|
bitfld.long 0x8 16. "enable,Enable line based ping pong toggle for Context 1 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 1"
|
|
line.long 0xC "RSS_CSI2A_CTX2_LINE_PING_PONG,"
|
|
bitfld.long 0xC 16. "enable,Enable line based ping pong toggle for Context 2 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 2"
|
|
line.long 0x10 "RSS_CSI2A_CTX3_LINE_PING_PONG,"
|
|
bitfld.long 0x10 16. "enable,Enable line based ping pong toggle for Context 3 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 3"
|
|
line.long 0x14 "RSS_CSI2A_CTX4_LINE_PING_PONG,"
|
|
bitfld.long 0x14 16. "enable,Enable line based ping pong toggle for Context 4 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 4"
|
|
line.long 0x18 "RSS_CSI2A_CTX5_LINE_PING_PONG,"
|
|
bitfld.long 0x18 16. "enable,Enable line based ping pong toggle for Context 5 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 5"
|
|
line.long 0x1C "RSS_CSI2A_CTX6_LINE_PING_PONG,"
|
|
bitfld.long 0x1C 16. "enable,Enable line based ping pong toggle for Context 6 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 6"
|
|
line.long 0x20 "RSS_CSI2A_CTX7_LINE_PING_PONG,"
|
|
bitfld.long 0x20 16. "enable,Enable line based ping pong toggle for Context 7 0 : Diabled 1:Enabled" "0: Diabled 1:Enabled,?"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 7"
|
|
line.long 0x24 "RSS_CSI2A_PARITY_CTRL,"
|
|
bitfld.long 0x24 16. "fifo_parity_en,Enable Parity for CSI2 FIFO Memory. Write 0x1 : Parity is enabled" "?,1: Parity is enabled"
|
|
newline
|
|
bitfld.long 0x24 0. "ctx_parity_en,Enable Parity for CSI2 CTX Memory. Write 0x1 : Parity is enabled" "?,1: Parity is enabled"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "RSS_CSI2A_PARITY_STATUS,"
|
|
hexmask.long.byte 0x0 16.--22. 1. "fifo_parity_addr,CSI2 FIFO Memory Error Address at which Parity Error occurred"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ctx_parity_addr,CSI2 CTX Memory Error Address at which Parity Error occurred"
|
|
group.long 0x64++0x1B
|
|
line.long 0x0 "RSS_CSI2A_LANE0_CFG,"
|
|
rbitfld.long 0x0 19. "dy0_wuevnt,Pad DY Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "dy0_wuen,Pad DY Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "dy0_ie,Pad DY Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "dy0_in,Pad DY Input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "dy0_enbpd,Pad DY Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "dy0_enbpu,Pad DY Enable Pull Up" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 13. "dx0_wuclkout,Pad DX Wakeup Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 12. "dx0_wuout,Pad DX Wakeup Output" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 11. "dx0_isoclkout,Pad DX Isosaltion Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 10. "dx0_isoout,Pad DX Isosaltion Output" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 9. "dx0_wuevnt,Pad DX Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "dx0_wuen,Pad DX Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "dx0_wuclkin,Pad DX Wakeup Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "dx0_wuin,Pad DX Wakeup Input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "dx0_isoclkin,Pad DX Isolation Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dx0_isoin,Pad DX Isosaltion Input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "dx0_ie,Pad DX Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "dx0_in,Pad DX Input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "dx0_enbpd,Pad DX Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "dx0_enbpu,Pad DX Enable Pull Up" "0,1"
|
|
line.long 0x4 "RSS_CSI2A_LANE1_CFG,"
|
|
rbitfld.long 0x4 19. "dy1_wuevnt,Pad DY Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "dy1_wuen,Pad DY Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "dy1_ie,Pad DY Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 16. "dy1_in,Pad DY Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "dy1_enbpd,Pad DY Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "dy1_enbpu,Pad DY Enable Pull Up" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 13. "dx1_wuclkout,Pad DX Wakeup Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 12. "dx1_wuout,Pad DX Wakeup Output" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 11. "dx1_isoclkout,Pad DX Isosaltion Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 10. "dx1_isoout,Pad DX Isosaltion Output" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 9. "dx1_wuevnt,Pad DX Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "dx1_wuen,Pad DX Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "dx1_wuclkin,Pad DX Wakeup Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "dx1_wuin,Pad DX Wakeup Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "dx1_isoclkin,Pad DX Isolation Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "dx1_isoin,Pad DX Isosaltion Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "dx1_ie,Pad DX Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 2. "dx1_in,Pad DX Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "dx1_enbpd,Pad DX Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "dx1_enbpu,Pad DX Enable Pull Up" "0,1"
|
|
line.long 0x8 "RSS_CSI2A_LANE2_CFG,"
|
|
rbitfld.long 0x8 19. "dy2_wuevnt,Pad DY Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "dy2_wuen,Pad DY Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "dy2_ie,Pad DY Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 16. "dy2_in,Pad DY Input" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "dy2_enbpd,Pad DY Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "dy2_enbpu,Pad DY Enable Pull Up" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 9. "dx2_wuevnt,Pad DX Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "dx2_wuen,Pad DX Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "dx2_wuclkin,Pad DX Wakeup Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "dx2_wuin,Pad DX Wakeup Input" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "dx2_isoclkin,Pad DX Isolation Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "dx2_isoin,Pad DX Isosaltion Input" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "dx2_ie,Pad DX Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 2. "dx2_in,Pad DX Input" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "dx2_enbpd,Pad DX Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "dx2_enbpu,Pad DX Enable Pull Up" "0,1"
|
|
line.long 0xC "RSS_CSI2A_LANE3_CFG,"
|
|
rbitfld.long 0xC 19. "dy3_wuevnt,Pad DY Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "dy3_wuen,Pad DY Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "dy3_ie,Pad DY Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 16. "dy3_in,Pad DY Input" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "dy3_enbpd,Pad DY Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "dy3_enbpu,Pad DY Enable Pull Up" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 13. "dx3_wuclkout,Pad DX Wakeup Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 12. "dx3_wuout,Pad DX Wakeup Output" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 11. "dx3_isoclkout,Pad DX Isosaltion Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 10. "dx3_isoout,Pad DX Isosaltion Output" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 9. "dx3_wuevnt,Pad DX Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "dx3_wuen,Pad DX Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "dx3_wuclkin,Pad DX Wakeup Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "dx3_wuin,Pad DX Wakeup Input" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "dx3_isoclkin,Pad DX Isolation Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "dx3_isoin,Pad DX Isosaltion Input" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "dx3_ie,Pad DX Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 2. "dx3_in,Pad DX Input" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "dx3_enbpd,Pad DX Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "dx3_enbpu,Pad DX Enable Pull Up" "0,1"
|
|
line.long 0x10 "RSS_CSI2A_LANE4_CFG,"
|
|
rbitfld.long 0x10 19. "dy4_wuevnt,Pad DY Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "dy4_wuen,Pad DY Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "dy4_ie,Pad DY Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 16. "dy4_in,Pad DY Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "dy4_enbpd,Pad DY Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "dy4_enbpu,Pad DY Enable Pull Up" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 13. "dx4_wuclkout,Pad DX Wakeup Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 12. "dx4_wuout,Pad DX Wakeup Output" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 11. "dx4_isoclkout,Pad DX Isosaltion Clkout" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 10. "dx4_isoout,Pad DX Isosaltion Output" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 9. "dx4_wuevnt,Pad DX Wakeup Event" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "dx4_wuen,Pad DX Wakeup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "dx4_wuclkin,Pad DX Wakeup Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "dx4_wuin,Pad DX Wakeup Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "dx4_isoclkin,Pad DX Isolation Clkin" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "dx4_isoin,Pad DX Isosaltion Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "dx4_ie,Pad DX Input Buffer Enable" "0,1"
|
|
newline
|
|
rbitfld.long 0x10 2. "dx4_in,Pad DX Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "dx4_enbpd,Pad DX Enable Pull Down" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "dx4_enbpu,Pad DX Enable Pull Up" "0,1"
|
|
line.long 0x14 "RSS_CSI2A_FIFO_MEMINIT,"
|
|
bitfld.long 0x14 0. "start,Start Memory intialization of memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed." "0,1"
|
|
line.long 0x18 "RSS_CSI2A_FIFO_MEMINIT_DONE,"
|
|
bitfld.long 0x18 0. "done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "RSS_CSI2A_FIFO_MEMINIT_STATUS,"
|
|
bitfld.long 0x0 0. "status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
|
|
group.long 0x84++0x7
|
|
line.long 0x0 "RSS_CSI2A_CTX_MEMINIT,"
|
|
bitfld.long 0x0 0. "start,Start Memory intialization of memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed." "0,1"
|
|
line.long 0x4 "RSS_CSI2A_CTX_MEMINIT_DONE,"
|
|
bitfld.long 0x4 0. "done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "RSS_CSI2A_CTX_MEMINIT_STATUS,"
|
|
bitfld.long 0x0 0. "status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "RSS_BUS_SAFETY_CTRL,"
|
|
bitfld.long 0x0 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "RSS_BUS_SAFETY_SEC_ERR_STAT0,"
|
|
bitfld.long 0x0 15. "RSS2MSS,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MSS2RSS,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DSS2RSS,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RSS2DSS,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BSS_SLV,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RCSS_MBOX,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STATIC_MEM,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CQ_MEM_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CQ_MEM_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ADC_BUF_WRD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ADC_BUF_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RCSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RCSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RCSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BSS_MST,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RCSS_CSI2A_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
group.long 0x98++0x7
|
|
line.long 0x0 "RSS_TPTCA0_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_TPTCA0_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xA0++0xF
|
|
line.long 0x0 "RSS_TPTCA0_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "RSS_TPTCA0_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_TPTCA0_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xB8++0x13
|
|
line.long 0x0 "RSS_TPTCA0_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "RSS_CSI2A_MDMA_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_CSI2A_MDMA_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xD4++0x17
|
|
line.long 0x0 "RSS_CSI2A_MDMA_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "RSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0xEC++0x7
|
|
line.long 0x0 "RSS_PCR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_PCR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0xF4++0x17
|
|
line.long 0x0 "RSS_PCR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "RSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x10C++0x7
|
|
line.long 0x0 "RSS_ADCBUF_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_ADCBUF_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x114++0xF
|
|
line.long 0x0 "RSS_ADCBUF_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_ADCBUF_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_ADCBUF_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_ADCBUF_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x124++0x7
|
|
line.long 0x0 "RSS_ADCBUF_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_ADCBUF_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x12C++0x13
|
|
line.long 0x0 "RSS_ADCBUF_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_ADCBUF_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_ADCBUF_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_ADCBUF_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_ADCBUF_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x140++0x7
|
|
line.long 0x0 "RSS_CQ_MEM_RD_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_CQ_MEM_RD_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x148++0xF
|
|
line.long 0x0 "RSS_CQ_MEM_RD_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_CQ_MEM_RD_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_CQ_MEM_RD_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_CQ_MEM_RD_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x158++0x7
|
|
line.long 0x0 "RSS_CQ_MEM_WR_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_CQ_MEM_WR_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x160++0x13
|
|
line.long 0x0 "RSS_CQ_MEM_WR_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_CQ_MEM_WR_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_CQ_MEM_WR_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_CQ_MEM_WR_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_CQ_MEM_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x1F4++0x7
|
|
line.long 0x0 "RSS_MBOX_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_MBOX_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x1FC++0x17
|
|
line.long 0x0 "RSS_MBOX_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "RSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x214++0x7
|
|
line.long 0x0 "RSS_STATIC_MEM_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_STATIC_MEM_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x21C++0x17
|
|
line.long 0x0 "RSS_STATIC_MEM_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_STATIC_MEM_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_STATIC_MEM_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_STATIC_MEM_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_STATIC_MEM_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "RSS_STATIC_MEM_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x234++0x7
|
|
line.long 0x0 "RSS_BSS_MST_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_BSS_MST_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x23C++0x17
|
|
line.long 0x0 "RSS_BSS_MST_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_BSS_MST_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_BSS_MST_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_BSS_MST_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_BSS_MST_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "RSS_BSS_MST_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x254++0x7
|
|
line.long 0x0 "RSS_BSS_SLV_BUS_SAFETY_CTRL,"
|
|
hexmask.long.byte 0x0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RSS_BSS_SLV_BUS_SAFETY_FI,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
bitfld.long 0x4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
|
|
rgroup.long 0x25C++0x17
|
|
line.long 0x0 "RSS_BSS_SLV_BUS_SAFETY_ERR,"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x4 "RSS_BSS_SLV_BUS_SAFETY_ERR_STAT_DATA0,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x8 "RSS_BSS_SLV_BUS_SAFETY_ERR_STAT_CMD,"
|
|
hexmask.long 0x8 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0xC "RSS_BSS_SLV_BUS_SAFETY_ERR_STAT_WRITE,"
|
|
hexmask.long 0xC 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x10 "RSS_BSS_SLV_BUS_SAFETY_ERR_STAT_READ,"
|
|
hexmask.long 0x10 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
line.long 0x14 "RSS_BSS_SLV_BUS_SAFETY_ERR_STAT_WRITERESP,"
|
|
hexmask.long 0x14 0.--31. 1. "stat,Refer to TPR12 Substem Microarch document for more details"
|
|
group.long 0x274++0x13
|
|
line.long 0x0 "RSS_TPTC_BOUNDARY_CFG,"
|
|
hexmask.long.byte 0x0 0.--5. 1. "tptc_a0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance"
|
|
line.long 0x4 "RSS_TPTC_XID_REORDER_CFG,"
|
|
bitfld.long 0x4 0. "tptc_a0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB" "0,1"
|
|
line.long 0x8 "DBG_ACK_CPU_CTRL,"
|
|
bitfld.long 0x8 0.--2. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals 0:MSS CR5 1:DSP 2:DSS CM4 3-7:RSS CR4" "0: MSS CR5 1:DSP 2:DSS CM4 3-7:RSS CR4,?,?,?,?,?,?,?"
|
|
line.long 0xC "RSS_ADCBUF_PING_MEMINIT,"
|
|
bitfld.long 0xC 0. "start,Start Memory intialization of memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed." "0,1"
|
|
line.long 0x10 "RSS_ADCBUF_PING_MEMINIT_DONE,"
|
|
bitfld.long 0x10 0. "done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
|
|
rgroup.long 0x288++0x3
|
|
line.long 0x0 "RSS_ADCBUF_PING_MEMINIT_STATUS,"
|
|
bitfld.long 0x0 0. "status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
|
|
group.long 0x28C++0x7
|
|
line.long 0x0 "RSS_ADCBUF_PONG_MEMINIT,"
|
|
bitfld.long 0x0 0. "start,Start Memory intialization of memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed." "0,1"
|
|
line.long 0x4 "RSS_ADCBUF_PONG_MEMINIT_DONE,"
|
|
bitfld.long 0x4 0. "done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
|
|
rgroup.long 0x294++0x3
|
|
line.long 0x0 "RSS_ADCBUF_PONG_MEMINIT_STATUS,"
|
|
bitfld.long 0x0 0. "status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
|
|
group.long 0x2C8++0x13
|
|
line.long 0x0 "SOC_TO_BSS_SW_INT,"
|
|
hexmask.long.byte 0x0 0.--7. 1. "trig,Write Pulse Bit field writing to each bit field <0-7>: 1'b1:triggers BSS_SW_INT_RSS_CTRL<0-7> to BSS"
|
|
line.long 0x4 "RSS_DBG_ACK_CTL0,"
|
|
bitfld.long 0x4 0.--2. "frc,emulation suspend signal control . Writing '111' would ungate the emulation suspend signal to the FRC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "DMMSWINT1,"
|
|
bitfld.long 0x8 22. "DMMCQWREN,CQ Write Enable from DMM. 0 --> Write to CQ memory will happen from DFE and Ping-pong select will come from HW FSM (same as ADC Buffer ping-pong select). 1 --> Write to CQ memory will happen from CQ_W slave port in DSS interconnect using DMM as.." "0: Write to CQ memory will happen from DFE and..,1: Write to CQ memory will happen from CQ_W slave.."
|
|
newline
|
|
bitfld.long 0x8 21. "DMMCQPINPONSEL,CQ Ping Pong select for HIL Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "DMMCPWREN,Writiing 1'b1: Enables DMM writes in to CP read registers 1'b0: Disables DMM writes to CP read registers" "?,1: Enables DMM writes in to CP read registers 1'b0:.."
|
|
newline
|
|
bitfld.long 0x8 17. "DMMADCBUFWREN,ADC Buffer Write Enable from DMM. 0 --> Write to ADC BUF memory will happen from DFE and Ping-pong select will come from HW FSM (same as ADC Buffer ping-pong select). 1 --> Write to CQ memory will happen from ADCBUF_W slave port in DSS.." "0: Write to ADC BUF memory will happen from DFE and..,1: Write to CQ memory will happen from ADCBUF_W.."
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bitfld.long 0x8 16. "DMMADCBUFPINPONSEL,ADC Buffer Ping Pong select for HIL Mode" "0,1"
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line.long 0xC "RSS_SHARED_MEM_MEMINIT,"
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bitfld.long 0xC 0. "start,Start Memory intialization of memory. Write 0x1 to start memory initilization. Write 0x0 after ensuring Memory intilization is in progress or has completed." "0,1"
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line.long 0x10 "RSS_SHARED_MEM_MEMINIT_DONE,"
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bitfld.long 0x10 0. "done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
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rgroup.long 0x2DC++0x3
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line.long 0x0 "RSS_SHARED_MEM_MEMINIT_STATUS,"
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bitfld.long 0x0 0. "status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
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group.long 0x2E0++0x3
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line.long 0x0 "RSS_CSI_ACCESS_MODE,"
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bitfld.long 0x0 0. "csi2a_sel,writing 1'b0 : ensures all the accesses from CSI2A are user-mode writing 1'b1 : ensures all the accesses from CSI2A are privilege mode" "0: ensures all the accesses from CSI2A are..,?"
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group.long 0x400++0xB
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line.long 0x0 "BSS_CONTROL,"
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bitfld.long 0x0 28.--30. "dss_l3_access,writing 3'b111 allocates DSS_L3_BANKD 256KB as TCM for RSS_CR4" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. "halt,writing 3'b000 unhalts BSS. This is expected to be writen only once per processor reset cycle." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 16.--18. "wfi_override,writing 3'b111 overrides the WFI signal from CR4 and asserts it." "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--11. 1. "bootmode,writing 12'h000 : selects the normal boot mode for CR4. 12'h111 : selects the FW dev mode for CR4 12'h222 : selects the orbit mode for CR4 12'h333 : selects the 14xx ROM swap mode"
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line.long 0x4 "BSS_TCM_MEMINIT,"
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bitfld.long 0x4 0. "mem0_init,Start Memory intialization of memory. Write 0x1 to start memory initilization." "0,1"
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line.long 0x8 "BSS_TCM_MEMINIT_DONE,"
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bitfld.long 0x8 0. "mem0_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
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rgroup.long 0x40C++0x3
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line.long 0x0 "BSS_TCM_MEMINIT_STATUS,"
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bitfld.long 0x0 0. "mem0_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
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group.long 0x410++0x7
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line.long 0x0 "BSS_VIM_MEMINIT,"
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bitfld.long 0x0 0. "mem0_init,Start Memory intialization of memory. Write 0x1 to start memory initilization." "0,1"
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line.long 0x4 "BSS_VIM_MEMINIT_DONE,"
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bitfld.long 0x4 0. "mem0_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
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rgroup.long 0x418++0x3
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line.long 0x0 "BSS_VIM_MEMINIT_STATUS,"
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bitfld.long 0x0 0. "mem0_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
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group.long 0x41C++0x7
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line.long 0x0 "BSS_DFE_MEMINIT,"
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bitfld.long 0x0 0. "mem0_init,Start Memory intialization of memory. Write 0x1 to start memory initilization." "0,1"
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line.long 0x4 "BSS_DFE_MEMINIT_DONE,"
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bitfld.long 0x4 0. "mem0_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
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rgroup.long 0x424++0x3
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line.long 0x0 "BSS_DFE_MEMINIT_STATUS,"
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bitfld.long 0x0 0. "mem0_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
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group.long 0x428++0x7
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line.long 0x0 "BSS_RAMPGEN_MEMINIT,"
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bitfld.long 0x0 0. "mem0_init,Start Memory intialization of memory. Write 0x1 to start memory initilization." "0,1"
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line.long 0x4 "BSS_RAMPGEN_MEMINIT_DONE,"
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bitfld.long 0x4 0. "mem0_done,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is complte. Write 0x1 to clear status." "0,1"
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rgroup.long 0x430++0x3
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line.long 0x0 "BSS_RAMPGEN_MEMINIT_STATUS,"
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bitfld.long 0x0 0. "mem0_status,Status field. Read value 0x1 indicates previously triggered Memory intialization of memory is in progress." "0,1"
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group.long 0x434++0x3
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line.long 0x0 "BSS_DSS_L3_STICKY,"
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bitfld.long 0x0 0.--2. "sticky_enable,writing 3'b111 make the BSS_CONTROL::DSS_L3_ACCESS_ENABLE sticky. Further writes to DSS_L3_ACCESS_ENABLE wont impact the register" "0,1,2,3,4,5,6,7"
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rgroup.long 0x438++0x3
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line.long 0x0 "BSS_DSS_L3_ACCESS,"
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bitfld.long 0x0 0. "status,reading 1'b0: DSS_L3_BANKD1 is not allocated to BSS_TCMA 1'b1: DSS_L3_BANKD1 is allocated to BSS_TCMA" "0: DSS_L3_BANKD1 is not allocated to BSS_TCMA 1'b1:..,?"
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group.long 0x800++0x3F
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line.long 0x0 "TESTPATTERNRX1ICFG,"
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hexmask.long.word 0x0 16.--31. 1. "TSTPATRX1IINCR,Value to be added for each successive sample for the test pattern data in I channel Rx channel 0. In this register the naming convention for the 4 Rx channel indices are from 1 to 4 instead of 0 to 3."
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hexmask.long.word 0x0 0.--15. 1. "TSTPATRX1IOFFSET,Offset value to be used for the first sample for the test pattern data in I channel Rx channel 0. In this register the naming convention for the 4 Rx channel indices are from 1 to 4 instead of 0 to 3."
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line.long 0x4 "TESTPATTERNRX2ICFG,"
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hexmask.long.word 0x4 16.--31. 1. "TSTPATRX2IINCR,Value to be added for each successive sample for the test pattern data in I channel Rx channel 1."
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hexmask.long.word 0x4 0.--15. 1. "TSTPATRX2IOFFSET,Offset value to be used for the first sample for the test pattern data in I channel Rx channel 1."
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line.long 0x8 "TESTPATTERNRX3ICFG,"
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hexmask.long.word 0x8 16.--31. 1. "TSTPATRX3IINCR,Value to be added for each successive sample for the test pattern data in I channel Rx channel 2"
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newline
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hexmask.long.word 0x8 0.--15. 1. "TSTPATRX3IOFFSET,Offset value to be used for the first sample for the test pattern data in I channel Rx channel 2"
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line.long 0xC "TESTPATTERNRX4ICFG,"
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hexmask.long.word 0xC 16.--31. 1. "TSTPATRX4IINCR,Value to be added for each successive sample for the test pattern data in I channel Rx channel 3"
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hexmask.long.word 0xC 0.--15. 1. "TSTPATRX4IOFFSET,Offset value to be used for the first sample for the test pattern data in I channel Rx channel 3"
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line.long 0x10 "TESTPATTERNRX1QCFG,"
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hexmask.long.word 0x10 16.--31. 1. "TSTPATRX1QINCR,Value to be added for each successive sample for the test pattern data in Q channel Rx channel 0. In this register the naming convention for the 4 Rx channel indices are from 1 to 4 instead of 0 to 3."
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hexmask.long.word 0x10 0.--15. 1. "TSTPATRX1QOFFSET,Offset value to be used for the first sample for the test pattern data in Q channel Rx channel 0. In this register the naming convention for the 4 Rx channel indices are from 1 to 4 instead of 0 to 3."
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line.long 0x14 "TESTPATTERNRX2QCFG,"
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hexmask.long.word 0x14 16.--31. 1. "TSTPATRX2QINCR,Value to be added for each successive sample for the test pattern data in Q channel Rx channel 1."
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newline
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hexmask.long.word 0x14 0.--15. 1. "TSTPATRX2QOFFSET,Offset value to be used for the first sample for the test pattern data in Q channel Rx channel 1."
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line.long 0x18 "TESTPATTERNRX3QCFG,"
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hexmask.long.word 0x18 16.--31. 1. "TSTPATRX3QINCR,Value to be added for each successive sample for the test pattern data in Q channel Rx channel 2"
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newline
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hexmask.long.word 0x18 0.--15. 1. "TSTPATRX3QOFFSET,Offset value to be used for the first sample for the test pattern data in Q channel Rx channel 2"
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line.long 0x1C "TESTPATTERNRX4QCFG,"
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hexmask.long.word 0x1C 16.--31. 1. "TSTPATRX4QINCR,Value to be added for each successive sample for the test pattern data in Q channel Rx channel 3"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "TSTPATRX4QOFFSET,Offset value to be used for the first sample for the test pattern data in Q channel Rx channel 3"
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line.long 0x20 "TESTPATTERNVLDCFG,"
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bitfld.long 0x20 8.--10. "TSTPATGENEN,Enable for test pattern generator. This is used to Mux with the functional data from BSS. 000 -->Disable 111-->Enable Others are reserved." "0: Disable,?,?,?,?,?,?,?"
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hexmask.long.byte 0x20 0.--7. 1. "TSTPATVLDCNT,Number of DSS Interconnect clocks (200 MHz) between successive samples for the test pattern gen."
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line.long 0x24 "ADCBUFCFG1,"
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rbitfld.long 0x24 16. "ADCBUFPIPOSEL,TI Internal Feature Ping-pong select value from ADC Buffer Packing logic. Even in SW override mode this register will indicate the ping-pong select signal generated from the ADC Buffer Packing logic and not the override value." "0,1"
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bitfld.long 0x24 15. "ADCBUFCONTSTOPPL,Stop Pulse for Continuous mode. The data capture will stop once this register is set. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type write to this field will generate a pulse" "0,1"
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newline
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bitfld.long 0x24 14. "ADCBUFCONTSTRTPL,Start Pulse for Continuous mode. The data capture will start from Address 0 once this register is set. All the other configurations like Enable Sample Count are expected to be programmed before this pulse. Continous mode is expected to.." "0,1"
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bitfld.long 0x24 13. "ADCBUFCONTMODEEN,Continuous mode enable for ADC Buffer. This is set when a fixed number of samples have to be stored in Ping/Pong and not depend on Chirp time-lines (Eg: Analog Lab characterization to stream out continuous data from DFE). Continous mode.." "0,1"
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bitfld.long 0x24 12. "ADCBUFWRITEMODE,This needs to be programmed to 0x1 in AR16xx 0 --> Interleaved 1 --> Non-interleaved" "0: Interleaved,1: Non-interleaved"
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newline
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bitfld.long 0x24 11. "ADCBUFPIPOOVRVAL,TI Internal Feature SW override value for ADC Buffer Ping Pong select" "0,1"
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newline
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bitfld.long 0x24 10. "ADCBUFPIPOOVRCNT,TI Internal Feature Override control for ADC Buffer Ping Pong select" "0,1"
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newline
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bitfld.long 0x24 9. "RX3EN,Enable for Rx3 write" "0,1"
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newline
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bitfld.long 0x24 8. "RX2EN,Enable for Rx2 write" "0,1"
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newline
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bitfld.long 0x24 7. "RX1EN,Enable for Rx1 write" "0,1"
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newline
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bitfld.long 0x24 6. "RX0EN,Enable for Rx0 write" "0,1"
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newline
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bitfld.long 0x24 5. "ADCBUFIQSWAP,0 --> I is stored in LSB and Q is stored in MSB 1 --> Q is stored in LSB and I is stored in MSB" "0: I is stored in LSB and Q is stored in MSB 1,?"
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bitfld.long 0x24 4. "ADCBUFRL2CHINTRL,TI reserved field. Do not touch" "0,1"
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newline
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bitfld.long 0x24 3. "ADCBUFRLMODECHSEL,TI Internal Feature 0 -->I channel 1 --> Q channel" "0: I channel,1: Q channel"
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newline
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bitfld.long 0x24 2. "ADCBUFREALONLYMODE,0-->Complex Data mode 1-->Real data mode" "0: Complex Data mode,1: Real data mode"
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newline
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bitfld.long 0x24 1. "ADCBUFPIPOSELINV,TI Internal Feature Inversion control for ADC Buffer Ping-pong select. By default ADC Buffer write starts with Pong write. By setting this bit to 1 it will start from Ping write after reset." "0,1"
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newline
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bitfld.long 0x24 0. "ADCBUFWRSOURCE,TI Internal Feature Write source for ADC Buffer. 0 --> DFE 1 --> VIN" "0: DFE,1: VIN"
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line.long 0x28 "ADCBUFCFG1_EXTD,"
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hexmask.long 0x28 0.--31. 1. "ADCBUFINTGENDLY,TI Intenal Feature. No of clocks to delay the ping-pong switch and interrupt generation w.r.t ADC Valid fall pulse. This will enable dithering the DSP activity for successive ping-pong switch cycles. This will not delay the ping pong.."
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line.long 0x2C "ADCBUFCFG2,"
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hexmask.long.word 0x2C 16.--26. 1. "ADCBUFADDRX1,128 bit Address offset to be added to the internal address pointer for Rx1 writes in Non-interleaved mode."
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newline
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hexmask.long.word 0x2C 0.--10. 1. "ADCBUFADDRX0,128 bit Address offset to be added to the internal address pointer for Rx0 writes in Non-interleaved mode."
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line.long 0x30 "ADCBUFCFG3,"
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hexmask.long.word 0x30 16.--26. 1. "ADCBUFADDRX3,128 bit Address offset to be added to the internal address pointer for Rx3 writes in Non-interleaved mode."
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newline
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hexmask.long.word 0x30 0.--10. 1. "ADCBUFADDRX2,128 bit Address offset to be added to the internal address pointer for Rx2 writes in Non-interleaved mode."
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line.long 0x34 "ADCBUFCFG4,"
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bitfld.long 0x34 30. "ADCBUFPNGSELTGLDIS,TI Internal Feature 0 --> Delay Interrupt Gen and Ping/Pong toggle together based on cfg_interrupt_gen_delay 1 --> Delay only Interrupt Gen based on cfg_interrupt_gen_delay. But toggle Ping/Pong select signal as soon as the write is.." "0: Delay Interrupt Gen and Ping/Pong toggle..,1: Delay only Interrupt Gen based on.."
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newline
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hexmask.long.byte 0x34 21.--25. 1. "ADCBUFNUMCHRPPONG,Number of chirps to be stored in Pong buffer. This register should be programmed with one less than the actual number needed. This is used when data is written to Pong Memory. The value written to this field should be the same as that.."
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newline
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hexmask.long.byte 0x34 16.--20. 1. "ADCBUFNUMCHRPPING,Number of chirps to be stored in Ping buffer. This register should be programmed with one less than the actual number needed. This is used when data is written to Pong Memory. The value written to this field should be the same as that.."
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newline
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hexmask.long.word 0x34 0.--15. 1. "ADCBUFSAMPCNT,No of samples to store in each Ping and Pong register in continuous mode of ADC Buffer. In real only mode this refers to the number of real samples and in complex mode this refers to number of complex samples. This refers to the number of.."
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line.long 0x38 "ADCBUFINTGENDITHERDLY,"
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hexmask.long 0x38 0.--31. 1. "ADCBUFINTGENDITHERDLY,TI Internal Feature. Additional dithering delay added on the Chirp Avilable interrupt"
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line.long 0x3C "CBUFF_FRAME_START_SEL,"
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bitfld.long 0x3C 0. "sel,writing: 1'b0: selects frame_start from DFE 1'b1: Selects frame_start from chirp_avail (adc capture complete)" "0: selects frame_start from DFE 1'b1: Selects..,?"
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group.long 0xC00++0x7
|
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line.long 0x0 "CQCFG1,"
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hexmask.long.word 0x0 22.--30. 1. "CQ2BASEADDR,128-bit Address offset which inidcates the start address for storing CQ0 (ADC/RxIF Saturation Detection) from the start of CQ memory. This is not the byte address offset but 128 bit address offset"
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hexmask.long.word 0x0 13.--21. 1. "CQ1BASEADDR,128-bit Address offset which inidcates the start address for storing CQ0 (Signal Image Band Energy detection) from the start of CQ memory. This is not the byte address offset but 128 bit address offset"
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newline
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hexmask.long.word 0x0 4.--12. 1. "CQ0BASEADDR,128-bit Address offset which inidcates the start address for storing CQ0 (Wide Band Energy detection) from the start of CQ memory. This is not the byte address offset but 128 bit address offset"
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newline
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bitfld.long 0x0 3. "CQ96BITPACKEN,This is used to pack the CQ data into only the LSB 96 bits of each row of the CQ memory. This can be used in 3 channel mode of LVDS where the ADC data and Chirp Params occupy only LSB 96 bits of each memory row." "0,1"
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newline
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bitfld.long 0x0 0.--1. "CQDATAWIDTH,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory. 00 01->Raw 16 10-->Raw 12 11-->Raw14" "?,1: Raw 16,?,?"
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line.long 0x4 "CQCFG2,"
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bitfld.long 0x4 17. "CQ_CLK_GATE,writing: 1'b0: ungates the clk to CQ logic 1'b1: Gates the clk to CQ logic" "0: ungates the clk to CQ logic 1'b1: Gates the clk..,?"
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newline
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bitfld.long 0x4 16. "CQPIPOSELVAL,Ping pong select override value for CQ Memory. 1 --> Read access from Chirp Info Slave of DSS Interconnect will be routed to ping memory and write access from CQ_W/DFE write will be routed to pong memory. 0 --> Read access from Chirp Info.." "0: Read access from Chirp Info Slave of DSS..,1: Read access from Chirp Info Slave of DSS.."
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newline
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bitfld.long 0x4 12. "CQPIPOSELCNT,Ping pong select override control for CQ Memory. 0 --> Ping-pong select comes from HW FSM (same as the ping-pong select for ADC Buffer)/DMMCQPINPONSEL 1 --> Ping pong select for CQ memory is taken from SW register (CQPIPOSELVAL)" "0: Ping-pong select comes from HW FSM,1: Ping pong select for CQ memory is taken from SW.."
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newline
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bitfld.long 0x4 8. "CQ2TESTMODEEN,TI Internal Feaure Test Mode enable for CQ2 (ADC/RxIF Saturation). Once enabled each 8 bit data is same as Addr+1." "0,1"
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newline
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bitfld.long 0x4 4. "CQ1TESTMODEEN,TI Internal Feaure Test Mode enable for CQ1 (SI). Once enabled each 16 bit data is same as [2*Addr+1 for the MSB 8 bits and Addr+1 for the LSB 8 bits." "0,1"
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newline
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bitfld.long 0x4 0. "CQ0TESTMODEEN,TI Internal Feaure Test Mode enable for CQ0 (WBE). Once enabled each 16 bit data is same as [2*Addr+1 for the MSB 8 bits and Addr+1 for the LSB 8 bits." "0,1"
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rgroup.long 0xC08++0x23F
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line.long 0x0 "CPREG0,"
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hexmask.long 0x0 0.--31. 1. "CPREG0,Chirp Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x4 "CPREG1,"
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hexmask.long 0x4 0.--31. 1. "CPREG1,Chirp Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
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line.long 0x8 "CPREG2,"
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hexmask.long 0x8 0.--31. 1. "CPREG2,Chirp Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0xC "CPREG3,"
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hexmask.long 0xC 0.--31. 1. "CPREG3,Chirp Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x10 "CPREG4,"
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hexmask.long 0x10 0.--31. 1. "CPREG4,Chirp Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x14 "CPREG5,"
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hexmask.long 0x14 0.--31. 1. "CPREG5,Chirp Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x18 "CPREG6,"
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hexmask.long 0x18 0.--31. 1. "CPREG6,Chirp Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x1C "CPREG7,"
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hexmask.long 0x1C 0.--31. 1. "CPREG7,Chirp Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x20 "CPREG8,"
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hexmask.long 0x20 0.--31. 1. "CPREG8,Chirp Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x24 "CPREG9,"
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hexmask.long 0x24 0.--31. 1. "CPREG9,Chirp Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x28 "CPREG10,"
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hexmask.long 0x28 0.--31. 1. "CPREG10,Chirp Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x2C "CPREG11,"
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|
hexmask.long 0x2C 0.--31. 1. "CPREG11,Chirp Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x30 "CPREG12,"
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|
hexmask.long 0x30 0.--31. 1. "CPREG12,Chirp Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x34 "CPREG13,"
|
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hexmask.long 0x34 0.--31. 1. "CPREG13,Chirp Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
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line.long 0x38 "CPREG14,"
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hexmask.long 0x38 0.--31. 1. "CPREG14,Chirp Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x3C "CPREG15,"
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hexmask.long 0x3C 0.--31. 1. "CPREG15,Chirp Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x40 "CH0CPREG0,"
|
|
hexmask.long 0x40 0.--31. 1. "CH0CPREG0,Multi Chirp 0 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x44 "CH0CPREG1,"
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hexmask.long 0x44 0.--31. 1. "CH0CPREG1,Multi Chirp 0 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x48 "CH0CPREG2,"
|
|
hexmask.long 0x48 0.--31. 1. "CH0CPREG2,Multi Chirp 0 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x4C "CH0CPREG3,"
|
|
hexmask.long 0x4C 0.--31. 1. "CH0CPREG3,Multi Chirp 0 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x50 "CH0CPREG4,"
|
|
hexmask.long 0x50 0.--31. 1. "CH0CPREG4,Multi Chirp 0 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x54 "CH0CPREG5,"
|
|
hexmask.long 0x54 0.--31. 1. "CH0CPREG5,Multi Chirp 0 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x58 "CH0CPREG6,"
|
|
hexmask.long 0x58 0.--31. 1. "CH0CPREG6,Multi Chirp 0 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x5C "CH0CPREG7,"
|
|
hexmask.long 0x5C 0.--31. 1. "CH0CPREG7,Multi Chirp 0 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x60 "CH0CPREG8,"
|
|
hexmask.long 0x60 0.--31. 1. "CH0CPREG8,Multi Chirp 0 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x64 "CH0CPREG9,"
|
|
hexmask.long 0x64 0.--31. 1. "CH0CPREG9,Multi Chirp 0 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x68 "CH0CPREG10,"
|
|
hexmask.long 0x68 0.--31. 1. "CH0CPREG10,Multi Chirp 0 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x6C "CH0CPREG11,"
|
|
hexmask.long 0x6C 0.--31. 1. "CH0CPREG11,Multi Chirp 0 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x70 "CH0CPREG12,"
|
|
hexmask.long 0x70 0.--31. 1. "CH0CPREG12,Multi Chirp 0 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x74 "CH0CPREG13,"
|
|
hexmask.long 0x74 0.--31. 1. "CH0CPREG13,Multi Chirp 0 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x78 "CH0CPREG14,"
|
|
hexmask.long 0x78 0.--31. 1. "CH0CPREG14,Multi Chirp 0 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x7C "CH0CPREG15,"
|
|
hexmask.long 0x7C 0.--31. 1. "CH0CPREG15,Multi Chirp 0 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x80 "CH1CPREG0,"
|
|
hexmask.long 0x80 0.--31. 1. "CH1CPREG0,Multi Chirp 1 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x84 "CH1CPREG1,"
|
|
hexmask.long 0x84 0.--31. 1. "CH1CPREG1,Multi Chirp 1 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x88 "CH1CPREG2,"
|
|
hexmask.long 0x88 0.--31. 1. "CH1CPREG2,Multi Chirp 1 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x8C "CH1CPREG3,"
|
|
hexmask.long 0x8C 0.--31. 1. "CH1CPREG3,Multi Chirp 1 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x90 "CH1CPREG4,"
|
|
hexmask.long 0x90 0.--31. 1. "CH1CPREG4,Multi Chirp 1 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x94 "CH1CPREG5,"
|
|
hexmask.long 0x94 0.--31. 1. "CH1CPREG5,Multi Chirp 1 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x98 "CH1CPREG6,"
|
|
hexmask.long 0x98 0.--31. 1. "CH1CPREG6,Multi Chirp 1 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x9C "CH1CPREG7,"
|
|
hexmask.long 0x9C 0.--31. 1. "CH1CPREG7,Multi Chirp 1 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xA0 "CH1CPREG8,"
|
|
hexmask.long 0xA0 0.--31. 1. "CH1CPREG8,Multi Chirp 1 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xA4 "CH1CPREG9,"
|
|
hexmask.long 0xA4 0.--31. 1. "CH1CPREG9,Multi Chirp 1 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xA8 "CH1CPREG10,"
|
|
hexmask.long 0xA8 0.--31. 1. "CH1CPREG10,Multi Chirp 1 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xAC "CH1CPREG11,"
|
|
hexmask.long 0xAC 0.--31. 1. "CH1CPREG11,Multi Chirp 1 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xB0 "CH1CPREG12,"
|
|
hexmask.long 0xB0 0.--31. 1. "CH1CPREG12,Multi Chirp 1 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xB4 "CH1CPREG13,"
|
|
hexmask.long 0xB4 0.--31. 1. "CH1CPREG13,Multi Chirp 1 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xB8 "CH1CPREG14,"
|
|
hexmask.long 0xB8 0.--31. 1. "CH1CPREG14,Multi Chirp 1 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xBC "CH1CPREG15,"
|
|
hexmask.long 0xBC 0.--31. 1. "CH1CPREG15,Multi Chirp 1 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xC0 "CH2CPREG0,"
|
|
hexmask.long 0xC0 0.--31. 1. "CH2CPREG0,Multi Chirp 2 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xC4 "CH2CPREG1,"
|
|
hexmask.long 0xC4 0.--31. 1. "CH2CPREG1,Multi Chirp 2 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xC8 "CH2CPREG2,"
|
|
hexmask.long 0xC8 0.--31. 1. "CH2CPREG2,Multi Chirp 2 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xCC "CH2CPREG3,"
|
|
hexmask.long 0xCC 0.--31. 1. "CH2CPREG3,Multi Chirp 2 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xD0 "CH2CPREG4,"
|
|
hexmask.long 0xD0 0.--31. 1. "CH2CPREG4,Multi Chirp 2 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xD4 "CH2CPREG5,"
|
|
hexmask.long 0xD4 0.--31. 1. "CH2CPREG5,Multi Chirp 2 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xD8 "CH2CPREG6,"
|
|
hexmask.long 0xD8 0.--31. 1. "CH2CPREG6,Multi Chirp 2 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xDC "CH2CPREG7,"
|
|
hexmask.long 0xDC 0.--31. 1. "CH2CPREG7,Multi Chirp 2 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xE0 "CH2CPREG8,"
|
|
hexmask.long 0xE0 0.--31. 1. "CH2CPREG8,Multi Chirp 2 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xE4 "CH2CPREG9,"
|
|
hexmask.long 0xE4 0.--31. 1. "CH2CPREG9,Multi Chirp 2 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xE8 "CH2CPREG10,"
|
|
hexmask.long 0xE8 0.--31. 1. "CH2CPREG10,Multi Chirp 2 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xEC "CH2CPREG11,"
|
|
hexmask.long 0xEC 0.--31. 1. "CH2CPREG11,Multi Chirp 2 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xF0 "CH2CPREG12,"
|
|
hexmask.long 0xF0 0.--31. 1. "CH2CPREG12,Multi Chirp 2 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xF4 "CH2CPREG13,"
|
|
hexmask.long 0xF4 0.--31. 1. "CH2CPREG13,Multi Chirp 2 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xF8 "CH2CPREG14,"
|
|
hexmask.long 0xF8 0.--31. 1. "CH2CPREG14,Multi Chirp 2 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0xFC "CH2CPREG15,"
|
|
hexmask.long 0xFC 0.--31. 1. "CH2CPREG15,Multi Chirp 2 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x100 "CH3CPREG0,"
|
|
hexmask.long 0x100 0.--31. 1. "CH3CPREG0,Multi Chirp 3 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x104 "CH3CPREG1,"
|
|
hexmask.long 0x104 0.--31. 1. "CH3CPREG1,Multi Chirp 3 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x108 "CH3CPREG2,"
|
|
hexmask.long 0x108 0.--31. 1. "CH3CPREG2,Multi Chirp 3 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x10C "CH3CPREG3,"
|
|
hexmask.long 0x10C 0.--31. 1. "CH3CPREG3,Multi Chirp 3 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x110 "CH3CPREG4,"
|
|
hexmask.long 0x110 0.--31. 1. "CH3CPREG4,Multi Chirp 3 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x114 "CH3CPREG5,"
|
|
hexmask.long 0x114 0.--31. 1. "CH3CPREG5,Multi Chirp 3 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x118 "CH3CPREG6,"
|
|
hexmask.long 0x118 0.--31. 1. "CH3CPREG6,Multi Chirp 3 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x11C "CH3CPREG7,"
|
|
hexmask.long 0x11C 0.--31. 1. "CH3CPREG7,Multi Chirp 3 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x120 "CH3CPREG8,"
|
|
hexmask.long 0x120 0.--31. 1. "CH3CPREG8,Multi Chirp 3 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x124 "CH3CPREG9,"
|
|
hexmask.long 0x124 0.--31. 1. "CH3CPREG9,Multi Chirp 3 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x128 "CH3CPREG10,"
|
|
hexmask.long 0x128 0.--31. 1. "CH3CPREG10,Multi Chirp 3 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x12C "CH3CPREG11,"
|
|
hexmask.long 0x12C 0.--31. 1. "CH3CPREG11,Multi Chirp 3 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x130 "CH3CPREG12,"
|
|
hexmask.long 0x130 0.--31. 1. "CH3CPREG12,Multi Chirp 3 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x134 "CH3CPREG13,"
|
|
hexmask.long 0x134 0.--31. 1. "CH3CPREG13,Multi Chirp 3 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x138 "CH3CPREG14,"
|
|
hexmask.long 0x138 0.--31. 1. "CH3CPREG14,Multi Chirp 3 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x13C "CH3CPREG15,"
|
|
hexmask.long 0x13C 0.--31. 1. "CH3CPREG15,Multi Chirp 3 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x140 "CH4CPREG0,"
|
|
hexmask.long 0x140 0.--31. 1. "CH4CPREG0,Multi Chirp 4 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x144 "CH4CPREG1,"
|
|
hexmask.long 0x144 0.--31. 1. "CH4CPREG1,Multi Chirp 4 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x148 "CH4CPREG2,"
|
|
hexmask.long 0x148 0.--31. 1. "CH4CPREG2,Multi Chirp 4 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x14C "CH4CPREG3,"
|
|
hexmask.long 0x14C 0.--31. 1. "CH4CPREG3,Multi Chirp 4 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x150 "CH4CPREG4,"
|
|
hexmask.long 0x150 0.--31. 1. "CH4CPREG4,Multi Chirp 4 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x154 "CH4CPREG5,"
|
|
hexmask.long 0x154 0.--31. 1. "CH4CPREG5,Multi Chirp 4 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x158 "CH4CPREG6,"
|
|
hexmask.long 0x158 0.--31. 1. "CH4CPREG6,Multi Chirp 4 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x15C "CH4CPREG7,"
|
|
hexmask.long 0x15C 0.--31. 1. "CH4CPREG7,Multi Chirp 4 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x160 "CH4CPREG8,"
|
|
hexmask.long 0x160 0.--31. 1. "CH4CPREG8,Multi Chirp 4 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x164 "CH4CPREG9,"
|
|
hexmask.long 0x164 0.--31. 1. "CH4CPREG9,Multi Chirp 4 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x168 "CH4CPREG10,"
|
|
hexmask.long 0x168 0.--31. 1. "CH4CPREG10,Multi Chirp 4 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x16C "CH4CPREG11,"
|
|
hexmask.long 0x16C 0.--31. 1. "CH4CPREG11,Multi Chirp 4 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x170 "CH4CPREG12,"
|
|
hexmask.long 0x170 0.--31. 1. "CH4CPREG12,Multi Chirp 4 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x174 "CH4CPREG13,"
|
|
hexmask.long 0x174 0.--31. 1. "CH4CPREG13,Multi Chirp 4 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x178 "CH4CPREG14,"
|
|
hexmask.long 0x178 0.--31. 1. "CH4CPREG14,Multi Chirp 4 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x17C "CH4CPREG15,"
|
|
hexmask.long 0x17C 0.--31. 1. "CH4CPREG15,Multi Chirp 4 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x180 "CH5CPREG0,"
|
|
hexmask.long 0x180 0.--31. 1. "CH5CPREG0,Multi Chirp 5 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x184 "CH5CPREG1,"
|
|
hexmask.long 0x184 0.--31. 1. "CH5CPREG1,Multi Chirp 5 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x188 "CH5CPREG2,"
|
|
hexmask.long 0x188 0.--31. 1. "CH5CPREG2,Multi Chirp 5 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x18C "CH5CPREG3,"
|
|
hexmask.long 0x18C 0.--31. 1. "CH5CPREG3,Multi Chirp 5 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x190 "CH5CPREG4,"
|
|
hexmask.long 0x190 0.--31. 1. "CH5CPREG4,Multi Chirp 5 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x194 "CH5CPREG5,"
|
|
hexmask.long 0x194 0.--31. 1. "CH5CPREG5,Multi Chirp 5 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x198 "CH5CPREG6,"
|
|
hexmask.long 0x198 0.--31. 1. "CH5CPREG6,Multi Chirp 5 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x19C "CH5CPREG7,"
|
|
hexmask.long 0x19C 0.--31. 1. "CH5CPREG7,Multi Chirp 5 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1A0 "CH5CPREG8,"
|
|
hexmask.long 0x1A0 0.--31. 1. "CH5CPREG8,Multi Chirp 5 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1A4 "CH5CPREG9,"
|
|
hexmask.long 0x1A4 0.--31. 1. "CH5CPREG9,Multi Chirp 5 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1A8 "CH5CPREG10,"
|
|
hexmask.long 0x1A8 0.--31. 1. "CH5CPREG10,Multi Chirp 5 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1AC "CH5CPREG11,"
|
|
hexmask.long 0x1AC 0.--31. 1. "CH5CPREG11,Multi Chirp 5 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1B0 "CH5CPREG12,"
|
|
hexmask.long 0x1B0 0.--31. 1. "CH5CPREG12,Multi Chirp 5 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1B4 "CH5CPREG13,"
|
|
hexmask.long 0x1B4 0.--31. 1. "CH5CPREG13,Multi Chirp 5 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1B8 "CH5CPREG14,"
|
|
hexmask.long 0x1B8 0.--31. 1. "CH5CPREG14,Multi Chirp 5 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1BC "CH5CPREG15,"
|
|
hexmask.long 0x1BC 0.--31. 1. "CH5CPREG15,Multi Chirp 5 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1C0 "CH6CPREG0,"
|
|
hexmask.long 0x1C0 0.--31. 1. "CH6CPREG0,Multi Chirp 6 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1C4 "CH6CPREG1,"
|
|
hexmask.long 0x1C4 0.--31. 1. "CH6CPREG1,Multi Chirp 6 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1C8 "CH6CPREG2,"
|
|
hexmask.long 0x1C8 0.--31. 1. "CH6CPREG2,Multi Chirp 6 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1CC "CH6CPREG3,"
|
|
hexmask.long 0x1CC 0.--31. 1. "CH6CPREG3,Multi Chirp 6 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1D0 "CH6CPREG4,"
|
|
hexmask.long 0x1D0 0.--31. 1. "CH6CPREG4,Multi Chirp 6 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1D4 "CH6CPREG5,"
|
|
hexmask.long 0x1D4 0.--31. 1. "CH6CPREG5,Multi Chirp 6 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1D8 "CH6CPREG6,"
|
|
hexmask.long 0x1D8 0.--31. 1. "CH6CPREG6,Multi Chirp 6 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1DC "CH6CPREG7,"
|
|
hexmask.long 0x1DC 0.--31. 1. "CH6CPREG7,Multi Chirp 6 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1E0 "CH6CPREG8,"
|
|
hexmask.long 0x1E0 0.--31. 1. "CH6CPREG8,Multi Chirp 6 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1E4 "CH6CPREG9,"
|
|
hexmask.long 0x1E4 0.--31. 1. "CH6CPREG9,Multi Chirp 6 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1E8 "CH6CPREG10,"
|
|
hexmask.long 0x1E8 0.--31. 1. "CH6CPREG10,Multi Chirp 6 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1EC "CH6CPREG11,"
|
|
hexmask.long 0x1EC 0.--31. 1. "CH6CPREG11,Multi Chirp 6 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1F0 "CH6CPREG12,"
|
|
hexmask.long 0x1F0 0.--31. 1. "CH6CPREG12,Multi Chirp 6 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1F4 "CH6CPREG13,"
|
|
hexmask.long 0x1F4 0.--31. 1. "CH6CPREG13,Multi Chirp 6 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1F8 "CH6CPREG14,"
|
|
hexmask.long 0x1F8 0.--31. 1. "CH6CPREG14,Multi Chirp 6 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x1FC "CH6CPREG15,"
|
|
hexmask.long 0x1FC 0.--31. 1. "CH6CPREG15,Multi Chirp 6 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x200 "CH7CPREG0,"
|
|
hexmask.long 0x200 0.--31. 1. "CH7CPREG0,Multi Chirp 7 Parameters Register 0. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x204 "CH7CPREG1,"
|
|
hexmask.long 0x204 0.--31. 1. "CH7CPREG1,Multi Chirp 7 Parameters Register 1. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x208 "CH7CPREG2,"
|
|
hexmask.long 0x208 0.--31. 1. "CH7CPREG2,Multi Chirp 7 Parameters Register 2. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x20C "CH7CPREG3,"
|
|
hexmask.long 0x20C 0.--31. 1. "CH7CPREG3,Multi Chirp 7 Parameters Register 3. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x210 "CH7CPREG4,"
|
|
hexmask.long 0x210 0.--31. 1. "CH7CPREG4,Multi Chirp 7 Parameters Register 4. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x214 "CH7CPREG5,"
|
|
hexmask.long 0x214 0.--31. 1. "CH7CPREG5,Multi Chirp 7 Parameters Register 5. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x218 "CH7CPREG6,"
|
|
hexmask.long 0x218 0.--31. 1. "CH7CPREG6,Multi Chirp 7 Parameters Register 6. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x21C "CH7CPREG7,"
|
|
hexmask.long 0x21C 0.--31. 1. "CH7CPREG7,Multi Chirp 7 Parameters Register 7. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x220 "CH7CPREG8,"
|
|
hexmask.long 0x220 0.--31. 1. "CH7CPREG8,Multi Chirp 7 Parameters Register 8. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x224 "CH7CPREG9,"
|
|
hexmask.long 0x224 0.--31. 1. "CH7CPREG9,Multi Chirp 7 Parameters Register 9. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x228 "CH7CPREG10,"
|
|
hexmask.long 0x228 0.--31. 1. "CH7CPREG10,Multi Chirp 7 Parameters Register 10. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x22C "CH7CPREG11,"
|
|
hexmask.long 0x22C 0.--31. 1. "CH7CPREG11,Multi Chirp 7 Parameters Register 11. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x230 "CH7CPREG12,"
|
|
hexmask.long 0x230 0.--31. 1. "CH7CPREG12,Multi Chirp 7 Parameters Register 12. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x234 "CH7CPREG13,"
|
|
hexmask.long 0x234 0.--31. 1. "CH7CPREG13,Multi Chirp 7 Parameters Register 13. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x238 "CH7CPREG14,"
|
|
hexmask.long 0x238 0.--31. 1. "CH7CPREG14,Multi Chirp 7 Parameters Register 14. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
line.long 0x23C "CH7CPREG15,"
|
|
hexmask.long 0x23C 0.--31. 1. "CH7CPREG15,Multi Chirp 7 Parameters Register 15. Refer to Chirp Parameter section for more details (DSS_CP)"
|
|
group.long 0xE48++0x13
|
|
line.long 0x0 "CH01_HIL_CP_OVERRIDE,"
|
|
hexmask.long.word 0x0 16.--31. 1. "chirp1,Override data used for Chirp1. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "chirp0,Override data used for Chirp0. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
line.long 0x4 "CH23_HIL_CP_OVERRIDE,"
|
|
hexmask.long.word 0x4 16.--31. 1. "chirp3,Override data used for Chirp3. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "chirp2,Override data used for Chirp2. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
line.long 0x8 "CH45_HIL_CP_OVERRIDE,"
|
|
hexmask.long.word 0x8 16.--31. 1. "chirp5,Override data used for Chirp5. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "chirp4,Override data used for Chirp4. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
line.long 0xC "CH67_HIL_CP_OVERRIDE,"
|
|
hexmask.long.word 0xC 16.--31. 1. "chirp7,Override data used for Chirp7. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "chirp6,Override data used for Chirp6. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
line.long 0x10 "CH_HIL_CP_OVERRIDE,"
|
|
hexmask.long.word 0x10 0.--15. 1. "chirp,Override data used for Chirp. data[11:0] is used for overriding chirp number data[15:12] is used for overriding chirp profile index"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_wph,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "RSS_RCM"
|
|
base ad:0x5000000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
repeat 3. (list 0x0 0x1 0x3)(list 0x0 0x4 0xC)
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "HW_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser"
|
|
repeat.end
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PREVIOUS_NAME,"
|
|
hexmask.long 0x0 0.--31. 1. "hwreg,HW Reserved regiser"
|
|
group.long 0x14++0x1F
|
|
line.long 0x0 "RSS_CSI2A_SYS_CLK_GATE,"
|
|
bitfld.long 0x0 0.--2. "gated,Clock gatring config for RSS CSI2A Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x4 "RSS_BSS_SYS_CLK_GATE,"
|
|
bitfld.long 0x4 0.--2. "gated,Clock gatring config for RSS BSS Data should be loaded as multibit. Write 3'b000 : Clock is ungated Write 3'b111 : Clock is gated" "0: Clock is ungated Write 3'b111 : Clock is gated,?,?,?,?,?,?,?"
|
|
line.long 0x8 "RSS_CSI2A_RST_CTRL,"
|
|
bitfld.long 0x8 0.--2. "assert,This feature is for debug pupose only. software need to ensure the correct state of Device/IP before configuring this reset control for RSS CSI2A Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
line.long 0xC "RSS_EDMA_RST_CTRL,"
|
|
bitfld.long 0xC 8.--10. "tptca0_assert,writing '111' will reset MSS_TPCCA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "tpcca_assert,This feature is for debug pupose only. software need to ensure the correct state of Device/IP before configuring this reset control for RSS EDMA Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
newline
|
|
bitfld.long 0xC 0.--2. "assert,This feature is for debug pupose only. software need to ensure the correct state of Device/IP before configuring this reset control for RSS EDMA Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
line.long 0x10 "RSS_BSS_RST_CTRL,"
|
|
bitfld.long 0x10 0.--2. "assert,This feature is for debug pupose only. software need to ensure the correct state of Device/IP before configuring this reset control for RSS BSS Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
line.long 0x14 "RSS_FRC_CLK_SRC_SEL,"
|
|
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for FRC.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register. Refer to TPR12 clock spec for source clock reference"
|
|
line.long 0x18 "RSS_FRC_CLK_GATE,"
|
|
bitfld.long 0x18 0.--2. "gated,writing 3'b111 will gate the clock for FRC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "RSS_FRC_CLK_DIV_VAL,"
|
|
hexmask.long.word 0x1C 0.--11. 1. "clkdivr,Divider value for FRC selected clock.Data should be loaded as multibit. For example: if divider value of 8(1000) should be selected then '100010001000' should be configured to the register. Refer to TPR12 clock planner for clock reference"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "RSS_FRC_CLK_STATUS,"
|
|
hexmask.long.byte 0x0 8.--15. 1. "currdivider,Status shows the current divider value choosen for FRC"
|
|
hexmask.long.byte 0x0 0.--7. 1. "clkinuse,Status shows the source clock slected for FRC"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "RSS_FRC_RST_CTRL,"
|
|
bitfld.long 0x0 0.--2. "assert,This feature is for debug pupose only. software need to ensure the correct state of Device/IP before configuring this reset control for RSS FRC Data should be loaded as multibit. Write 3'b000: Reset is not asserted by SW. There could be another.." "0: Reset is not asserted by SW,?,?,?,?,?,?,7: Reset is asserted by SW"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_wph,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "RSS_TPCC_A"
|
|
base ad:0x5100000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "PID,Peripheral ID Register"
|
|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
|
|
line.long 0x4 "CCCFG,CC Configuration Register"
|
|
hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD"
|
|
bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included"
|
|
newline
|
|
bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included"
|
|
bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
|
|
bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD"
|
|
hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N."
|
|
newline
|
|
bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel."
|
|
rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x3
|
|
line.long 0x0 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel."
|
|
rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x7
|
|
line.long 0x0 "QUETCMAP,Queue to TC Mapping"
|
|
hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD"
|
|
bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "QUEPRI,Queue Priority"
|
|
hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD"
|
|
bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1"
|
|
bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x7
|
|
line.long 0x0 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit.."
|
|
bitfld.long 0x0 31. "E31,Event Missed #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
line.long 0x4 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated.."
|
|
bitfld.long 0x4 31. "E63,Event Missed #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed #32" "0,1"
|
|
wgroup.long 0x308++0x7
|
|
line.long 0x0 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
line.long 0x4 "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x0 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR).."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed #0" "0,1"
|
|
group.long 0x314++0x3
|
|
line.long 0x0 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1"
|
|
rgroup.long 0x318++0x3
|
|
line.long 0x0 "CCERR,CC Error Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "?,1: Watermark/threshold has been exceeded"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: QTHRXCD0 = 0 : Watermark/threshold has not been..,1: Watermark/threshold has been exceeded"
|
|
group.long 0x31C++0x7
|
|
line.long 0x0 "CCERRCLR,CC Error Clear Register"
|
|
hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD"
|
|
bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1"
|
|
bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "?,1: Write of '1' clears the values of QSTAT1"
|
|
newline
|
|
bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0: Write of '1' clears the values of QSTAT0,?"
|
|
line.long 0x4 "EEVAL,Error Eval Register"
|
|
hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD"
|
|
bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1"
|
|
group.long 0x340++0x7
|
|
line.long 0x0 "DRAEM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
|
|
line.long 0x4 "DRAEHM,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt.."
|
|
bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "QRAEN,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD"
|
|
bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.."
|
|
repeat.end
|
|
rgroup.long 0x600++0x3
|
|
line.long 0x0 "QSTATN,QSTATn Register Set"
|
|
hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD"
|
|
bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR,1: Threshold specified by QWMTHR"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10.."
|
|
newline
|
|
bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)"
|
|
group.long 0x620++0x3
|
|
line.long 0x0 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0.."
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD"
|
|
hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value"
|
|
newline
|
|
rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value"
|
|
rgroup.long 0x640++0x3
|
|
line.long 0x0 "CCSTAT,CC Status Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD"
|
|
bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7"
|
|
newline
|
|
bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6"
|
|
bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5"
|
|
newline
|
|
bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4"
|
|
bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3"
|
|
newline
|
|
bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2"
|
|
bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1"
|
|
newline
|
|
bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0"
|
|
bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.."
|
|
bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
|
|
bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.."
|
|
bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
newline
|
|
bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "AETCTL,Advanced Event Trigger Control"
|
|
bitfld.long 0x0 31. "EN,AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled"
|
|
hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)"
|
|
rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA Events,1: Event specified by STARTEVT applies to QDMA.."
|
|
hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)"
|
|
rgroup.long 0x704++0x3
|
|
line.long 0x0 "AETSTAT,Advanced Event Trigger Stat"
|
|
hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "STAT,AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high"
|
|
group.long 0x708++0x3
|
|
line.long 0x0 "AETCMD,AET Command"
|
|
hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD"
|
|
bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1000++0x7
|
|
line.long 0x0 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low).."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1008++0xF
|
|
line.long 0x0 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1018++0xF
|
|
line.long 0x0 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1028++0xF
|
|
line.long 0x0 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1038++0x7
|
|
line.long 0x0 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x1040++0x7
|
|
line.long 0x0 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x1050++0x7
|
|
line.long 0x0 "IER,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1058++0xF
|
|
line.long 0x0 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x1068++0x7
|
|
line.long 0x0 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x1070++0x7
|
|
line.long 0x0 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x1078++0x3
|
|
line.long 0x0 "IEVAL,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x1080++0x7
|
|
line.long 0x0 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x1088++0x7
|
|
line.long 0x0 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x1094++0x3
|
|
line.long 0x0 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2000++0x7
|
|
line.long 0x0 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2008++0xF
|
|
line.long 0x0 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2018++0xF
|
|
line.long 0x0 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2028++0xF
|
|
line.long 0x0 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
line.long 0x8 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x8 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x8 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x8 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x8 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x8 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x8 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x8 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x8 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x8 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x8 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x8 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x8 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x8 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x8 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x8 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x8 0. "E0,Event #0" "0,1"
|
|
line.long 0xC "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0xC 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0xC 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0xC 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0xC 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0xC 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0xC 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0xC 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0xC 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0xC 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0xC 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0xC 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0xC 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0xC 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0xC 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0xC 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0xC 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2038++0x7
|
|
line.long 0x0 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in.."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently.."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
wgroup.long 0x2040++0x7
|
|
line.long 0x0 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect."
|
|
bitfld.long 0x0 31. "E31,Event #31" "0,1"
|
|
bitfld.long 0x0 30. "E30,Event #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "E29,Event #29" "0,1"
|
|
bitfld.long 0x0 28. "E28,Event #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "E27,Event #27" "0,1"
|
|
bitfld.long 0x0 26. "E26,Event #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "E25,Event #25" "0,1"
|
|
bitfld.long 0x0 24. "E24,Event #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "E23,Event #23" "0,1"
|
|
bitfld.long 0x0 22. "E22,Event #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "E21,Event #21" "0,1"
|
|
bitfld.long 0x0 20. "E20,Event #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "E19,Event #19" "0,1"
|
|
bitfld.long 0x0 18. "E18,Event #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "E17,Event #17" "0,1"
|
|
bitfld.long 0x0 16. "E16,Event #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "E15,Event #15" "0,1"
|
|
bitfld.long 0x0 14. "E14,Event #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "E13,Event #13" "0,1"
|
|
bitfld.long 0x0 12. "E12,Event #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "E11,Event #11" "0,1"
|
|
bitfld.long 0x0 10. "E10,Event #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "E9,Event #9" "0,1"
|
|
bitfld.long 0x0 8. "E8,Event #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect."
|
|
bitfld.long 0x4 31. "E63,Event #63" "0,1"
|
|
bitfld.long 0x4 30. "E62,Event #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "E61,Event #61" "0,1"
|
|
bitfld.long 0x4 28. "E60,Event #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "E59,Event #59" "0,1"
|
|
bitfld.long 0x4 26. "E58,Event #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "E57,Event #57" "0,1"
|
|
bitfld.long 0x4 24. "E56,Event #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "E55,Event #55" "0,1"
|
|
bitfld.long 0x4 22. "E54,Event #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "E53,Event #53" "0,1"
|
|
bitfld.long 0x4 20. "E52,Event #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "E51,Event #51" "0,1"
|
|
bitfld.long 0x4 18. "E50,Event #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "E49,Event #49" "0,1"
|
|
bitfld.long 0x4 16. "E48,Event #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "E47,Event #47" "0,1"
|
|
bitfld.long 0x4 14. "E46,Event #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "E45,Event #45" "0,1"
|
|
bitfld.long 0x4 12. "E44,Event #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "E43,Event #43" "0,1"
|
|
bitfld.long 0x4 10. "E42,Event #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "E41,Event #41" "0,1"
|
|
bitfld.long 0x4 8. "E40,Event #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "E39,Event #39" "0,1"
|
|
bitfld.long 0x4 6. "E38,Event #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "E37,Event #37" "0,1"
|
|
bitfld.long 0x4 4. "E36,Event #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "E35,Event #35" "0,1"
|
|
bitfld.long 0x4 2. "E34,Event #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "E33,Event #33" "0,1"
|
|
bitfld.long 0x4 0. "E32,Event #32" "0,1"
|
|
rgroup.long 0x2050++0x7
|
|
line.long 0x0 "IER_RN,Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2058++0xF
|
|
line.long 0x0 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
line.long 0x8 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0xC "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.."
|
|
bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
rgroup.long 0x2068++0x7
|
|
line.long 0x0 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
wgroup.long 0x2070++0x7
|
|
line.long 0x0 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1"
|
|
bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1"
|
|
bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1"
|
|
bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1"
|
|
bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1"
|
|
bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1"
|
|
bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1"
|
|
bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1"
|
|
bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1"
|
|
bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1"
|
|
bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1"
|
|
bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1"
|
|
bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1"
|
|
bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1"
|
|
bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1"
|
|
bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1"
|
|
bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1"
|
|
line.long 0x4 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC."
|
|
bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1"
|
|
bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1"
|
|
bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1"
|
|
bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1"
|
|
bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1"
|
|
bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1"
|
|
bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1"
|
|
bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1"
|
|
bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1"
|
|
bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1"
|
|
bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1"
|
|
bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1"
|
|
bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1"
|
|
bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1"
|
|
bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1"
|
|
bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1"
|
|
bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1"
|
|
group.long 0x2078++0x3
|
|
line.long 0x0 "IEVAL_RN,Interrupt Eval Register"
|
|
hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD"
|
|
bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1"
|
|
rgroup.long 0x2080++0x7
|
|
line.long 0x0 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
group.long 0x2088++0x7
|
|
line.long 0x0 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
line.long 0x4 "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.."
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD"
|
|
bitfld.long 0x4 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x4 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x4 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x4 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "E0,Event #0" "0,1"
|
|
rgroup.long 0x2090++0x3
|
|
line.long 0x0 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is.."
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD"
|
|
bitfld.long 0x0 7. "E7,Event #7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "E6,Event #6" "0,1"
|
|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "E4,Event #4" "0,1"
|
|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "E2,Event #2" "0,1"
|
|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "E0,Event #0" "0,1"
|
|
group.long 0x2094++0x3
|
|
line.long 0x0 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU.."
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|
hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD"
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bitfld.long 0x0 7. "E7,Event #7" "0,1"
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newline
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bitfld.long 0x0 6. "E6,Event #6" "0,1"
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|
bitfld.long 0x0 5. "E5,Event #5" "0,1"
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newline
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bitfld.long 0x0 4. "E4,Event #4" "0,1"
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|
bitfld.long 0x0 3. "E3,Event #3" "0,1"
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newline
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bitfld.long 0x0 2. "E2,Event #2" "0,1"
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|
bitfld.long 0x0 1. "E1,Event #1" "0,1"
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|
newline
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bitfld.long 0x0 0. "E0,Event #0" "0,1"
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|
tree.end
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|
tree "RSS_TPTC_A0"
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|
base ad:0x5160000
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rgroup.long 0x0++0x7
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|
line.long 0x0 "PID,Peripheral ID Register"
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|
bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family."
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newline
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hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version"
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bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3"
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hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision"
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line.long 0x4 "TCCFG,TC Configuration Register"
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|
bitfld.long 0x4 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
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bitfld.long 0x4 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
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newline
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bitfld.long 0x4 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
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rgroup.long 0x100++0x7
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line.long 0x0 "TCSTAT,TC Status Register"
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bitfld.long 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3"
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bitfld.long 0x0 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy"
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newline
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bitfld.long 0x0 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "WSACTV,Write Status Active WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands. WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write.." "0: Write status is not pending,1: Write Status is pending"
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newline
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bitfld.long 0x0 1. "SRCACTV,Source Active State SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1]. SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.."
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bitfld.long 0x0 0. "PROGBUSY,Program Register Set Busy PROGBUSY = 0 : Prog set idle and is available for programming. PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy"
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line.long 0x4 "INTSTAT,Interrupt Status Register"
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bitfld.long 0x4 1. "TRDONE,TR Done Event Status: TRDONE = 0 : Condition not detected. TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to.." "0: Condition not detected,1: Set when TC has completed a Transfer Request"
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bitfld.long 0x4 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY = 0 : Condition not detected. PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.."
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group.long 0x108++0x3
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line.long 0x0 "INTEN,Interrupt Enable Register"
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bitfld.long 0x0 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE = 0 : TRDONE Event is disabled. INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.."
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bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled. INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.."
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wgroup.long 0x10C++0x7
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line.long 0x0 "INTCLR,Interrupt Clear Register"
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bitfld.long 0x0 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE = 0 : Writes of '0' have no effect. INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
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bitfld.long 0x0 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect. INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT"
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line.long 0x4 "INTCMD,Interrupt Command Register"
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bitfld.long 0x4 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
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bitfld.long 0x4 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
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rgroup.long 0x120++0x3
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line.long 0x0 "ERRSTAT,Error Status Register"
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bitfld.long 0x0 3. "MMRAERR,MMR Address Error: MMRAERR = 0 : Condition not detected. MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.."
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bitfld.long 0x0 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1"
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newline
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bitfld.long 0x0 0. "BUSERR,Bus Error Event: BUSERR = 0: Condition not detected. BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.."
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group.long 0x124++0x3
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line.long 0x0 "ERREN,Error Enable Register"
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bitfld.long 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR = 0 : BUSERR is disabled. ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.."
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bitfld.long 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR = 0 : BUSERR is disabled. ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.."
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newline
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bitfld.long 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR = 0 : BUSERR is disabled. ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.."
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wgroup.long 0x128++0x3
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line.long 0x0 "ERRCLR,Error Clear Register"
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bitfld.long 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR = 0 : Writes of '0' have no effect. ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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bitfld.long 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR = 0 : Writes of '0' have no effect. ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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newline
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bitfld.long 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR = 0 : Writes of '0' have no effect. ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT"
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rgroup.long 0x12C++0x3
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line.long 0x0 "ERRDET,Error Details Register"
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bitfld.long 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
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bitfld.long 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1"
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newline
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hexmask.long.byte 0x0 8.--13. 1. "15-14,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error."
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hexmask.long.byte 0x0 0.--3. 1. "13-8,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle.."
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wgroup.long 0x130++0x3
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line.long 0x0 "ERRCMD,Error Command Register"
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bitfld.long 0x0 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect." "0,1"
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bitfld.long 0x0 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect." "0,1"
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group.long 0x140++0x3
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line.long 0x0 "RDRATE,Read Rate Register"
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bitfld.long 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7"
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group.long 0x200++0x13
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line.long 0x0 "POPT,Prog Set Options"
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bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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newline
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
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hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
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newline
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bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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newline
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bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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line.long 0x4 "PSRC,Prog Set Src Address"
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hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set"
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line.long 0x8 "PCNT,Prog Set Count"
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hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length."
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hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
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line.long 0xC "PDST,Prog Set Dst Address"
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hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set"
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line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
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hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
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hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.."
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rgroup.long 0x214++0x3
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line.long 0x0 "PMPPRXY,Prog Set Mem Protect Proxy"
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bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
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group.long 0x240++0x3
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line.long 0x0 "SAOPT,Src Actv Set Options"
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bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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newline
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
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hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
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newline
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bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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newline
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bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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rgroup.long 0x244++0x23
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line.long 0x0 "SASRC,Src Actv Set Src Address"
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hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set"
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line.long 0x4 "SACNT,Src Actv Set A-Count"
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hexmask.long.tbyte 0x4 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension."
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line.long 0x8 "SADST,Src Actv Set Dst Address"
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hexmask.long 0x8 0.--31. 1. "DADDR,Destination address for Source Active Register Set"
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line.long 0xC "SABIDX,Src Actv Set B-Dim Idx"
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hexmask.long.word 0xC 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.."
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hexmask.long.word 0xC 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used.."
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line.long 0x10 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
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bitfld.long 0x10 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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bitfld.long 0x10 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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newline
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hexmask.long.byte 0x10 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
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line.long 0x14 "SACNTRLD,Src Actv Set Cnt Reload"
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hexmask.long.word 0x14 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.."
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line.long 0x18 "SASRCBREF,Src Actv Set Src Addr B-Reference"
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hexmask.long 0x18 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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line.long 0x1C "SADSTBREF,Src Actv Set Dst Addr B-Reference"
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hexmask.long 0x1C 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0."
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line.long 0x20 "SABCNT,Src Actv Set B-Count"
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hexmask.long.word 0x20 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT.."
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rgroup.long 0x280++0x7
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line.long 0x0 "DFCNTRLD,Dst FIFO Set Cnt Reload"
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hexmask.long.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by.."
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line.long 0x4 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
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hexmask.long 0x4 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value."
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repeat 2. (list 0x0 0x1)(list 0x0 0x40)
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group.long ($2+0x300)++0x3
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line.long 0x0 "DFOPT$1,Dst FIFO Set Options"
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bitfld.long 0x0 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3"
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bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled"
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newline
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bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled"
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hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module."
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newline
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bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 4.--6. "PRI,Transfer Priority: 0: Priority 0 - Highest priority 1: Priority 1 ... 7: Priority 7 - Lowest priority" "0: Priority 0,1: Priority 1,?,?,?,?,?,7: Priority 7"
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newline
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bitfld.long 0x0 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.."
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bitfld.long 0x0 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.."
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repeat.end
|
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repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x304)++0x3
|
|
line.long 0x0 "DFSRC$1,Dst FIFO Set Src Address"
|
|
hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0."
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repeat.end
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repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x308)++0x3
|
|
line.long 0x0 "DFACNT$1,Dst FIFO Set A-Count"
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|
hexmask.long.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension."
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repeat.end
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repeat 2. (list 0x0 0x1)(list 0x0 0x40)
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|
rgroup.long ($2+0x30C)++0x3
|
|
line.long 0x0 "DFDST$1,Dst FIFO Set Dst Address"
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|
hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set: Initial value is copied from PDST.DADDR. TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued. When a TR.."
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repeat.end
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repeat 2. (list 0x0 0x1)(list 0x0 0x40)
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|
rgroup.long ($2+0x310)++0x3
|
|
line.long 0x0 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
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|
hexmask.long.word 0x0 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is.."
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|
repeat.end
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repeat 2. (list 0x0 0x1)(list 0x0 0x40)
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|
rgroup.long ($2+0x314)++0x3
|
|
line.long 0x0 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
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|
bitfld.long 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1"
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|
bitfld.long 0x0 8. "PRIV,Privilege Level: PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger.." "0: User level privilege PRIV =,1: Supervisor level privilege PMPPRXY"
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|
newline
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hexmask.long.byte 0x0 0.--3. 1. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the value.."
|
|
repeat.end
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|
repeat 2. (list 0x0 0x1)(list 0x0 0x40)
|
|
rgroup.long ($2+0x318)++0x3
|
|
line.long 0x0 "DFBCNT$1,Dst FIFO Set B-Count"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
|
|
repeat.end
|
|
tree.end
|
|
tree "TOP_AURORA_TX"
|
|
base ad:0x3060000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
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newline
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hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
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|
newline
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bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
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|
newline
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|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
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|
newline
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|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "AURORA_TX_CONFIG,"
|
|
bitfld.long 0x0 16.--18. "AURORA_TX_CONFIG_NUM_LANES,Selects the number of lanes for trasnmission 0 : 1 Lane 1 : 2 Lanes 7 : 8Lanes" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x0 2. "AURORA_TX_CONFIG_STRICT_ALIGN,Enable Aurora Strict Alingment Rules" "0,1"
|
|
newline
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bitfld.long 0x0 1. "AURORA_TX_CONFIG_PROTOCOL_SEL,Selects if the IP is in 8b/10b OR 64b/66b mode. 0 : 8b/10b 1 : 64b/66b" "0,1"
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|
newline
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bitfld.long 0x0 0. "AURORA_TX_CONFIG_ENABLE,Selects if the IP is in 8b/10b OR 64b/66b mode. 0 : 8b/10b 1 : 64b/66b" "0,1"
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|
line.long 0x4 "AURORA_TX_LANE_MAP,"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AURORA_TX_LANE_MAP_LANE7_M,These 3 bits determine the logical lane that is transported over the physical lane 7. 000 : Logical lane 0 is transported over physical lane 7 001 : Logical lane 1 is transported over physical lane 7. .. 111 : Logical.."
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|
newline
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hexmask.long.byte 0x4 24.--27. 1. "AURORA_TX_LANE_MAP_LANE6_M,These 3 bits determine the logical lane that is transported over the physical lane 6. 000 : Logical lane 0 is transported over physical lane 6 001 : Logical lane 1 is transported over physical lane 6. .. 111 : Logical.."
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|
newline
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hexmask.long.byte 0x4 20.--23. 1. "AURORA_TX_LANE_MAP_LANE5_M,These 3 bits determine the logical lane that is transported over the physical lane 5. 000 : Logical lane 0 is transported over physical lane 5 001 : Logical lane 1 is transported over physical lane 5. .. 111 : Logical.."
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|
newline
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hexmask.long.byte 0x4 16.--19. 1. "AURORA_TX_LANE_MAP_LANE4_M,These 3 bits determine the logical lane that is transported over the physical lane 4. 000 : Logical lane 0 is transported over physical lane 4. 001 : Logical lane 1 is transported over physical lane 4. .. 111 : Logical.."
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|
newline
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hexmask.long.byte 0x4 12.--15. 1. "OVER THE PHYSICAL LANE 3.,These 3 bits determine the logical lane that is transported over the physical lane 3. 000 : Logical lane 0 is transported over physical lane 3 001 : Logical lane 1 is transported over physical lane 3. .. 111 : Logical.."
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|
newline
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hexmask.long.byte 0x4 8.--11. 1. "000,These 3 bits determine the logical lane that is transported over the physical lane 2. 000 : Logical lane 0 is transported over physical lane 2 001 : Logical lane 1 is transported over physical lane 2. .. 111 : Logical lane 7 is transported.."
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|
newline
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hexmask.long.byte 0x4 4.--7. 1. "001,These 3 bits determine the logical lane that is transported over the physical lane 1. 000 : Logical lane 0 is transported over physical lane 1 001 : Logical lane 1 is transported over physical lane 1. .. 111 : Logical lane 7 is transported.."
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|
newline
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hexmask.long.byte 0x4 0.--3. 1. "...,These 3 bits determine the logical lane that is transported over the physical lane 0. 000 : Logical lane 0 is transported over physical lane 0. 001 : Logical lane 0 is transported over physical lane 1 .. 111 : Logical lane 7 is transported.."
|
|
line.long 0x8 "AURORA_TX_UDP_CONFIG,"
|
|
hexmask.long.byte 0x8 16.--20. 1. "AURORA_TX_UDP_CONFIG_FRAME_,Header Enable configuration 0x0 : Disable Header transmission 0x1 - 0x10 : Number of 32 bit Header to be transmmited"
|
|
newline
|
|
bitfld.long 0x8 8. "HEADER_EN,Writing a value of 1'b1 : Bypass the aurora protocol. - No aurora framing is done 1'b0 : Normal Mode - Framing is done as per aurora protocol" "0: Normal Mode,1: Bypass the aurora protocol"
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|
newline
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bitfld.long 0x8 7. "WRITING A VALUE OF,Writing a value of 1'b1: Enable the test pattern generation when the aurora transmitter is in IDLE state." "?,1: Enable the test pattern generation when the.."
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|
newline
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bitfld.long 0x8 6. "1'B1,Writing a value of 1'b1 : Enables the compression of incoming synchronisation packets. This allows only a configurable number of TWP synchronization packets define by AURORA_TX_TWP_SYNC_CNT::AURORA_TX_TWP_SYNC_CNT_SYNC_CNT to be send through aurora.." "0: Disable the TWP padding packet filter,1: Enables the compression of incoming.."
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|
newline
|
|
bitfld.long 0x8 5. "SYNCHRONISATION PACKETS.,Writing a value of 1'b1 : Enable the UDP CRC calculation 1'b0 : Disable UDP CRC calculation" "?,1: Enable the UDP CRC calculation 1'b0 : Disable.."
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|
newline
|
|
bitfld.long 0x8 4. "THIS ALLOWS ONLY A CONFIGURABLE NUMBER OF TWP,Writing a value of 1'b1 : Filters out the incoming TWP Padding Packet from being send via aurora interface. 1'b0 : Disable the TWP padding packet filter." "0: Disable the TWP padding packet filter,1: Filters out the incoming TWP Padding Packet from.."
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|
newline
|
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bitfld.long 0x8 0.--1. "SYNCHRONIZATION PACKETS DEFINE BY,Configure to select AURORATX_UDP_SIZE format 0: Number of TWP Packets 1 : Number of Bytes 3: SW only" "0: Number of TWP Packets,1: Number of Bytes 3: SW only,?,?"
|
|
line.long 0xC "AURORA_TX_UDP_SIZE,"
|
|
hexmask.long 0xC 0.--31. 1. "AURORA_TX_UDP_SIZE,Configure the number of TWP packets or data bytes to be sent as one packet based on AURORATX_CTRL::PACK_MODE. If PACK_MODE=1 Value configure should be multiple of 4 Bytes."
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|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "AURORA_TX_UDP_FRAME_HEADER$1,"
|
|
hexmask.long 0x0 0.--31. 1. "AURORA_TX_UDP_FRAME_HEADE,32 bit DATA Sent out as Frame Header"
|
|
repeat.end
|
|
group.long 0x64++0xF
|
|
line.long 0x0 "AURORA_TX_UFC_MSG_CTRL,"
|
|
bitfld.long 0x0 0. "AURORA_TX_UFC_MSG_CTRL_UFC_MS,This bit indicates that the message send triggered by the SEND_MSG bit has been completed. Read 1 : Either a hardware or software UFC event occurred. Read 0 : No UFC event occurred. Write 0 : No effect. Write 1 : Clears.." "0: No effect,1: Clears this bit"
|
|
line.long 0x4 "AURORA_TX_UFC_MESSAGE0,"
|
|
hexmask.long 0x4 0.--31. 1. "AURORA_TX_UFC_MESSAGE0_ME,This register contains the octets 0 through 3 of the UFC message. All octets have a default value of 0x0A."
|
|
line.long 0x8 "AURORA_TX_UFC_MESSAGE1,"
|
|
hexmask.long 0x8 0.--31. 1. "AURORA_TX_UFC_MESSAGE1_ME,This register contains the octets 4 through 7 of the UFC message. All octets have a default value of 0x0A."
|
|
line.long 0xC "AURORA_TX_TWP_SYNC_CNT,"
|
|
hexmask.long.word 0xC 0.--9. 1. "AURORA_TX_TWP_SYNC_CNT_SYNC_,Number of TWP Sync Packet that would be sent if AURORA_TX_UDP_CONFIG::A_TX_UDP_CONFIG_TWP_SYNC_COMPRESSION_EN is 0x1. (Min Value 2)"
|
|
group.long 0x80++0x1F
|
|
line.long 0x0 "AURORA_TX_INITIALIZE_REQ,"
|
|
bitfld.long 0x0 1. "AURORA_TX_INITIALIZE_REQ_TX_INIT,The single bit input to trigger the initialization sequence. Asserting this bit starts Tx process." "0,1"
|
|
line.long 0x4 "AURORA_TX_UFC_MSG_REQ,"
|
|
bitfld.long 0x4 0. "AURORA_TX_UFC_MSG_REQ_SEND_M,The bit that triggers the controller to send the MESSAGE0 and MESSAGE1 register contents as a UFC packet." "0,1"
|
|
line.long 0x8 "AURORA_TX_FLUSH_REQ,"
|
|
bitfld.long 0x8 0. "AURORA_TX_FLUSH_REQ_TRIGGER,Selects the number of lanes for trasnmission 0 : 1 Lane 1 : 2 Lanes 7 : 8Lanes" "0,1"
|
|
line.long 0xC "AURORA_TX_EOP_REQ,"
|
|
bitfld.long 0xC 0. "AURORA_TX_EOP_REQ_TRIGG,SW End of Packet trigger to aurora dataframer." "0,1"
|
|
line.long 0x10 "AURORA_TX_DATA_START_REQ,"
|
|
bitfld.long 0x10 1. "AURORA_TX_DATA_START_REQ_DATA,The single bit input to trigger the initialization sequence. Asserting this bit starts Tx process." "0,1"
|
|
line.long 0x14 "AURORA_TX_DATA_STOP_REQ,"
|
|
bitfld.long 0x14 1. "AURORA_TX_DATA_STOP_REQ_DATA_S,The single bit input to trigger the Start of Data Transmission" "0,1"
|
|
line.long 0x18 "AURORA_TX_TESTPATTERN_START_REQ,"
|
|
bitfld.long 0x18 1. "AURORA_TX_TESTPATTERN_START_R,The single bit input to trigger the Stop of Data Transmission" "0,1"
|
|
line.long 0x1C "AURORA_TX_TESTPATTERN_STOP_REQ,"
|
|
bitfld.long 0x1C 1. "AURORA_TX_TESTPATTERN_STOP_REQ,The single bit input to trigger the Start of TestPattern Transmission" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "AURORA_TX_OVERRIDE,"
|
|
bitfld.long 0x0 22. "7,This read write bit indicates whether the CC1_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 21. "AURORA_TX_OVERRIDE_INIT_SP3_OVR,This read write bit indicates whether the CC0_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 20. "_TYP,This read write bit indicates whether the INIT_V3_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 19. "AURORA_TX_OVERRIDE_INIT_SP2_OVR,This read write bit indicates whether the INIT_V2_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 18. "_TYP,This read write bit indicates whether the INIT_V1_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 17. "AURORA_TX_OVERRIDE_INIT_SP1_OVR,This read write bit indicates whether the INIT_V0_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 16. "_TYP,This read write bit indicates whether the INIT_SP3_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 15. "AURORA_TX_OVERRIDE_INIT_SP0_OVR,This read write bit indicates whether the INIT_SP2_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 14. "_TYP,This read write bit indicates whether the INIT_SP1_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 13. "AURORA_TX_OVERRIDE_UFC_SUF_OVR,This read write bit indicates whether the INIT_SP0_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 12. "_TYP,This read write bit indicates whether the UFC_SUF_OVR_TYP symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 11. "AURORA_TX_OVERRIDE_I2_OVR_TYP,This read write bit indicates whether the I2_OVR symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 10. "AURORA_TX_OVERRIDE_I1_OVR_TYP,This read write bit indicates whether the I1_OVR symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 9. "AURORA_TX_OVERRIDE_I0_OVR_TYP,This read write bit indicates whether the I0_OVR symbol is a /D/ octet or /K/ octet. 1 : Indicates a /K/ octet. 0 : Indicates a /D/ octet." "0: Indicates a /D/ octet,1: Indicates a /K/ octet"
|
|
newline
|
|
bitfld.long 0x0 8. "AURORA_TX_OVERRIDE_SYM_OVR_EN RW,This read write bit allows the symbols used in the various sequences to be overridden with the values used in the AURORA_TX_SYM register." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "AURORA_TX_OVERRIDE_TX_STATE_OV,These bits take effect to enforce a certain transmission state if the TX_ST_OVR_EN bit is set. The states are enforced as per the following bit values: 0000 : Reset no transmission. 0001 : Initialization 0010 : Clock.."
|
|
newline
|
|
bitfld.long 0x0 0. "R_VAL,This read write bit allows the user to force the IP to remain in a given transmission state. The enforced transmission state is defined by the TX_ST_OVR bits." "0,1"
|
|
line.long 0x4 "AURORA_TX_8B10B_OVERRIDE0,"
|
|
hexmask.long.byte 0x4 24.--31. 1. "AURORA_TX_8B10B_OVERRIDE0_U,The 8B/10B protocol defines Start of User Flow Control PDU symbol /SUF/. The value defined in the octet here allows this value to be overridden. The value defined here will be effective whenever the User Flow Control.."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "FC_SUF,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence. The value defined here will be effective whenever the Idle sequence is used during any transmission state. Default value of this octet is.."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "AURORA_TX_8B10B_OVERRIDE0_I2 RW,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence. The value defined in the octet here allows one of the three to be overridden. The value defined here will be.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "AURORA_TX_8B10B_OVERRIDE0_I1 RW,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence. The value defined here will be effective whenever the Idle sequence is used during any transmission state. Default.."
|
|
line.long 0x8 "AURORA_TX_8B10B_OVERRIDE1,"
|
|
hexmask.long.byte 0x8 24.--31. 1. "AURORA_TX_8B10B_OVERRIDE1_SP,The 8B/10B protocol defines the /D10.2/ as the fourth octet to be used in the Sync Polarity (/SP/) sequence during lane initialization. The value defined in the octet here allows the fourth octet to be overridden. Default.."
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "AURORA_TX_8B10B_OVERRIDE1_SP,The 8B/10B protocol defines the /D10.2/ as the third octet to be used in the Sync Polarity (/SP/) sequence during lane initialization. The value defined in the octet here allows the third octet to be overridden. Default.."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "AURORA_TX_8B10B_OVERRIDE1_SP,The 8B/10B protocol defines the /D10.2/ as the second octet to be used in the Sync Polarity (/SP/) sequence during lane initialization. The value defined in the octet here allows the second octet to be overridden. Default.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "7,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Sync Polarity (/SP/) sequence during lane initialization. The value defined in the octet here allows the first octet to be overridden. Default value of this octet is /K28.5/.."
|
|
line.long 0xC "AURORA_TX_8B10B_OVERRIDE2,"
|
|
hexmask.long.byte 0xC 24.--31. 1. "AURORA_TX_8B10B_OVERRIDE2_V,The 8B/10B protocol defines the /D8.7/ as the fourth octet to be used in the Verification sequence during lane initialization. The value defined in the octet here allows the fourth octet to be overridden. Default value of.."
|
|
newline
|
|
hexmask.long.byte 0xC 16.--23. 1. "AURORA_TX_8B10B_OVERRIDE2_V,The 8B/10B protocol defines the /D8.7/ as the third octet to be used in the Verification sequence during lane initialization. The value defined in the octet here allows the third octet to be overridden. Default value of this.."
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "AURORA_TX_8B10B_OVERRIDE2_V,The 8B/10B protocol defines the /D8.7/ as the second octet to be used in the Verification sequence during lane inititialization. The value defined in the octet here allows the second octet to be overridden. Default value of.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "AURORA_TX_8B10B_OVERRIDE2_V,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Verification sequence during lane inititialization. The value defined in the octet here allows the first octet to be overridden. Default value of.."
|
|
line.long 0x10 "AURORA_TX_8B10B_OVERRIDE3,"
|
|
hexmask.long.byte 0x10 8.--15. 1. "AURORA_TX_8B10B_OVERRIDE3_CC,The 8B/10B protocol defines the /K23.7/ as the second octet to be used in the Clock Compensation sequence. The value defined in the octet here allows the second octet to be overridden. Default value of this octet is /K23.7/.."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "AURORA_TX_8B10B_OVERRIDE3_CC,The 8B/10B protocol defines the /K23.7/ as the first octet to be used in the Clock Compensation sequence. The value defined in the octet here allows the first octet to be overridden. Default value of this octet is /K23.7/.."
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line.long 0x14 "AURORA_TX_64B66B_OVERRIDE1,"
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hexmask.long.byte 0x14 24.--31. 1. "AURORA_TX_64B66B_OVERRIDE1_C,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks. This field may be overriden with the values defined here. These bits are used during Channel Bonding. Bit 8 overrides the CC bit (bit 10.."
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hexmask.long.byte 0x14 16.--23. 1. "B_BITS,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks. The value given in this field may be used to override the BTF for the Channel Bonding code blocks. This value is effective only if the SYM_OVR_EN.."
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hexmask.long.byte 0x14 8.--15. 1. "AURORA_TX_64B66B_OVERRIDE1_C,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks. This field may be overriden with the values defined here. Bit 8 overrides the CC bit (bit 10 of 64B/66B block code) Bit 9 overrides the.."
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hexmask.long.byte 0x14 0.--7. 1. "B_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks. The value given in this field may be used to override the BTF for the Idle code blocks. This value is effective only if the SYM_OVR_EN bit in the.."
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line.long 0x18 "AURORA_TX_64B66B_OVERRIDE2,"
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hexmask.long.byte 0x18 16.--23. 1. "AURORA_TX_64B66B_OVERRIDE2_C,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Channel Bonding Blocks. This field may be overriden with the values defined here. These bits are used during the Clock Compensation block.."
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hexmask.long.byte 0x18 8.--15. 1. "C_BITS,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks. The value given in this field may be used to override the BTF for the Clock Compensation code blocks. This value is effective only if the SYM_OVR_EN.."
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hexmask.long.byte 0x18 0.--7. 1. "AURORA_TX_64B66B_OVERRIDE2_C,The 64B/66B protocol defines the value of 0x2D as the BTF for the UFC code block. The value given in this field may be used to override the BTF for the UFC code block. This value is effective only if the SYM_OVR_EN bit in.."
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line.long 0x1C "AURORA_TX_64B66B_OVERRIDE2,"
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hexmask.long.byte 0x1C 8.--15. 1. "AURORA_TX_64B66B_OVERRIDE2_C,The 64B/66B protocol defines the value of 0xE1 as the BTF for the Separator-7. The value given in this field may be used to override the BTF for Separator-7. This value is effective only if the SYM_OVR_EN bit in the.."
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hexmask.long.byte 0x1C 0.--7. 1. "C_BITS,The 64B/66B protocol defines the value of 0x1E as the BTF for the Separator. The value given in this field may be used to override the BTF for Separator. This value is effective only if the SYM_OVR_EN bit in the AURORA_TX_OVERRIDE register is.."
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group.long 0x124++0x57
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line.long 0x0 "AURORA_TX_INIT_CNT_LRC,"
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hexmask.long 0x0 0.--31. 1. "LRC_N,The 32-bit count value used to move from the TXRESET1 state to the TXINIT0 state. This value indicates the number of times the /SP/ sequence is sent in the TXRESET1 state."
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line.long 0x4 "AURORA_TX_INIT_CNT_ALIGN,"
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hexmask.long.byte 0x4 16.--19. 1. "AURORA_TX_INIT_CNT_ALIGN_ALIGN,Alignment pattern multiplier. Defines the multiplier used in conjunction with ALIGN_LEN when performing link initialization. 0000b: Alignment pattern multiplier is 32. 0001b: Reserved. 0010b: Reserved. 0011b: Reserved."
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hexmask.long.word 0x4 0.--12. 1. "_MUL,The number of times the Aurora alignment pattern is sent. Number of patterns = ALIGN_MUL*(ALIGN_LEN + 1)."
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line.long 0x8 "AURORA_TX_INIT_CNT_BONDING,"
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hexmask.long.byte 0x8 20.--27. 1. "AURORA_TX_INIT_CNT_BONDING_N,The 64B standard mentions that There must be at least four Idle blocks between each Channel Bonding block. in Table 4-1 of the 4.2.1 Lane Initialization section. The user could specify 1 to 16 Idle blocks between the.."
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hexmask.long.byte 0x8 16.--19. 1. "O_OF_IDLES,Bond pattern multiplier. Defines the multiplier used in conjunction with BOND_LEN when performing link initialization. 0000b: Bond pattern multiplier is 4. 0001b: Reserved. Otherwise Bond pattern multiplier is 2n where n is the value of.."
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hexmask.long.word 0x8 0.--8. 1. "AURORA_TX_INIT_CNT_BONDING_B,The number of times the Aurora bonding pattern is sent. Number of patterns = BOND_MUL*(BOND_LEN + 1)."
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line.long 0xC "AURORA_TX_INIT_CNT_VERIFY,"
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hexmask.long.byte 0xC 16.--19. 1. "AURORA_TX_INIT_CNT_VERIFY_VERI,Verify pattern multiplier. Defines the multiplier used in conjunction with VERIFY_LEN when performing link initialization. 0000b: Verify pattern multiplier is 4. 0001b: Reserved. Otherwise Verify pattern multiplier is.."
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hexmask.long.word 0xC 0.--8. 1. "FY_MUL,The number of times the Aurora verification pattern is sent. Number of patterns = VERIFY_MUL*(VERIFY_LEN + 1)."
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line.long 0x10 "AURORA_TX_INIT_CTRL,"
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bitfld.long 0x10 2. "AURORA_TX_INIT_CTRL_TX_VERIFIED,The single bit input to trigger the transition from the verification state to the channel ready state." "0,1"
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bitfld.long 0x10 1. "AURORA_TX_INIT_CTRL_TX_BONDED,The single bit input to trigger the transition from the bonding to the verification state." "0,1"
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bitfld.long 0x10 0. "AURORA_TX_INIT_CTRL_TX_ALIGNED,The single bit input to trigger the Stop of TestPattern Transmission" "0,1"
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line.long 0x14 "AURORA_TX_IDLE_CTRL,"
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hexmask.long.byte 0x14 2.--5. 1. "AURORA_TX_IDLE_CTR,The 4-bit value used to seed the pseudo random integer used in the idle sequence generator."
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line.long 0x18 "AURORA_TX_IDLE_REQ,"
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bitfld.long 0x18 0. "AURORA_TX_IDLE_REQ_SEND_IDLE,This bit is used to trigger the insertion of the IDLE sequence by the software. The IDLE FSM will insert the IDLE sequence octets at the earliest possible opportunity." "0,1"
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line.long 0x1C "AURORA_TX_CC_REQ,"
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bitfld.long 0x1C 1. "AURORA_TX_CC_REQ_SEND_CC,The single bit input that can trigger a CC sequence. The internal FSM will insert a CC sequence at the earliest possible opportunity." "0,1"
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line.long 0x20 "AURORA_TX_CC_CNT,"
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hexmask.long.word 0x20 0.--15. 1. "AURORA_TX_CC_CNT_SYNC_COUNT,The 16-bit count value used to indicate the number of code group octets after which the CC sequence should be transmitted. Default is 0x26FC (decimal 9980) and increasing the period beyond this value is not advised as.."
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line.long 0x24 "AURORA_TX_CB_STATUS,"
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bitfld.long 0x24 0. "AURORA_TX_CB_STATUS_CB_COMP,This bit reflects the state of the Channel Bonding FSM. Read 0 : CB Block is not complete. Read 1 : CB Block is complete. Write 0 : No effect. Write 1 : Clears the bit. Setting the SEND_CB bit also clears this bit. This bit.." "0: No effect,1: Clears the bit"
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line.long 0x28 "AURORA_TX_CB_REQ,"
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bitfld.long 0x28 1. "AURORA_TX_CB_REQ_SEND_CB,The single bit input that can trigger a Channel Bonding Block. The internal FSM will insert a Channel Bonding sequence at the earliest possible opportunity. This bit is applicable only in the 64B/66B protocol mode after the.." "0,1"
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line.long 0x2C "AURORA_TX_CB_CNT,"
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hexmask.long.word 0x2C 0.--15. 1. "AURORA_TX_CB_CNT_CB_COUNT,The 16-bit count value used to indicate the number of data blocks after which the Channel Bonding sequence should be transmitted. The default value is 0x4E20 (decimal 20000). A value of zero will ensure that the Channel Bonding.."
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line.long 0x30 "AURORA_TX_RESET_REQ,"
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bitfld.long 0x30 0. "AURORA_TX_RESET_REQ_TX_RESET,The single bit input to reset the Tx process. Asserting this bit brings all internal FSMs to their reset state. (The TX_INIT bit must be asserted for the FSMs to continue to their next states after the reset state.)" "0,1"
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line.long 0x34 "AURORA_TX_SERIALIZER_OVERRIDE0,"
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hexmask.long 0x34 0.--31. 1. "AURORA_TX_SERIALIZER_OVERRID,Serialzer Override Value0 for Debug/Legacy modes. This value is not expected tp be changed"
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line.long 0x38 "AURORA_TX_SERIALIZER_OVERRIDE1,"
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hexmask.long 0x38 0.--31. 1. "AURORA_TX_SERIALIZER_OVERRID,Serialzer Override Value1 for Debug/Legacy modes. This value is not expected tp be changed"
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line.long 0x3C "AURORA_TX_DATA_BYTE_REVERSE,"
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bitfld.long 0x3C 1. "AURORA_TX_DATA_BYTE_REVERSE_,Enable Byte reversal on the CRC value." "0,1"
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bitfld.long 0x3C 0. "CRC_BYTE_REVERSE_EN,Enable Byte reversal on the input data. Aplicable only on the data from TPIU and Testpattern" "0,1"
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line.long 0x40 "AURORA_TX_64B66B_SCRAMBLER_INIT0,"
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hexmask.long 0x40 0.--31. 1. "AURORA_TX_64B66B_SCRAMBLER_,Initial value in the LFSR scrambler bits[31:0]"
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line.long 0x44 "AURORA_TX_64B66B_SCRAMBLER_INIT1,"
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bitfld.long 0x44 31. "AURORA_TX_64B66B_SCRAMBLER_,Write 0x1 to loaf the scrambler lfsr init value" "0,1"
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hexmask.long 0x44 0.--25. 1. "INIT1_LOAD,Initial value in the LFSR scrambler bits[57:32]"
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line.long 0x48 "AURORA_TX_TESTPATTERN_CTRL,"
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bitfld.long 0x48 0. "AURORA_TX_TESTPATTERN_CTRL_R,Enable a ramp patten as the testpattern" "0,1"
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line.long 0x4C "AURORA_TX_CC_SEQ_CNT,"
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hexmask.long.byte 0x4C 16.--19. 1. "AURORA_TX_CC_SEQ_CNT_COUNT_6,Configure the number of 64b66b Clock Compensation block to be sent. The default value is as per the Aurora Spec. This is intented for Debug purposes only."
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hexmask.long.byte 0x4C 0.--3. 1. "4B66B,Configure the number of 8b10b Clock Compensation octets to be sent. The default value is as per the Aurora Spec. This is intented for Debug purposes only."
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line.long 0x50 "AURORA_TX_EOP_DELAY,"
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bitfld.long 0x50 16. "AURORA_TX_EOP_DELAY_ENABLE,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY" "0,1"
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hexmask.long.word 0x50 0.--15. 1. "AURORA_TX_EOP_DELAY_DELAY,Internal Delay between the Data Framer and the Controller Block to stall data to the controller and force IDLES to be inserted by the controller after an ECP of a UDP. This is a feature added for Debug Purposes only and has not.."
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line.long 0x54 "AURORA_TX_FLUSH_DELAY,"
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hexmask.long.byte 0x54 0.--7. 1. "AURORA_TX_FLUSH_DELAY_DELAY,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY"
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rgroup.long 0x200++0x7
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line.long 0x0 "AURORA_TX_STATUS,"
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hexmask.long.word 0x0 16.--31. 1. "AURORA_TX_STATUS_DATAFRAMER,Dataframer Status fields Bit 16 : Write on Full FIFO Bit 17 : Read on Empty FIFO Bits [20:18] : Run State 000 : OFF.."
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hexmask.long.byte 0x0 0.--3. 1. "AURORA_TX_STATUS_TX_STATE,These read only bits indicate the state of the transmitter in 8B/10B and 64B/66B. 0000 : Reset no transmission. 0001 : Initialization 0010 : Clock Compensation 0011 : Idle 0100 : UFC 0101 : Run (data) 0110 : Test (data) 0111 :.."
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line.long 0x4 "AURORA_TX_INIT_STATUS,"
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bitfld.long 0x4 4. "AURORA_TX_INIT_STATUS_TX_CH_RDY,The status bit that indicates that the channel ready state has been reached. This bit is reset with the device reset and when the TX_RESET bit is set." "0,1"
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bitfld.long 0x4 3. "AURORA_TX_INIT_STATUS_TX_TXCB0,The status bit that indicates that the TX_ TXCB0 state has been completed. This bit is reset with the device reset and when the TX_RESET bit is set." "0,1"
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bitfld.long 0x4 2. "AURORA_TX_INIT_STATUS_TX_INIT0,The status bit that indicates that the TX_INIT0 state has been completed. This bit is reset with the device reset and when the TX_RESET bit is set." "0,1"
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bitfld.long 0x4 1. "AURORA_TX_INIT_STATUS_TX_RESET1,The status bit that indicates that the TX_RESET1 state has been completed. This bit is reset with the device reset and when the TX_RESET bit is set." "0,1"
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bitfld.long 0x4 0. "AURORA_TX_INIT_STATUS_TX_RESET0,The status bit that indicates that the TX_RESET0 state has been completed. This bit is reset with the device reset and when the TX_RESET bit is set." "0,1"
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group.long 0x208++0x1F
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line.long 0x0 "AURORA_TX_CC_STATUS,"
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bitfld.long 0x0 0. "AURORA_TX_CC_STATUS_CC_COMP,This bit reflects the state of the CC FSM. Read 0 : CC sequence is not complete. Read 1 : CC sequence is complete. Write 0 : No effect. Write 1 : Clears the bit. Setting the SEND_CC bit also clears this bit." "0: No effect,1: Clears the bit"
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line.long 0x4 "AURORA_TX_IDLE_STATUS,"
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bitfld.long 0x4 0. "AURORA_TX_IDLE_STATUS_IDLE_COMP,This bit reflects the state of the IDLE FSM. Read 0 : IDLE sequence is not complete. Read 1 : IDLE sequence is complete. Write 0 : No effect. Write 1 : Clears the bit. Setting the SEND_IDLE bit also clears this bit." "0: No effect,1: Clears the bit"
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line.long 0x8 "AURORA_TX_INTAGG_MASK,"
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bitfld.long 0x8 15. "AURORA_TX_INTAGG_MASK_INT15,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 15" "0,1"
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bitfld.long 0x8 14. "AURORA_TX_INTAGG_MASK_INT14,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 14" "0,1"
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bitfld.long 0x8 13. "AURORA_TX_INTAGG_MASK_INT13,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 13" "0,1"
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bitfld.long 0x8 12. "AURORA_TX_INTAGG_MASK_INT12,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 12" "0,1"
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bitfld.long 0x8 11. "AURORA_TX_INTAGG_MASK_INT11,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 11" "0,1"
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bitfld.long 0x8 10. "AURORA_TX_INTAGG_MASK_INT10,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 10" "0,1"
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bitfld.long 0x8 9. "AURORA_TX_INTAGG_MASK_INT9,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 9" "0,1"
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bitfld.long 0x8 8. "AURORA_TX_INTAGG_MASK_INT8,Mask the the corresponding event line from generating an Interrupt. This field masks the interrupt from Event 8" "0,1"
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bitfld.long 0x8 7. "AURORA_TX_INTAGG_MASK_INT7,Mask Interrupt AURORA_TX_HEADER_DONE 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x8 6. "AURORA_TX_INTAGG_MASK_INT6,Mask Interrupt AURORA_TX_EOP_DONE 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x8 5. "AURORA_TX_INTAGG_MASK_INT5,Mask Interrupt DATA_STOP_DONE 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x8 4. "AURORA_TX_INTAGG_MASK_INT4,Mask Interrupt AURORA_TX_CC_DONE 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x8 3. "AURORA_TX_INTAGG_MASK_INT3,Mask Interrupt AURORA_TX_UFC_SENT 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x8 2. "AURORA_TX_INTAGG_MASK_INT2,Mask Interrupt AURORA_TX_EXT_FLUSH_DONE 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x8 1. "AURORA_TX_INTAGG_MASK_INT1,Mask Interrupt AURORA_TX_FLUSH_DONE 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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bitfld.long 0x8 0. "AURORA_TX_INTAGG_MASK_INT0,Mask Interrupt AURORA_TX_INIT_DONE 1 : Interrupt is Masked 0 : Interrupt is Unmasked" "0: Interrupt is Unmasked,1: Interrupt is Masked"
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line.long 0xC "AURORA_TX_INTAGG_STATUS,"
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bitfld.long 0xC 15. "AURORA_TX_INTAGG_STATUS_INT15,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 15" "0,1"
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bitfld.long 0xC 14. "AURORA_TX_INTAGG_STATUS_INT14,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 14" "0,1"
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bitfld.long 0xC 13. "AURORA_TX_INTAGG_STATUS_INT13,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 13" "0,1"
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bitfld.long 0xC 12. "AURORA_TX_INTAGG_STATUS_INT12,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 12" "0,1"
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bitfld.long 0xC 11. "AURORA_TX_INTAGG_STATUS_INT11,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 11" "0,1"
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bitfld.long 0xC 10. "AURORA_TX_INTAGG_STATUS_INT10,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 10" "0,1"
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bitfld.long 0xC 9. "AURORA_TX_INTAGG_STATUS_INT9,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 9" "0,1"
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bitfld.long 0xC 8. "AURORA_TX_INTAGG_STATUS_INT8,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of Event 8" "0,1"
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bitfld.long 0xC 7. "AURORA_TX_INTAGG_STATUS_INT7,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of AURORA_TX_HEADER_DONE." "0,1"
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bitfld.long 0xC 6. "AURORA_TX_INTAGG_STATUS_INT6,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of AURORA_TX_EOP_DONE." "0,1"
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bitfld.long 0xC 5. "AURORA_TX_INTAGG_STATUS_INT5,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of DATA_STOP_DONE." "0,1"
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bitfld.long 0xC 4. "AURORA_TX_INTAGG_STATUS_INT4,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of AURORA_TX_CC_DONE" "0,1"
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bitfld.long 0xC 3. "AURORA_TX_INTAGG_STATUS_INT3,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of AURORA_TX_UFC_SENT." "0,1"
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bitfld.long 0xC 2. "AURORA_TX_INTAGG_STATUS_INT2,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of AURORA_TX_EXT_FLUSH_DONE" "0,1"
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bitfld.long 0xC 1. "AURORA_TX_INTAGG_STATUS_INT1,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of AURORA_TX_FLUSH_DONE" "0,1"
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bitfld.long 0xC 0. "AURORA_TX_INTAGG_STATUS_INT0,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This field indicates assertion of AURORA_TX_INIT_DONE" "0,1"
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line.long 0x10 "AURORA_TX_INTAGG_STATUS_RAW,"
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bitfld.long 0x10 15. "AURORA_TX_INTAGG_STATUS_RAW_INT15,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 14. "AURORA_TX_INTAGG_STATUS_RAW_INT14,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 13. "AURORA_TX_INTAGG_STATUS_RAW_INT13,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 12. "AURORA_TX_INTAGG_STATUS_RAW_INT12,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 11. "AURORA_TX_INTAGG_STATUS_RAW_INT11,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 10. "AURORA_TX_INTAGG_STATUS_RAW_INT10,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 9. "AURORA_TX_INTAGG_STATUS_RAW_INT9,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion of.." "0,1"
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bitfld.long 0x10 8. "AURORA_TX_INTAGG_STATUS_RAW_INT8,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion of.." "0,1"
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bitfld.long 0x10 7. "AURORA_TX_INTAGG_STATUS_RAW_INT7,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 6. "AURORA_TX_INTAGG_STATUS_RAW_INT6,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 5. "AURORA_TX_INTAGG_STATUS_RAW_INT5,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion of.." "0,1"
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bitfld.long 0x10 4. "AURORA_TX_INTAGG_STATUS_RAW_INT4,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 3. "AURORA_TX_INTAGG_STATUS_RAW_INT3,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion.." "0,1"
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bitfld.long 0x10 2. "AURORA_TX_INTAGG_STATUS_RAW_INT2,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion of.." "0,1"
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bitfld.long 0x10 1. "AURORA_TX_INTAGG_STATUS_RAW_INT1,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion of.." "0,1"
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bitfld.long 0x10 0. "AURORA_TX_INTAGG_STATUS_RAW_INT0,Read of 0x1 indicates a rising edge was detected on the corresponding event line . This is the raw status that will be asserted even if the event has been masked in AURORA_TX_INTAGG_MASK. This field indicates assertion of.." "0,1"
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line.long 0x14 "AURORA_TX_ERRAGG_MASK,"
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bitfld.long 0x14 15. "AURORA_TX_ERRAGG_MASK_ERR15,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 15" "0,1"
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bitfld.long 0x14 14. "AURORA_TX_ERRAGG_MASK_ERR14,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 14" "0,1"
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bitfld.long 0x14 13. "AURORA_TX_ERRAGG_MASK_ERR13,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 13" "0,1"
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bitfld.long 0x14 12. "AURORA_TX_ERRAGG_MASK_ERR12,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 12" "0,1"
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bitfld.long 0x14 11. "AURORA_TX_ERRAGG_MASK_ERR11,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 11" "0,1"
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bitfld.long 0x14 10. "AURORA_TX_ERRAGG_MASK_ERR10,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 10" "0,1"
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bitfld.long 0x14 9. "AURORA_TX_ERRAGG_MASK_ERR9,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 9" "0,1"
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bitfld.long 0x14 8. "AURORA_TX_ERRAGG_MASK_ERR8,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 8" "0,1"
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bitfld.long 0x14 7. "AURORA_TX_ERRAGG_MASK_ERR7,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 7" "0,1"
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bitfld.long 0x14 6. "AURORA_TX_ERRAGG_MASK_ERR6,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 6" "0,1"
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bitfld.long 0x14 5. "AURORA_TX_ERRAGG_MASK_ERR5,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 5" "0,1"
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bitfld.long 0x14 4. "AURORA_TX_ERRAGG_MASK_ERR4,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 4" "0,1"
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bitfld.long 0x14 3. "AURORA_TX_ERRAGG_MASK_ERR3,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 3" "0,1"
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bitfld.long 0x14 2. "AURORA_TX_ERRAGG_MASK_ERR2,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 2" "0,1"
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bitfld.long 0x14 1. "AURORA_TX_ERRAGG_MASK_ERR1,Mask the the corresponding Error event line from generating an Interrupt. This field masks the interrupt from Error event 1" "0,1"
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bitfld.long 0x14 0. "AURORA_TX_ERRAGG_MASK_ERR0,Mask error AURORA_TX_UFC_ERR 1 : Error is Masked 0 : Error is Unmasked" "0: Error is Unmasked,1: Error is Masked"
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line.long 0x18 "AURORA_TX_ERRAGG_STATUS,"
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bitfld.long 0x18 15. "AURORA_TX_ERRAGG_STATUS_ERR1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 15" "0,1"
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bitfld.long 0x18 14. "AURORA_TX_ERRAGG_STATUS_ERR1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 14" "0,1"
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bitfld.long 0x18 13. "AURORA_TX_ERRAGG_STATUS_ERR1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 13" "0,1"
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bitfld.long 0x18 12. "AURORA_TX_ERRAGG_STATUS_ERR1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 12" "0,1"
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bitfld.long 0x18 11. "AURORA_TX_ERRAGG_STATUS_ERR1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 11" "0,1"
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bitfld.long 0x18 10. "AURORA_TX_ERRAGG_STATUS_ERR1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 10" "0,1"
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bitfld.long 0x18 9. "AURORA_TX_ERRAGG_STATUS_ERR9 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 9" "0,1"
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bitfld.long 0x18 8. "AURORA_TX_ERRAGG_STATUS_ERR8 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 8" "0,1"
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bitfld.long 0x18 7. "AURORA_TX_ERRAGG_STATUS_ERR7 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 7" "0,1"
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bitfld.long 0x18 6. "AURORA_TX_ERRAGG_STATUS_ERR6 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 6" "0,1"
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bitfld.long 0x18 5. "AURORA_TX_ERRAGG_STATUS_ERR5 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 5" "0,1"
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bitfld.long 0x18 4. "AURORA_TX_ERRAGG_STATUS_ERR4 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 4" "0,1"
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bitfld.long 0x18 3. "AURORA_TX_ERRAGG_STATUS_ERR3 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 3" "0,1"
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bitfld.long 0x18 2. "AURORA_TX_ERRAGG_STATUS_ERR2 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 2" "0,1"
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bitfld.long 0x18 1. "AURORA_TX_ERRAGG_STATUS_ERR1 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error event 1" "0,1"
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bitfld.long 0x18 0. "AURORA_TX_ERRAGG_STATUS_ERR0 RW,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This field indicates assertion of Error AURORA_TX_UFC_ERR" "0,1"
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line.long 0x1C "AURORA_TX_ERRAGG_STATUS_RAW,"
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bitfld.long 0x1C 15. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
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bitfld.long 0x1C 14. "RR15,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error event 14" "0,1"
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bitfld.long 0x1C 13. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
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bitfld.long 0x1C 12. "RR14,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error event 12" "0,1"
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bitfld.long 0x1C 11. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
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bitfld.long 0x1C 10. "RR13,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error event 10" "0,1"
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bitfld.long 0x1C 9. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
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newline
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bitfld.long 0x1C 8. "RR12,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error event 8" "0,1"
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bitfld.long 0x1C 7. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
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bitfld.long 0x1C 6. "RR11,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error event 6" "0,1"
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bitfld.long 0x1C 5. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
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newline
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bitfld.long 0x1C 4. "RR10,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error event 4" "0,1"
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newline
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bitfld.long 0x1C 3. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
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newline
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bitfld.long 0x1C 2. "RR9,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error event 2" "0,1"
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newline
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bitfld.long 0x1C 1. "AURORA_TX_ERRAGG_STATUS_RAW_E,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates.." "0,1"
|
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newline
|
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bitfld.long 0x1C 0. "RR8,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line . This is the raw status that will be asseter even if the Error event has been masked in AURORA_TX_ERRAGG_MASK. This field indicates assertion of Error.." "0,1"
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rgroup.long 0x228++0xB
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line.long 0x0 "AURORA_TX_SERIALIZER_STATUS0,"
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hexmask.long 0x0 0.--31. 1. "AURORA_TX_SERIALIZER_STATUS0_,Status of the serializer. For debug purposes only"
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line.long 0x4 "AURORA_TX_SERIALIZER_STATUS1,"
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hexmask.long 0x4 0.--31. 1. "AURORA_TX_SERIALIZER_STATUS1_,Status of the serializer. For debug purposes only"
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line.long 0x8 "AURORA_TX_TPIU_DATA_PACKED,"
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hexmask.long 0x8 0.--31. 1. "AURORA_TX_TPIU_DATA_PACKED_B,Number of input tpiu bytes packed in the current aurora frame"
|
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group.long 0xFD0++0xF
|
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line.long 0x0 "HW_SPARE_RW0,"
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hexmask.long 0x0 0.--31. 1. "HW_SPARE_RW0_HW_SPARE_RW,Reserved for HW R&D"
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line.long 0x4 "HW_SPARE_RW1,"
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hexmask.long 0x4 0.--31. 1. "HW_SPARE_RW1_HW_SPARE_RW,Reserved for HW R&D"
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line.long 0x8 "HW_SPARE_RW2,"
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hexmask.long 0x8 0.--31. 1. "HW_SPARE_RW2_HW_SPARE_RW,Reserved for HW R&D"
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line.long 0xC "HW_SPARE_RW3,"
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hexmask.long 0xC 0.--31. 1. "HW_SPARE_RW3_HW_SPARE_RW,Reserved for HW R&D"
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rgroup.long 0xFE0++0x7
|
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line.long 0x0 "HW_SPARE_RO0,"
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hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO1_HW_SPARE_RO0,Reserved for HW R&D"
|
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line.long 0x4 "HW_SPARE_RO1,"
|
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hexmask.long 0x4 0.--31. 1. "HW_SPARE_RO2_HW_SPARE_RO1,Reserved for HW R&D"
|
|
repeat 2. (list 0x2 0x3)(list 0x0 0x4)
|
|
rgroup.long ($2+0xFE8)++0x3
|
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line.long 0x0 "HW_SPARE_RO$1,"
|
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hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO3_HW_SPARE_RO2,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "HW_SPARE_WPH_HW_SPARE_WP,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
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bitfld.long 0x4 31. "HW_SPARE_REC_HW_SPARE_REC31,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "HW_SPARE_REC_HW_SPARE_REC30,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "HW_SPARE_REC_HW_SPARE_REC29,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 28. "HW_SPARE_REC_HW_SPARE_REC28,Reserved for HW R&D" "0,1"
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newline
|
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bitfld.long 0x4 27. "HW_SPARE_REC_HW_SPARE_REC27,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 26. "HW_SPARE_REC_HW_SPARE_REC26,Reserved for HW R&D" "0,1"
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|
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bitfld.long 0x4 25. "HW_SPARE_REC_HW_SPARE_REC25,Reserved for HW R&D" "0,1"
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|
newline
|
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bitfld.long 0x4 24. "HW_SPARE_REC_HW_SPARE_REC24,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 23. "HW_SPARE_REC_HW_SPARE_REC23,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 22. "HW_SPARE_REC_HW_SPARE_REC22,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 21. "HW_SPARE_REC_HW_SPARE_REC21,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 20. "HW_SPARE_REC_HW_SPARE_REC20,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 19. "HW_SPARE_REC_HW_SPARE_REC19,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 18. "HW_SPARE_REC_HW_SPARE_REC18,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 17. "HW_SPARE_REC_HW_SPARE_REC17,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 16. "HW_SPARE_REC_HW_SPARE_REC16,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 15. "HW_SPARE_REC_HW_SPARE_REC15,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 14. "HW_SPARE_REC_HW_SPARE_REC14,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 13. "HW_SPARE_REC_HW_SPARE_REC13,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 12. "HW_SPARE_REC_HW_SPARE_REC12,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "HW_SPARE_REC_HW_SPARE_REC11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "HW_SPARE_REC_HW_SPARE_REC10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "HW_SPARE_REC_HW_SPARE_REC9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "HW_SPARE_REC_HW_SPARE_REC8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "HW_SPARE_REC_HW_SPARE_REC7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "HW_SPARE_REC_HW_SPARE_REC6,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 5. "HW_SPARE_REC_HW_SPARE_REC5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "HW_SPARE_REC_HW_SPARE_REC4,Reserved for HW R&D" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "HW_SPARE_REC_HW_SPARE_REC3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "HW_SPARE_REC_HW_SPARE_REC2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HW_SPARE_REC_HW_SPARE_REC1,Reserved for HW R&D" "0,1"
|
|
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|
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bitfld.long 0x4 0. "HW_SPARE_REC_HW_SPARE_REC0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "FAULT_NS,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "FAULT_XID,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "FAULT_ROUTEID,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "FAULT_PRIVID,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "TOP_CTRL"
|
|
base ad:0x30E0000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "MDO_CTRL,"
|
|
bitfld.long 0x0 4.--5. "SRC_SELECT,Select the source IP of LVDS Data 0: Aurora full data on LVDS 1: CBUFF on LVDS 2: Aurora bit-clk frame clk and 2 data support. 3: Aurora 1bit clk and 2 data support for LOP package" "0: Aurora full data on LVDS 1: CBUFF on LVDS,?,2: Aurora bit-clk,3: Aurora 1bit clk and 2 data support for LOP package"
|
|
newline
|
|
bitfld.long 0x0 0. "AURORATX_SRC_SELECT,Select the TPIU source to TOP_AURORATX IP 0:Measurement Data 1: Trace Data" "0: Measurement Data,1: Trace Data"
|
|
line.long 0x4 "PROBE_BUS_SEL0,"
|
|
hexmask.long 0x4 0.--31. 1. "sel,Probe Bus 0 Mux Select"
|
|
line.long 0x8 "PROBE_BUS_SEL1,"
|
|
hexmask.long 0x8 0.--31. 1. "sel,Probe Bus 1 Mux Select"
|
|
line.long 0xC "RS232_SLEEP_CLK_DIV,"
|
|
hexmask.long 0xC 0.--31. 1. "div_val,The Divider value for RS232 sleep clock generation from RCclk"
|
|
line.long 0x10 "RS232_SLEEP_CLK_DIV_by2,"
|
|
hexmask.long 0x10 0.--31. 1. "div_val,The Dividerby2 value for RS232 sleep clock generation from RCclk. This decides the duty cycle of sleep clock."
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0x200)++0x3
|
|
line.long 0x0 "EFUSE_DIEID$1,"
|
|
hexmask.long 0x0 0.--31. 1. "val,EFUSE DieID[31:0]"
|
|
repeat.end
|
|
repeat 3. (list 0x0 0x1 0x2)(list 0x0 0x4 0x8)
|
|
rgroup.long ($2+0x210)++0x3
|
|
line.long 0x0 "EFUSE_UID$1,"
|
|
hexmask.long 0x0 0.--31. 1. "val,EFUSE UID[31:0]"
|
|
repeat.end
|
|
rgroup.long 0x21C++0xB
|
|
line.long 0x0 "EFUSE_UID3,"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "val,EFUSE UID[120:96]"
|
|
line.long 0x4 "PREVIOUS_NAME,"
|
|
hexmask.long.word 0x4 0.--15. 1. "val,EFUSE Device Type"
|
|
line.long 0x8 "EFUSE_FROM0_CHECKSUM,"
|
|
hexmask.long 0x8 0.--31. 1. "val,32 bit FROM0 Checksum"
|
|
repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20)
|
|
rgroup.long ($2+0x228)++0x3
|
|
line.long 0x0 "EFUSE_ROM_SEQ_UPDATE$1,"
|
|
hexmask.long 0x0 0.--31. 1. "val,EFUSE ROM Seq Update [31:0]"
|
|
repeat.end
|
|
repeat 3. (list 0x3D 0x3E 0x3F)(list 0x0 0x4 0x8)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "EFUSE0_ROW_$1,"
|
|
hexmask.long 0x0 0.--25. 1. "EFUSE0_ROW_61,Captures the EFUSE Value. Refer to EFUSE Mapping XLS for more details"
|
|
repeat.end
|
|
repeat 16. (list 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13 0x14)(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C)
|
|
rgroup.long ($2+0x40C)++0x3
|
|
line.long 0x0 "EFUSE1_ROW_$1,"
|
|
hexmask.long 0x0 0.--25. 1. "EFUSE1_ROW_5,Captures the EFUSE Value. Refer to EFUSE Mapping XLS for more details"
|
|
repeat.end
|
|
repeat 16. (list 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24)(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C)
|
|
rgroup.long ($2+0x40C)++0x3
|
|
line.long 0x0 "EFUSE1_ROW_$1,"
|
|
hexmask.long 0x0 0.--25. 1. "EFUSE1_ROW_5,Captures the EFUSE Value. Refer to EFUSE Mapping XLS for more details"
|
|
repeat.end
|
|
repeat 7. (list 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B)(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98)
|
|
rgroup.long ($2+0x40C)++0x3
|
|
line.long 0x0 "EFUSE1_ROW_$1,"
|
|
hexmask.long 0x0 0.--25. 1. "EFUSE1_ROW_5,Captures the EFUSE Value. Refer to EFUSE Mapping XLS for more details"
|
|
repeat.end
|
|
group.long 0x800++0x53
|
|
line.long 0x0 "EFUSE_OVERRIDE_HSM_HALT_ON_ROM_ECC_ERR_EN,"
|
|
bitfld.long 0x0 4. "override_val,Override MMR value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x4 "EFUSE_OVERRIDE_MEM_MARGINCTRL,"
|
|
bitfld.long 0x4 28.--29. "brg_margin,Override MMR value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "brg_margin_override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "byg_margin,Override MMR value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "byg_margin_override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "gwg_margin,Override MMR value"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "gwg_margin_override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "glg_margin,Override MMR value" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "glg_margin_override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x8 "EFUSE_OVERRIDE_LVDS_BGAP_TRIM,"
|
|
hexmask.long.byte 0x8 4.--9. 1. "override_val,Override MMR value"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0xC "EFUSE_OVERRIDE_XTAL_STABLIZATION_WAIT,"
|
|
bitfld.long 0xC 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value . Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x10 "EFUSE_OVERRIDE_SLICER_BIAS_RTRIM,"
|
|
bitfld.long 0x10 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value . Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x14 "EFUSE_OVERRIDE_XO_OUTPUT_DRIVE,"
|
|
bitfld.long 0x14 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value . Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x18 "EFUSE_OVERRIDE_RCOSC_TRIM_CODE,"
|
|
bitfld.long 0x18 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value . Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x1C "EFUSE_OVERRIDE_IP1_BG1_RTRIM,"
|
|
bitfld.long 0x1C 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x20 "EFUSE_OVERRIDE_IP1_BG1_SLOPE,"
|
|
bitfld.long 0x20 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x24 "EFUSE_OVERRIDE_IP1_BG1_MAG,"
|
|
bitfld.long 0x24 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x28 "EFUSE_OVERRIDE_RS232_CLKMODE,"
|
|
bitfld.long 0x28 4. "override_val,Override value for RS232 Clock Mode 0 : Autobaud 1 : Fixed Interval" "0: Autobaud,1: Fixed Interval"
|
|
newline
|
|
bitfld.long 0x28 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value." "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x2C "EFUSE_OVERRIDE_VMON_VDD_OV_UV_TRIM,"
|
|
bitfld.long 0x2C 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x30 "EFUSE_OVERRIDE_VMON_VDDS_3P3_UV_TRIM,"
|
|
bitfld.long 0x30 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x34 "EFUSE_OVERRIDE_VMON_VDDA_OSC_TRIM,"
|
|
bitfld.long 0x34 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x38 "EFUSE_OVERRIDE_VDD_VT_DET,"
|
|
bitfld.long 0x38 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x3C "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_VAL,"
|
|
bitfld.long 0x3C 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x40 "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_SEL,"
|
|
bitfld.long 0x40 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x44 "EFUSE_OVERRIDE_EN_VOL_MON_FUNC,"
|
|
bitfld.long 0x44 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x48 "EFUSE_OVERRIDE_EN_VOL_MON_FUNC,"
|
|
bitfld.long 0x48 4. "override_val,Override value for Hold Buffer Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x48 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value." "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x4C "EFUSE_OVERRIDE_SPARE_ANA,"
|
|
bitfld.long 0x4C 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
line.long 0x50 "EFUSE_OVERRIDE_SLICER_DLY_DISABLE,"
|
|
bitfld.long 0x50 0.--2. "override,Override EFUSE Value with SW Value Write 3'b000 : EFUSE Value Write 3'b111 : MMR Value. Refer to the ANAREG in TOP_RCM for the override value" "0: EFUSE Value Write 3'b111 : MMR Value,?,?,?,?,?,?,?"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_rw0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_ro0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "hw_spare_wph,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_kick0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_kick1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "TOP_MDO_INFRA"
|
|
base ad:0x3080000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "PID,PID register"
|
|
hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PID_CUSTOM," "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "HW_REG$1,"
|
|
hexmask.long 0x0 0.--31. 1. "HWREG,HW Reserved regiser"
|
|
repeat.end
|
|
group.long 0x14++0x14F
|
|
line.long 0x0 "SRC0_CTRL,"
|
|
bitfld.long 0x0 20. "GEN_MARKER_ON_FLUSH,Write 0x1 to generate a marker on Flush trigger" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "RANGE_EN,Enable the corresponding range for data capture. Bit 0 : 0: Range 0 is disabled 1 : Range 0 is enableld"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "HW_FLUSH_EN,Write 0x1 to enable HW Marker trigger to generate a Flush"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HW_MARKER_EN,Write 0x1 to enable HW Marker trigger to generate a Marker"
|
|
newline
|
|
bitfld.long 0x0 2. "CROP_EN,Chop of the sign extension bits [15:12] for every 16 bits of data. 0 : Send all 16 bits 1 : Send lower 12 of 16 bits" "0: Send all 16 bits,1: Send lower 12 of 16 bits"
|
|
newline
|
|
bitfld.long 0x0 1. "SNIF_MODE,Select which bus to capture. 0 : Read Bus 1 : Write Bus" "0: Read Bus,1: Write Bus"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,Indicates is the sniffer block is active or inactive. 0 : Captuere is Disabled 1 : Sniffer Enabled" "0: Captuere is Disabled,1: Sniffer Enabled"
|
|
line.long 0x4 "SRC0_RANGE_START0,"
|
|
hexmask.long 0x4 0.--31. 1. "START,Range 0 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x8 "SRC0_RANGE_END0,"
|
|
hexmask.long 0x8 0.--31. 1. "END,Range 0 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xC "SRC0_RANGE_START1,"
|
|
hexmask.long 0xC 0.--31. 1. "START,Range 1 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x10 "SRC0_RANGE_END1,"
|
|
hexmask.long 0x10 0.--31. 1. "END,Range 1 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x14 "SRC0_RANGE_START2,"
|
|
hexmask.long 0x14 0.--31. 1. "START,Range 2 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x18 "SRC0_RANGE_END2,"
|
|
hexmask.long 0x18 0.--31. 1. "END,Range 2 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x1C "SRC0_RANGE_START3,"
|
|
hexmask.long 0x1C 0.--31. 1. "START,Range 3 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x20 "SRC0_RANGE_END3,"
|
|
hexmask.long 0x20 0.--31. 1. "END,Range 3 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x24 "SRC0_SW_TRIGGER,"
|
|
bitfld.long 0x24 4. "FLUSH,Write 0x1 to trigger a Flush. A marker packet will also be inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "MARKER,Write 0x1 to insert a Marker" "0,1"
|
|
line.long 0x28 "SRC0_THRESHOLD,"
|
|
hexmask.long.word 0x28 0.--9. 1. "THRESHOLD,The FIFO threshold to trigger writes from the Source FIFO. This value is in multiples of 32 bytes. If SRCx_BW_CTRL_WRITE_MODE is 0x0 then the bits [9:5] of this field need to be programmed to 0x0"
|
|
line.long 0x2C "SRC0_BW_CTRL,"
|
|
bitfld.long 0x2C 28.--30. "PRIORITY,0 : Highest Dynamic Priority 7 : Lowest Dynamic Priority" "0: Highest Dynamic Priority,?,?,?,?,?,?,7: Lowest Dynamic Priority"
|
|
newline
|
|
hexmask.long.byte 0x2C 16.--20. 1. "BURST_SIZE,The burst_size is the minimum size for which the SRC will keep arbitration once it wins . The value in multiples of 32 bytes"
|
|
newline
|
|
hexmask.long.byte 0x2C 4.--11. 1. "BURST_NUM,The FIFO threshold to trigger writes from the Source FIFO. Value to be aligned to 32 bytes [4:0] should be 0x0"
|
|
newline
|
|
bitfld.long 0x2C 0. "WRITE_MODE,0 : Send data equivalent to burst_count * burst_size 1 : Send data equivalent to threshold size. This can be set only if threshold is less than 1024 bytes" "0: Send data equivalent to burst_count * burst_size,1: Send data equivalent to threshold size"
|
|
line.long 0x30 "SRC0_CHANNEL,"
|
|
hexmask.long 0x30 0.--31. 1. "ADDR,Configure the STM Channel Number"
|
|
line.long 0x34 "SRC0_CHANNEL_CFG,"
|
|
bitfld.long 0x34 4. "NONDATA_TIMESTAMPE,Selects whether the Non Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x34 3. "NONDATA_GUARANTEE,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
newline
|
|
bitfld.long 0x34 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x34 1. "DATA_MARKED,Selects whether the Data access for the Source is marked 0 : Un-Marked 1 : Marked" "0: Un-Marked,1: Marked"
|
|
newline
|
|
bitfld.long 0x34 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
line.long 0x38 "SRC1_CTRL,"
|
|
bitfld.long 0x38 20. "GEN_MARKER_ON_FLUSH,Write 0x1 to generate a marker on Flush trigger" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x38 16.--19. 1. "RANGE_EN,Enable the corresponding range for data capture. Bit 0 : 0: Range 0 is disabled 1 : Range 0 is enableld"
|
|
newline
|
|
hexmask.long.byte 0x38 12.--15. 1. "HW_FLUSH_EN,Write 0x1 to enable HW Marker trigger to generate a Flush"
|
|
newline
|
|
hexmask.long.byte 0x38 8.--11. 1. "HW_MARKER_EN,Write 0x1 to enable HW Marker trigger to generate a Marker"
|
|
newline
|
|
bitfld.long 0x38 2. "CROP_EN,Chop of the sign extension bits [15:12] for every 16 bits of data. 0 : Send all 16 bits 1 : Send lower 12 of 16 bits" "0: Send all 16 bits,1: Send lower 12 of 16 bits"
|
|
newline
|
|
bitfld.long 0x38 1. "SNIF_MODE,Select which bus to capture. 0 : Read Bus 1 : Write Bus" "0: Read Bus,1: Write Bus"
|
|
newline
|
|
bitfld.long 0x38 0. "ENABLE,Indicates is the sniffer block is active or inactive. 0 : Captuere is Disabled 1 : Sniffer Enabled" "0: Captuere is Disabled,1: Sniffer Enabled"
|
|
line.long 0x3C "SRC1_RANGE_START0,"
|
|
hexmask.long 0x3C 0.--31. 1. "START,Range 0 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x40 "SRC1_RANGE_END0,"
|
|
hexmask.long 0x40 0.--31. 1. "END,Range 0 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x44 "SRC1_RANGE_START1,"
|
|
hexmask.long 0x44 0.--31. 1. "START,Range 1 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x48 "SRC1_RANGE_END1,"
|
|
hexmask.long 0x48 0.--31. 1. "END,Range 1 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x4C "SRC1_RANGE_START2,"
|
|
hexmask.long 0x4C 0.--31. 1. "START,Range 2 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x50 "SRC1_RANGE_END2,"
|
|
hexmask.long 0x50 0.--31. 1. "END,Range 2 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x54 "SRC1_RANGE_START3,"
|
|
hexmask.long 0x54 0.--31. 1. "START,Range 3 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x58 "SRC1_RANGE_END3,"
|
|
hexmask.long 0x58 0.--31. 1. "END,Range 3 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x5C "SRC1_SW_TRIGGER,"
|
|
bitfld.long 0x5C 4. "FLUSH,Write 0x1 to trigger a Flush. A marker packet will also be inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x5C 0. "MARKER,Write 0x1 to insert a Marker" "0,1"
|
|
line.long 0x60 "SRC1_THRESHOLD,"
|
|
hexmask.long.word 0x60 0.--9. 1. "THRESHOLD,The FIFO threshold to trigger writes from the Source FIFO. This value is in multiples of 32 bytes. If SRCx_BW_CTRL_WRITE_MODE is 0x0 then the bits [9:5] of this field need to be programmed to 0x0"
|
|
line.long 0x64 "SRC1_BW_CTRL,"
|
|
bitfld.long 0x64 28.--30. "PRIORITY,0 : Highest Dynamic Priority 7 : Lowest Dynamic Priority" "0: Highest Dynamic Priority,?,?,?,?,?,?,7: Lowest Dynamic Priority"
|
|
newline
|
|
hexmask.long.byte 0x64 16.--20. 1. "BURST_SIZE,The burst_size is the minimum size for which the SRC will keep arbitration once it wins . The value in multiples of 32 bytes"
|
|
newline
|
|
hexmask.long.byte 0x64 4.--11. 1. "BURST_NUM,The FIFO threshold to trigger writes from the Source FIFO. Value to be aligned to 32 bytes [4:0] should be 0x0"
|
|
newline
|
|
bitfld.long 0x64 0. "WRITE_MODE,0 : Send data equivalent to burst_count * burst_size 1 : Send data equivalent to threshold size. This can be set only if threshold is less than 1024 bytes" "0: Send data equivalent to burst_count * burst_size,1: Send data equivalent to threshold size"
|
|
line.long 0x68 "SRC1_CHANNEL,"
|
|
hexmask.long 0x68 0.--31. 1. "ADDR,Configure the STM Channel Number"
|
|
line.long 0x6C "SRC1_CHANNEL_CFG,"
|
|
bitfld.long 0x6C 4. "NONDATA_TIMESTAMPE,Selects whether the Non Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x6C 3. "NONDATA_GUARANTEE,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
newline
|
|
bitfld.long 0x6C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x6C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked 0 : Un-Marked 1 : Marked" "0: Un-Marked,1: Marked"
|
|
newline
|
|
bitfld.long 0x6C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
line.long 0x70 "SRC2_CTRL,"
|
|
bitfld.long 0x70 20. "GEN_MARKER_ON_FLUSH,Write 0x1 to generate a marker on Flush trigger" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x70 16.--19. 1. "RANGE_EN,Enable the corresponding range for data capture. Bit 0 : 0: Range 0 is disabled 1 : Range 0 is enableld"
|
|
newline
|
|
hexmask.long.byte 0x70 12.--15. 1. "HW_FLUSH_EN,Write 0x1 to enable HW Marker trigger to generate a Flush"
|
|
newline
|
|
hexmask.long.byte 0x70 8.--11. 1. "HW_MARKER_EN,Write 0x1 to enable HW Marker trigger to generate a Marker"
|
|
newline
|
|
bitfld.long 0x70 2. "CROP_EN,Chop of the sign extension bits [15:12] for every 16 bits of data. 0 : Send all 16 bits 1 : Send lower 12 of 16 bits" "0: Send all 16 bits,1: Send lower 12 of 16 bits"
|
|
newline
|
|
bitfld.long 0x70 1. "SNIF_MODE,Select which bus to capture. 0 : Read Bus 1 : Write Bus" "0: Read Bus,1: Write Bus"
|
|
newline
|
|
bitfld.long 0x70 0. "ENABLE,Indicates is the sniffer block is active or inactive. 0 : Captuere is Disabled 1 : Sniffer Enabled" "0: Captuere is Disabled,1: Sniffer Enabled"
|
|
line.long 0x74 "SRC2_RANGE_START0,"
|
|
hexmask.long 0x74 0.--31. 1. "START,Range 0 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x78 "SRC2_RANGE_END0,"
|
|
hexmask.long 0x78 0.--31. 1. "END,Range 0 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x7C "SRC2_RANGE_START1,"
|
|
hexmask.long 0x7C 0.--31. 1. "START,Range 1 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x80 "SRC2_RANGE_END1,"
|
|
hexmask.long 0x80 0.--31. 1. "END,Range 1 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x84 "SRC2_RANGE_START2,"
|
|
hexmask.long 0x84 0.--31. 1. "START,Range 2 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x88 "SRC2_RANGE_END2,"
|
|
hexmask.long 0x88 0.--31. 1. "END,Range 2 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x8C "SRC2_RANGE_START3,"
|
|
hexmask.long 0x8C 0.--31. 1. "START,Range 3 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x90 "SRC2_RANGE_END3,"
|
|
hexmask.long 0x90 0.--31. 1. "END,Range 3 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x94 "SRC2_SW_TRIGGER,"
|
|
bitfld.long 0x94 4. "FLUSH,Write 0x1 to trigger a Flush. A marker packet will also be inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x94 0. "MARKER,Write 0x1 to insert a Marker" "0,1"
|
|
line.long 0x98 "SRC2_THRESHOLD,"
|
|
hexmask.long.word 0x98 0.--9. 1. "THRESHOLD,The FIFO threshold to trigger writes from the Source FIFO. This value is in multiples of 32 bytes. If SRCx_BW_CTRL_WRITE_MODE is 0x0 then the bits [9:5] of this field need to be programmed to 0x0"
|
|
line.long 0x9C "SRC2_BW_CTRL,"
|
|
bitfld.long 0x9C 28.--30. "PRIORITY,0 : Highest Dynamic Priority 7 : Lowest Dynamic Priority" "0: Highest Dynamic Priority,?,?,?,?,?,?,7: Lowest Dynamic Priority"
|
|
newline
|
|
hexmask.long.byte 0x9C 16.--20. 1. "BURST_SIZE,The burst_size is the minimum size for which the SRC will keep arbitration once it wins . The value in multiples of 32 bytes"
|
|
newline
|
|
hexmask.long.byte 0x9C 4.--11. 1. "BURST_NUM,The FIFO threshold to trigger writes from the Source FIFO. Value to be aligned to 32 bytes [4:0] should be 0x0"
|
|
newline
|
|
bitfld.long 0x9C 0. "WRITE_MODE,0 : Send data equivalent to burst_count * burst_size 1 : Send data equivalent to threshold size. This can be set only if threshold is less than 1024 bytes" "0: Send data equivalent to burst_count * burst_size,1: Send data equivalent to threshold size"
|
|
line.long 0xA0 "SRC2_CHANNEL,"
|
|
hexmask.long 0xA0 0.--31. 1. "ADDR,Configure the STM Channel Number"
|
|
line.long 0xA4 "SRC2_CHANNEL_CFG,"
|
|
bitfld.long 0xA4 4. "NONDATA_TIMESTAMPE,Selects whether the Non Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0xA4 3. "NONDATA_GUARANTEE,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
newline
|
|
bitfld.long 0xA4 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0xA4 1. "DATA_MARKED,Selects whether the Data access for the Source is marked 0 : Un-Marked 1 : Marked" "0: Un-Marked,1: Marked"
|
|
newline
|
|
bitfld.long 0xA4 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
line.long 0xA8 "SRC3_CTRL,"
|
|
bitfld.long 0xA8 20. "GEN_MARKER_ON_FLUSH,Write 0x1 to generate a marker on Flush trigger" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xA8 16.--19. 1. "RANGE_EN,Enable the corresponding range for data capture. Bit 0 : 0: Range 0 is disabled 1 : Range 0 is enableld"
|
|
newline
|
|
hexmask.long.byte 0xA8 12.--15. 1. "HW_FLUSH_EN,Write 0x1 to enable HW Marker trigger to generate a Flush"
|
|
newline
|
|
hexmask.long.byte 0xA8 8.--11. 1. "HW_MARKER_EN,Write 0x1 to enable HW Marker trigger to generate a Marker"
|
|
newline
|
|
bitfld.long 0xA8 2. "CROP_EN,Chop of the sign extension bits [15:12] for every 16 bits of data. 0 : Send all 16 bits 1 : Send lower 12 of 16 bits" "0: Send all 16 bits,1: Send lower 12 of 16 bits"
|
|
newline
|
|
bitfld.long 0xA8 1. "SNIF_MODE,Select which bus to capture. 0 : Read Bus 1 : Write Bus" "0: Read Bus,1: Write Bus"
|
|
newline
|
|
bitfld.long 0xA8 0. "ENABLE,Indicates is the sniffer block is active or inactive. 0 : Captuere is Disabled 1 : Sniffer Enabled" "0: Captuere is Disabled,1: Sniffer Enabled"
|
|
line.long 0xAC "SRC3_RANGE_START0,"
|
|
hexmask.long 0xAC 0.--31. 1. "START,Range 0 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0xB0 "SRC3_RANGE_END0,"
|
|
hexmask.long 0xB0 0.--31. 1. "END,Range 0 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xB4 "SRC3_RANGE_START1,"
|
|
hexmask.long 0xB4 0.--31. 1. "START,Range 1 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0xB8 "SRC3_RANGE_END1,"
|
|
hexmask.long 0xB8 0.--31. 1. "END,Range 1 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xBC "SRC3_RANGE_START2,"
|
|
hexmask.long 0xBC 0.--31. 1. "START,Range 2 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0xC0 "SRC3_RANGE_END2,"
|
|
hexmask.long 0xC0 0.--31. 1. "END,Range 2 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xC4 "SRC3_RANGE_START3,"
|
|
hexmask.long 0xC4 0.--31. 1. "START,Range 3 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0xC8 "SRC3_RANGE_END3,"
|
|
hexmask.long 0xC8 0.--31. 1. "END,Range 3 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xCC "SRC3_SW_TRIGGER,"
|
|
bitfld.long 0xCC 4. "FLUSH,Write 0x1 to trigger a Flush. A marker packet will also be inserted" "0,1"
|
|
newline
|
|
bitfld.long 0xCC 0. "MARKER,Write 0x1 to insert a Marker" "0,1"
|
|
line.long 0xD0 "SRC3_THRESHOLD,"
|
|
hexmask.long.word 0xD0 0.--9. 1. "THRESHOLD,The FIFO threshold to trigger writes from the Source FIFO. This value is in multiples of 32 bytes. If SRCx_BW_CTRL_WRITE_MODE is 0x0 then the bits [9:5] of this field need to be programmed to 0x0"
|
|
line.long 0xD4 "SRC3_BW_CTRL,"
|
|
bitfld.long 0xD4 28.--30. "PRIORITY,0 : Highest Dynamic Priority 7 : Lowest Dynamic Priority" "0: Highest Dynamic Priority,?,?,?,?,?,?,7: Lowest Dynamic Priority"
|
|
newline
|
|
hexmask.long.byte 0xD4 16.--20. 1. "BURST_SIZE,The burst_size is the minimum size for which the SRC will keep arbitration once it wins . The value in multiples of 32 bytes"
|
|
newline
|
|
hexmask.long.byte 0xD4 4.--11. 1. "BURST_NUM,The FIFO threshold to trigger writes from the Source FIFO. Value to be aligned to 32 bytes [4:0] should be 0x0"
|
|
newline
|
|
bitfld.long 0xD4 0. "WRITE_MODE,0 : Send data equivalent to burst_count * burst_size 1 : Send data equivalent to threshold size. This can be set only if threshold is less than 1024 bytes" "0: Send data equivalent to burst_count * burst_size,1: Send data equivalent to threshold size"
|
|
line.long 0xD8 "SRC3_CHANNEL,"
|
|
hexmask.long 0xD8 0.--31. 1. "ADDR,Configure the STM Channel Number"
|
|
line.long 0xDC "SRC3_CHANNEL_CFG,"
|
|
bitfld.long 0xDC 4. "NONDATA_TIMESTAMPE,Selects whether the Non Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0xDC 3. "NONDATA_GUARANTEE,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
newline
|
|
bitfld.long 0xDC 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0xDC 1. "DATA_MARKED,Selects whether the Data access for the Source is marked 0 : Un-Marked 1 : Marked" "0: Un-Marked,1: Marked"
|
|
newline
|
|
bitfld.long 0xDC 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
line.long 0xE0 "SRC4_CTRL,"
|
|
bitfld.long 0xE0 20. "GEN_MARKER_ON_FLUSH,Write 0x1 to generate a marker on Flush trigger" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xE0 16.--19. 1. "RANGE_EN,Enable the corresponding range for data capture. Bit 0 : 0: Range 0 is disabled 1 : Range 0 is enableld"
|
|
newline
|
|
hexmask.long.byte 0xE0 12.--15. 1. "HW_FLUSH_EN,Write 0x1 to enable HW Marker trigger to generate a Flush"
|
|
newline
|
|
hexmask.long.byte 0xE0 8.--11. 1. "7-5,Write 0x1 to enable HW Marker trigger to generate a Marker"
|
|
newline
|
|
bitfld.long 0xE0 4. "HW_MARKER_EN,Select which bus to capture. 0 : DSS_HWA_DMA0 1 : DSS_HWA_DMA1" "0: DSS_HWA_DMA0,1: DSS_HWA_DMA1"
|
|
newline
|
|
bitfld.long 0xE0 2. "PORT_SEL,Chop of the sign extension bits [15:12] for every 16 bits of data. 0 : Send all 16 bits 1 : Send lower 12 of 16 bits" "0: Send all 16 bits,1: Send lower 12 of 16 bits"
|
|
newline
|
|
bitfld.long 0xE0 1. "CROP_EN,Select which bus to capture. 0 : Read Bus 1 : Write Bus" "0: Read Bus,1: Write Bus"
|
|
newline
|
|
bitfld.long 0xE0 0. "SNIF_MODE,Indicates is the sniffer block is active or inactive. 0 : Captuere is Disabled 1 : Sniffer Enabled" "0: Captuere is Disabled,1: Sniffer Enabled"
|
|
line.long 0xE4 "SRC4_RANGE_START0,"
|
|
hexmask.long 0xE4 0.--31. 1. "START,Range 0 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0xE8 "SRC4_RANGE_END0,"
|
|
hexmask.long 0xE8 0.--31. 1. "END,Range 0 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xEC "SRC4_RANGE_START1,"
|
|
hexmask.long 0xEC 0.--31. 1. "START,Range 1 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0xF0 "SRC4_RANGE_END1,"
|
|
hexmask.long 0xF0 0.--31. 1. "END,Range 1 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xF4 "SRC4_RANGE_START2,"
|
|
hexmask.long 0xF4 0.--31. 1. "START,Range 2 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0xF8 "SRC4_RANGE_END2,"
|
|
hexmask.long 0xF8 0.--31. 1. "END,Range 2 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0xFC "SRC4_RANGE_START3,"
|
|
hexmask.long 0xFC 0.--31. 1. "START,Range 3 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x100 "SRC4_RANGE_END3,"
|
|
hexmask.long 0x100 0.--31. 1. "END,Range 3 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x104 "SRC4_SW_TRIGGER,"
|
|
bitfld.long 0x104 4. "FLUSH,Write 0x1 to trigger a Flush. A marker packet will also be inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x104 0. "MARKER,Write 0x1 to insert a Marker" "0,1"
|
|
line.long 0x108 "SRC4_THRESHOLD,"
|
|
hexmask.long.word 0x108 0.--9. 1. "THRESHOLD,The FIFO threshold to trigger writes from the Source FIFO. This value is in multiples of 32 bytes. If SRCx_BW_CTRL_WRITE_MODE is 0x0 then the bits [9:5] of this field need to be programmed to 0x0"
|
|
line.long 0x10C "SRC4_BW_CTRL,"
|
|
bitfld.long 0x10C 28.--30. "PRIORITY,0 : Highest Dynamic Priority 7 : Lowest Dynamic Priority" "0: Highest Dynamic Priority,?,?,?,?,?,?,7: Lowest Dynamic Priority"
|
|
newline
|
|
hexmask.long.byte 0x10C 16.--20. 1. "BURST_SIZE,The burst_size is the minimum size for which the SRC will keep arbitration once it wins . The value in multiples of 32 bytes"
|
|
newline
|
|
hexmask.long.byte 0x10C 4.--11. 1. "BURST_NUM,The FIFO threshold to trigger writes from the Source FIFO. Value to be aligned to 32 bytes [4:0] should be 0x0"
|
|
newline
|
|
bitfld.long 0x10C 0. "WRITE_MODE,0 : Send data equivalent to burst_count * burst_size 1 : Send data equivalent to threshold size. This can be set only if threshold is less than 1024 bytes" "0: Send data equivalent to burst_count * burst_size,1: Send data equivalent to threshold size"
|
|
line.long 0x110 "SRC4_CHANNEL,"
|
|
hexmask.long 0x110 0.--31. 1. "ADDR,Configure the STM Channel Number"
|
|
line.long 0x114 "SRC4_CHANNEL_CFG,"
|
|
bitfld.long 0x114 4. "NONDATA_TIMESTAMPE,Selects whether the Non Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x114 3. "NONDATA_GUARANTEE,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
newline
|
|
bitfld.long 0x114 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x114 1. "DATA_MARKED,Selects whether the Data access for the Source is marked 0 : Un-Marked 1 : Marked" "0: Un-Marked,1: Marked"
|
|
newline
|
|
bitfld.long 0x114 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
line.long 0x118 "SRC5_CTRL,"
|
|
bitfld.long 0x118 20. "GEN_MARKER_ON_FLUSH,Write 0x1 to generate a marker on Flush trigger" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x118 16.--19. 1. "RANGE_EN,Enable the corresponding range for data capture. Bit 0 : 0: Range 0 is disabled 1 : Range 0 is enableld"
|
|
newline
|
|
hexmask.long.byte 0x118 12.--15. 1. "HW_FLUSH_EN,Write 0x1 to enable HW Marker trigger to generate a Flush"
|
|
newline
|
|
hexmask.long.byte 0x118 8.--11. 1. "HW_MARKER_EN,Write 0x1 to enable HW Marker trigger to generate a Marker"
|
|
newline
|
|
bitfld.long 0x118 2. "CROP_EN,Chop of the sign extension bits [15:12] for every 16 bits of data. 0 : Send all 16 bits 1 : Send lower 12 of 16 bits" "0: Send all 16 bits,1: Send lower 12 of 16 bits"
|
|
newline
|
|
bitfld.long 0x118 1. "SNIF_MODE,Select which bus to capture. 0 : Read Bus 1 : Write Bus" "0: Read Bus,1: Write Bus"
|
|
newline
|
|
bitfld.long 0x118 0. "ENABLE,Indicates is the sniffer block is active or inactive. 0 : Captuere is Disabled 1 : Sniffer Enabled" "0: Captuere is Disabled,1: Sniffer Enabled"
|
|
line.long 0x11C "SRC5_RANGE_START0,"
|
|
hexmask.long 0x11C 0.--31. 1. "START,Range 0 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x120 "SRC5_RANGE_END0,"
|
|
hexmask.long 0x120 0.--31. 1. "END,Range 0 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x124 "SRC5_RANGE_START1,"
|
|
hexmask.long 0x124 0.--31. 1. "START,Range 1 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x128 "SRC5_RANGE_END1,"
|
|
hexmask.long 0x128 0.--31. 1. "END,Range 1 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x12C "SRC5_RANGE_START2,"
|
|
hexmask.long 0x12C 0.--31. 1. "START,Range 2 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x130 "SRC5_RANGE_END2,"
|
|
hexmask.long 0x130 0.--31. 1. "END,Range 2 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x134 "SRC5_RANGE_START3,"
|
|
hexmask.long 0x134 0.--31. 1. "START,Range 3 Start address OR Start param number for HWA which needs to be captured"
|
|
line.long 0x138 "SRC5_RANGE_END3,"
|
|
hexmask.long 0x138 0.--31. 1. "END,Range 3 End address OR End param number for HWA which needs to be captured"
|
|
line.long 0x13C "SRC5_SW_TRIGGER,"
|
|
bitfld.long 0x13C 4. "FLUSH,Write 0x1 to trigger a Flush. A marker packet will also be inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x13C 0. "MARKER,Write 0x1 to insert a Marker" "0,1"
|
|
line.long 0x140 "SRC5_THRESHOLD,"
|
|
hexmask.long.word 0x140 0.--9. 1. "THRESHOLD,The FIFO threshold to trigger writes from the Source FIFO. This value is in multiples of 32 bytes. If SRCx_BW_CTRL_WRITE_MODE is 0x0 then the bits [9:5] of this field need to be programmed to 0x0"
|
|
line.long 0x144 "SRC5_BW_CTRL,"
|
|
bitfld.long 0x144 28.--30. "PRIORITY,0 : Highest Dynamic Priority 7 : Lowest Dynamic Priority" "0: Highest Dynamic Priority,?,?,?,?,?,?,7: Lowest Dynamic Priority"
|
|
newline
|
|
hexmask.long.byte 0x144 16.--20. 1. "BURST_SIZE,The burst_size is the minimum size for which the SRC will keep arbitration once it wins . The value in multiples of 32 bytes"
|
|
newline
|
|
hexmask.long.byte 0x144 4.--11. 1. "BURST_NUM,The FIFO threshold to trigger writes from the Source FIFO. Value to be aligned to 32 bytes [4:0] should be 0x0"
|
|
newline
|
|
bitfld.long 0x144 0. "WRITE_MODE,0 : Send data equivalent to burst_count * burst_size 1 : Send data equivalent to threshold size. This can be set only if threshold is less than 1024 bytes" "0: Send data equivalent to burst_count * burst_size,1: Send data equivalent to threshold size"
|
|
line.long 0x148 "SRC5_CHANNEL,"
|
|
hexmask.long 0x148 0.--31. 1. "ADDR,Configure the STM Channel Number"
|
|
line.long 0x14C "SRC5_CHANNEL_CFG,"
|
|
bitfld.long 0x14C 4. "NONDATA_TIMESTAMPE,Selects whether the Non Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x14C 3. "NONDATA_GUARANTEE,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
newline
|
|
bitfld.long 0x14C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped 0 : No Timestamp 1 : Timestamped" "0: No Timestamp,1: Timestamped"
|
|
newline
|
|
bitfld.long 0x14C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked 0 : Un-Marked 1 : Marked" "0: Un-Marked,1: Marked"
|
|
newline
|
|
bitfld.long 0x14C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing 0 : Time Invariant 1 : Guaranteed" "0: Time Invariant,1: Guaranteed"
|
|
group.long 0x1D4++0x1B
|
|
line.long 0x0 "SRC0_STATUS,"
|
|
hexmask.long.word 0x0 16.--31. 1. "STATUS,Status of the Sniffer for Source 0"
|
|
newline
|
|
bitfld.long 0x0 3. "OVERFLOW_ERR,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FLUSH_ERR,Flush Err is generated on Multiple Flush requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DATA_MISS,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FLUSH_DONE,Flush Done is generated on completion of a flush request" "0,1"
|
|
line.long 0x4 "SRC1_STATUS,"
|
|
hexmask.long.word 0x4 16.--31. 1. "STATUS,Status of the Sniffer for Source 1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVERFLOW_ERR,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FLUSH_ERR,Flush Err is generated on Multiple Flush requests" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DATA_MISS,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FLUSH_DONE,Flush Done is generated on completion of a flush request" "0,1"
|
|
line.long 0x8 "SRC2_STATUS,"
|
|
hexmask.long.word 0x8 16.--31. 1. "STATUS,Status of the Sniffer for Source 2"
|
|
newline
|
|
bitfld.long 0x8 3. "OVERFLOW_ERR,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "FLUSH_ERR,Flush Err is generated on Multiple Flush requests" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DATA_MISS,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "FLUSH_DONE,Flush Done is generated on completion of a flush request" "0,1"
|
|
line.long 0xC "SRC3_STATUS,"
|
|
hexmask.long.word 0xC 16.--31. 1. "STATUS,Status of the Sniffer for Source 3"
|
|
newline
|
|
bitfld.long 0xC 3. "OVERFLOW_ERR,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "FLUSH_ERR,Flush Err is generated on Multiple Flush requests" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "DATA_MISS,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "FLUSH_DONE,Flush Done is generated on completion of a flush request" "0,1"
|
|
line.long 0x10 "SRC4_STATUS,"
|
|
hexmask.long.word 0x10 16.--31. 1. "STATUS,Status of the Sniffer for Source 4"
|
|
newline
|
|
bitfld.long 0x10 3. "TABLE 25-101. SRC4_STATUS REGISTER FIELD DESCRIPTIONS,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "15-4,Flush Err is generated on Multiple Flush requests" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "OVERFLOW_ERR,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "FLUSH_ERR,Flush Done is generated on completion of a flush request" "0,1"
|
|
line.long 0x14 "SRC5_STATUS,"
|
|
hexmask.long.word 0x14 16.--31. 1. "STATUS,Status of the Sniffer for Source 5"
|
|
newline
|
|
bitfld.long 0x14 3. "OVERFLOW_ERR,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "FLUSH_ERR,Flush Err is generated on Multiple Flush requests" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "DATA_MISS,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "FLUSH_DONE,Flush Done is generated on completion of a flush request" "0,1"
|
|
line.long 0x18 "INTERRUPT_MASK,"
|
|
hexmask.long 0x18 0.--31. 1. "MASK,MDO Infra Interrupt Mask"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0xFD0)++0x3
|
|
line.long 0x0 "HW_SPARE_RW$1,"
|
|
hexmask.long 0x0 0.--31. 1. "HW_SPARE_RW0,Reserved for HW R&D"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
rgroup.long ($2+0xFE0)++0x3
|
|
line.long 0x0 "HW_SPARE_RO$1,"
|
|
hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO0,Reserved for HW R&D"
|
|
repeat.end
|
|
group.long 0xFF0++0x7
|
|
line.long 0x0 "HW_SPARE_WPH,"
|
|
hexmask.long 0x0 0.--31. 1. "HW_SPARE_WPH,Reserved for HW R&D"
|
|
line.long 0x4 "HW_SPARE_REC,"
|
|
bitfld.long 0x4 31. "HW_SPARE_REC31,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "HW_SPARE_REC30,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "HW_SPARE_REC29,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "HW_SPARE_REC28,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "HW_SPARE_REC27,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "HW_SPARE_REC26,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "HW_SPARE_REC25,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "HW_SPARE_REC24,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "HW_SPARE_REC23,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "HW_SPARE_REC22,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "HW_SPARE_REC21,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "HW_SPARE_REC20,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "HW_SPARE_REC19,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "HW_SPARE_REC18,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "HW_SPARE_REC17,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "HW_SPARE_REC16,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "HW_SPARE_REC15,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "HW_SPARE_REC14,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "HW_SPARE_REC13,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "HW_SPARE_REC12,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "HW_SPARE_REC11,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "HW_SPARE_REC10,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "HW_SPARE_REC9,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "HW_SPARE_REC8,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "HW_SPARE_REC7,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "HW_SPARE_REC6,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "HW_SPARE_REC5,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "HW_SPARE_REC4,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "HW_SPARE_REC3,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "HW_SPARE_REC2,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HW_SPARE_REC1,Reserved for HW R&D" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HW_SPARE_REC0,Reserved for HW R&D" "0,1"
|
|
group.long 0x1008++0x1B
|
|
line.long 0x0 "LOCK0_KICK0,- KICK0 component"
|
|
hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component"
|
|
line.long 0x4 "LOCK0_KICK1,- KICK1 component"
|
|
hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component"
|
|
line.long 0x8 "intr_raw_status,Interrupt Raw Status/Set Register"
|
|
bitfld.long 0x8 3. "proxy_err,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "kick_err,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "addr_err,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "prot_err,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0xC "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
|
|
bitfld.long 0xC 3. "enabled_proxy_err,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "enabled_kick_err,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "enabled_addr_err,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "enabled_prot_err,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1"
|
|
line.long 0x10 "intr_enable,Interrupt Enable register"
|
|
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
|
|
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1"
|
|
line.long 0x18 "eoi,EOI register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value. Write this with interrupt distribution value in the chip."
|
|
rgroup.long 0x1024++0xB
|
|
line.long 0x0 "fault_address,Fault Address register"
|
|
hexmask.long 0x0 0.--31. 1. "fault_addr,Fault Address."
|
|
line.long 0x4 "fault_type_status,Fault Type Status register"
|
|
bitfld.long 0x4 6. "fault_ns,Non-secure access." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "fault_type,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir.."
|
|
line.long 0x8 "fault_attr_status,Fault Attribute Status register"
|
|
hexmask.long.word 0x8 20.--31. 1. "fault_xid,XID."
|
|
newline
|
|
hexmask.long.word 0x8 8.--19. 1. "fault_routeid,Route ID."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "fault_privid,Privilege ID."
|
|
wgroup.long 0x1030++0x3
|
|
line.long 0x0 "fault_clear,Fault Clear register"
|
|
bitfld.long 0x0 0. "fault_clr,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1"
|
|
tree.end
|
|
tree "TOP_PBIST"
|
|
base ad:0x2F79400
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "PBIST_A$1,Variable Address Register0"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "PBIST_L$1,Variable Loop Count Register L0"
|
|
repeat.end
|
|
group.long 0x120++0x7
|
|
line.long 0x0 "PBIST_DD10,DD0 Data Register 16 (D0)"
|
|
line.long 0x4 "PBIST_DE10,DE0 Data Register 16 (D0)"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x130)++0x3
|
|
line.long 0x0 "PBIST_CA$1,Constant Address Register0"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list 0x0 0x4 0x8 0xC)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "PBIST_CL$1,Constant Loop Count Register0"
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x4)
|
|
group.long ($2+0x150)++0x3
|
|
line.long 0x0 "PBIST_CI$1,Constant Increment Register0"
|
|
repeat.end
|
|
repeat 2. (list 0x2 0x3)(list 0x0 0x4)
|
|
group.word ($2+0x158)++0x1
|
|
line.word 0x0 "PBIST_CI$1,Constant Increment Register2"
|
|
hexmask.word 0x0 0.--15. 1. "PBIST_CI2,TI Internal Register.Reserved for HW RnD"
|
|
repeat.end
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
hexmask.long.byte 0x0 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
hexmask.long.byte 0x0 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
group.word 0x164++0x1
|
|
line.word 0x0 "PBIST_DLR,Datalogger 0"
|
|
hexmask.word.byte 0x0 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode. When in this mode ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config write to both this bit and bit [2] of the Datalogger Register.."
|
|
hexmask.word.byte 0x0 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM [3] : Do not change this bit from its default value of 1 [4] : Config.."
|
|
group.byte 0x168++0x0
|
|
line.byte 0x0 "PBIST_CMS,Clock mux select"
|
|
hexmask.byte 0x0 0.--3. 1. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset."
|
|
group.byte 0x16C++0x0
|
|
line.byte 0x0 "PBIST_PC,Program Control"
|
|
hexmask.byte 0x0 0.--4. 1. "PBIST_PC,TI Internal Register.Reserved for HW RnD"
|
|
repeat 2. (list 0x1 0x4)(list 0x0 0x4)
|
|
group.long ($2+0x170)++0x3
|
|
line.long 0x0 "PBIST_SCR$1,Address Scramble 0 -3"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
|
|
repeat.end
|
|
group.long 0x178++0x3
|
|
line.long 0x0 "PBIST_CS,Chip Select 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
|
|
group.byte 0x17C++0x0
|
|
line.byte 0x0 "PBIST_FDLY,Fail Delay"
|
|
hexmask.byte 0x0 0.--7. 1. "PBIST_FDLY,TI Internal Register.Reserved for HW RnD"
|
|
group.byte 0x180++0x0
|
|
line.byte 0x0 "PBIST_PACT,Pbist Active"
|
|
bitfld.byte 0x0 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used as the clock gate enable. As long as this bit is 0 any access to PBIST will not go.." "0: Disable internal PBIST clocks Value,1: Enable internal PBIST clocks"
|
|
group.byte 0x184++0x0
|
|
line.byte 0x0 "PBIST_ID,PBIST ID"
|
|
hexmask.byte 0x0 0.--4. 1. "PBIST_ID,PBIST ID. This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. The value of this register does not affect the functionality of the CPU interface."
|
|
group.long 0x188++0x3
|
|
line.long 0x0 "PBIST_OVR,PBIST Overrides"
|
|
rgroup.byte 0x190++0x0
|
|
line.byte 0x0 "PBIST_FSFR0,Fail status fail - port 0"
|
|
bitfld.byte 0x0 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure" "0: No failure occurred Value,1: Indicates a failure"
|
|
rgroup.byte 0x194++0x0
|
|
line.byte 0x0 "PBIST_FSFR1,Fail status fail - port 1"
|
|
bitfld.byte 0x0 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure" "0: No failure occurred Value,1: Indicates a failure"
|
|
rgroup.byte 0x198++0x0
|
|
line.byte 0x0 "PBIST_FSRCR0,Fail Count fail - port 0"
|
|
hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test. The PBIST controller stops executing the memory self-test whenever a failure occurs in any memory instance for any of the.."
|
|
rgroup.byte 0x19C++0x0
|
|
line.byte 0x0 "PBIST_FSRCR1,Fail Count fail - port 1"
|
|
hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test. The PBIST controller stops executing the memory self-test whenever a failure occurs in any memory instance for any of the.."
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "PBIST_FSRA0,Fail status address - port 0"
|
|
rgroup.word 0x1A4++0x1
|
|
line.word 0x0 "PBIST_FSRA1,Fail status address - port 1"
|
|
hexmask.word 0x0 0.--15. 1. "PBIST_FSRA1,TI Internal Register.Reserved for HW RnD"
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x8)
|
|
rgroup.long ($2+0x1A8)++0x3
|
|
line.long 0x0 "PBIST_FSRDL$1,Fail status Data - port 0"
|
|
hexmask.long 0x0 0.--31. 1. "PBIST_FSRDL0,TI Internal Register.Reserved for HW RnD"
|
|
repeat.end
|
|
group.long 0x1B4++0xB
|
|
line.long 0x0 "PBIST_MARGIN,Margin Mode"
|
|
line.long 0x4 "PBIST_WRENZ,WRENZ"
|
|
line.long 0x8 "PBIST_PGS,PAGE/PGS"
|
|
group.byte 0x1C0++0x0
|
|
line.byte 0x0 "PBIST_ROM,Rom Mask"
|
|
bitfld.byte 0x0 0.--1. "PBIST_ROM,Rom Mask . This two-bit register sets appropriate ROM access modes for the PBIST controller. Value 0h = No information is used from ROM Value 1h = Only RAM Group information from ROM Vaule 2h = Only Algorithm information from ROM Value 3h =.." "0,1,2,3"
|
|
group.long 0x1C4++0xB
|
|
line.long 0x0 "PBIST_ALGO,ROM Algorithm Mask 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
hexmask.long.byte 0x0 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
hexmask.long.byte 0x0 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit enables the corresponding algorithm. Writing a value 0 to the.."
|
|
line.long 0x4 "PBIST_RINFOL,RAM Info Mask Lower 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x4 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
line.long 0x8 "PBIST_RINFOU,RAM Info Mask Upper 0"
|
|
hexmask.long.byte 0x8 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
|
|
hexmask.long.byte 0x8 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
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hexmask.long.byte 0x8 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
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hexmask.long.byte 0x8 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.."
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tree.end
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AUTOINDENT.OFF
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